Merge tag 'phy-for-4.8-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-linus

Kishon writes:

phy: for 4.8 -rc

*) Fix to get host-only mode working in sun4i
*) Fix a compilation error because of missing header file
*) Other minor fixes

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

4 files changed, 202 insertions, 25 deletions

diff --git a/drivers/phy/phy-brcm-sata.c b/drivers/phy/phy-brcm-sata.c
index 18d662610075..8ffc44afdb75 100644
--- a/drivers/phy/phy-brcm-sata.c
+++ b/drivers/phy/phy-brcm-sata.c
@@ -367,7 +367,7 @@ static int brcm_sata_phy_init(struct phy *phy)
                 rc = -ENODEV;
         };
 
-        return 0;
+        return rc;
 }
 
 static const struct phy_ops phy_ops = {
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 0a45bc6088ae..8c7eb335622e 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -40,6 +40,7 @@
 #include <linux/power_supply.h>
 #include <linux/regulator/consumer.h>
 #include <linux/reset.h>
+#include <linux/usb/of.h>
 #include <linux/workqueue.h>
 
 #define REG_ISCR                        0x00
@@ -110,6 +111,7 @@ struct sun4i_usb_phy_cfg {
 struct sun4i_usb_phy_data {
         void __iomem *base;
         const struct sun4i_usb_phy_cfg *cfg;
+        enum usb_dr_mode dr_mode;
         struct mutex mutex;
         struct sun4i_usb_phy {
                 struct phy *phy;
@@ -120,6 +122,7 @@ struct sun4i_usb_phy_data {
                 bool regulator_on;
                 int index;
         } phys[MAX_PHYS];
+        int first_phy;
         /* phy0 / otg related variables */
         struct extcon_dev *extcon;
         bool phy0_init;
@@ -285,16 +288,10 @@ static int sun4i_usb_phy_init(struct phy *_phy)
                 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN);
                 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN);
 
-                if (data->id_det_gpio) {
-                        /* OTG mode, force ISCR and cable state updates */
-                        data->id_det = -1;
-                        data->vbus_det = -1;
-                        queue_delayed_work(system_wq, &data->detect, 0);
-                } else {
-                        /* Host only mode */
-                        sun4i_usb_phy0_set_id_detect(_phy, 0);
-                        sun4i_usb_phy0_set_vbus_detect(_phy, 1);
-                }
+                /* Force ISCR and cable state updates */
+                data->id_det = -1;
+                data->vbus_det = -1;
+                queue_delayed_work(system_wq, &data->detect, 0);
         }
 
         return 0;
@@ -319,6 +316,19 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
         return 0;
 }
 
+static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
+{
+        switch (data->dr_mode) {
+        case USB_DR_MODE_OTG:
+                return gpiod_get_value_cansleep(data->id_det_gpio);
+        case USB_DR_MODE_HOST:
+                return 0;
+        case USB_DR_MODE_PERIPHERAL:
+        default:
+                return 1;
+        }
+}
+
 static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
 {
         if (data->vbus_det_gpio)
@@ -432,7 +442,10 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
         struct phy *phy0 = data->phys[0].phy;
         int id_det, vbus_det, id_notify = 0, vbus_notify = 0;
 
-        id_det = gpiod_get_value_cansleep(data->id_det_gpio);
+        if (phy0 == NULL)
+                return;
+
+        id_det = sun4i_usb_phy0_get_id_det(data);
         vbus_det = sun4i_usb_phy0_get_vbus_det(data);
 
         mutex_lock(&phy0->mutex);
@@ -448,7 +461,8 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
                  * without vbus detection report vbus low for long enough for
                  * the musb-ip to end the current device session.
                  */
-                if (!sun4i_usb_phy0_have_vbus_det(data) && id_det == 0) {
+                if (data->dr_mode == USB_DR_MODE_OTG &&
+                    !sun4i_usb_phy0_have_vbus_det(data) && id_det == 0) {
                         sun4i_usb_phy0_set_vbus_detect(phy0, 0);
                         msleep(200);
                         sun4i_usb_phy0_set_vbus_detect(phy0, 1);
@@ -474,7 +488,8 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
                  * without vbus detection report vbus low for long enough to
                  * the musb-ip to end the current host session.
                  */
-                if (!sun4i_usb_phy0_have_vbus_det(data) && id_det == 1) {
+                if (data->dr_mode == USB_DR_MODE_OTG &&
+                    !sun4i_usb_phy0_have_vbus_det(data) && id_det == 1) {
                         mutex_lock(&phy0->mutex);
                         sun4i_usb_phy0_set_vbus_detect(phy0, 0);
                         msleep(1000);
@@ -519,7 +534,8 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
 {
         struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
 
-        if (args->args[0] >= data->cfg->num_phys)
+        if (args->args[0] < data->first_phy ||
+            args->args[0] >= data->cfg->num_phys)
                 return ERR_PTR(-ENODEV);
 
         return data->phys[args->args[0]].phy;
@@ -593,13 +609,17 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
                         return -EPROBE_DEFER;
         }
 
-        /* vbus_det without id_det makes no sense, and is not supported */
-        if (sun4i_usb_phy0_have_vbus_det(data) && !data->id_det_gpio) {
-                dev_err(dev, "usb0_id_det missing or invalid\n");
-                return -ENODEV;
-        }
-
-        if (data->id_det_gpio) {
+        data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0);
+        switch (data->dr_mode) {
+        case USB_DR_MODE_OTG:
+                /* otg without id_det makes no sense, and is not supported */
+                if (!data->id_det_gpio) {
+                        dev_err(dev, "usb0_id_det missing or invalid\n");
+                        return -ENODEV;
+                }
+                /* fall through */
+        case USB_DR_MODE_HOST:
+        case USB_DR_MODE_PERIPHERAL:
                 data->extcon = devm_extcon_dev_allocate(dev,
                                                         sun4i_usb_phy0_cable);
                 if (IS_ERR(data->extcon))
@@ -610,9 +630,13 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
                         dev_err(dev, "failed to register extcon: %d\n", ret);
                         return ret;
                 }
+                break;
+        default:
+                dev_info(dev, "dr_mode unknown, not registering usb phy0\n");
+                data->first_phy = 1;
         }
 
-        for (i = 0; i < data->cfg->num_phys; i++) {
+        for (i = data->first_phy; i < data->cfg->num_phys; i++) {
                 struct sun4i_usb_phy *phy = data->phys + i;
                 char name[16];
 
diff --git a/drivers/phy/phy-sun9i-usb.c b/drivers/phy/phy-sun9i-usb.c
index ac4f31abefe3..28fce4bce638 100644
--- a/drivers/phy/phy-sun9i-usb.c
+++ b/drivers/phy/phy-sun9i-usb.c
@@ -141,9 +141,9 @@ static int sun9i_usb_phy_probe(struct platform_device *pdev)
                 }
 
                 phy->hsic_clk = devm_clk_get(dev, "hsic_12M");
-                if (IS_ERR(phy->clk)) {
+                if (IS_ERR(phy->hsic_clk)) {
                         dev_err(dev, "failed to get hsic_12M clock\n");
-                        return PTR_ERR(phy->clk);
+                        return PTR_ERR(phy->hsic_clk);
                 }
 
                 phy->reset = devm_reset_control_get(dev, "hsic");
diff --git a/include/linux/mfd/da8xx-cfgchip.h b/include/linux/mfd/da8xx-cfgchip.h
new file mode 100644
index 000000000000..304985e288d2
--- /dev/null
+++ b/include/linux/mfd/da8xx-cfgchip.h
@@ -0,0 +1,153 @@
+/*
+ * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
+ *
+ * Copyright (C) 2016 David Lechner <david@lechnology.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
+#define __LINUX_MFD_DA8XX_CFGCHIP_H
+
+#include <linux/bitops.h>
+
+/* register offset (32-bit registers) */
+#define CFGCHIP(n)                              ((n) * 4)
+
+/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
+#define CFGCHIP0_PLL_MASTER_LOCK                BIT(4)
+#define CFGCHIP0_EDMA30TC1DBS(n)                ((n) << 2)
+#define CFGCHIP0_EDMA30TC1DBS_MASK              CFGCHIP0_EDMA30TC1DBS(0x3)
+#define CFGCHIP0_EDMA30TC1DBS_16                CFGCHIP0_EDMA30TC1DBS(0x0)
+#define CFGCHIP0_EDMA30TC1DBS_32                CFGCHIP0_EDMA30TC1DBS(0x1)
+#define CFGCHIP0_EDMA30TC1DBS_64                CFGCHIP0_EDMA30TC1DBS(0x2)
+#define CFGCHIP0_EDMA30TC0DBS(n)                ((n) << 0)
+#define CFGCHIP0_EDMA30TC0DBS_MASK              CFGCHIP0_EDMA30TC0DBS(0x3)
+#define CFGCHIP0_EDMA30TC0DBS_16                CFGCHIP0_EDMA30TC0DBS(0x0)
+#define CFGCHIP0_EDMA30TC0DBS_32                CFGCHIP0_EDMA30TC0DBS(0x1)
+#define CFGCHIP0_EDMA30TC0DBS_64                CFGCHIP0_EDMA30TC0DBS(0x2)
+
+/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
+#define CFGCHIP1_CAP2SRC(n)                     ((n) << 27)
+#define CFGCHIP1_CAP2SRC_MASK                   CFGCHIP1_CAP2SRC(0x1f)
+#define CFGCHIP1_CAP2SRC_ECAP_PIN               CFGCHIP1_CAP2SRC(0x0)
+#define CFGCHIP1_CAP2SRC_MCASP0_TX              CFGCHIP1_CAP2SRC(0x1)
+#define CFGCHIP1_CAP2SRC_MCASP0_RX              CFGCHIP1_CAP2SRC(0x2)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD   CFGCHIP1_CAP2SRC(0x7)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_RX             CFGCHIP1_CAP2SRC(0x8)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_TX             CFGCHIP1_CAP2SRC(0x9)
+#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC           CFGCHIP1_CAP2SRC(0xa)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD   CFGCHIP1_CAP2SRC(0xb)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_RX             CFGCHIP1_CAP2SRC(0xc)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_TX             CFGCHIP1_CAP2SRC(0xd)
+#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC           CFGCHIP1_CAP2SRC(0xe)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD   CFGCHIP1_CAP2SRC(0xf)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_RX             CFGCHIP1_CAP2SRC(0x10)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_TX             CFGCHIP1_CAP2SRC(0x11)
+#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC           CFGCHIP1_CAP2SRC(0x12)
+#define CFGCHIP1_CAP1SRC(n)                     ((n) << 22)
+#define CFGCHIP1_CAP1SRC_MASK                   CFGCHIP1_CAP1SRC(0x1f)
+#define CFGCHIP1_CAP1SRC_ECAP_PIN               CFGCHIP1_CAP1SRC(0x0)
+#define CFGCHIP1_CAP1SRC_MCASP0_TX              CFGCHIP1_CAP1SRC(0x1)
+#define CFGCHIP1_CAP1SRC_MCASP0_RX              CFGCHIP1_CAP1SRC(0x2)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD   CFGCHIP1_CAP1SRC(0x7)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_RX             CFGCHIP1_CAP1SRC(0x8)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_TX             CFGCHIP1_CAP1SRC(0x9)
+#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC           CFGCHIP1_CAP1SRC(0xa)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD   CFGCHIP1_CAP1SRC(0xb)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_RX             CFGCHIP1_CAP1SRC(0xc)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_TX             CFGCHIP1_CAP1SRC(0xd)
+#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC           CFGCHIP1_CAP1SRC(0xe)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD   CFGCHIP1_CAP1SRC(0xf)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_RX             CFGCHIP1_CAP1SRC(0x10)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_TX             CFGCHIP1_CAP1SRC(0x11)
+#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC           CFGCHIP1_CAP1SRC(0x12)
+#define CFGCHIP1_CAP0SRC(n)                     ((n) << 17)
+#define CFGCHIP1_CAP0SRC_MASK                   CFGCHIP1_CAP0SRC(0x1f)
+#define CFGCHIP1_CAP0SRC_ECAP_PIN               CFGCHIP1_CAP0SRC(0x0)
+#define CFGCHIP1_CAP0SRC_MCASP0_TX              CFGCHIP1_CAP0SRC(0x1)
+#define CFGCHIP1_CAP0SRC_MCASP0_RX              CFGCHIP1_CAP0SRC(0x2)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD   CFGCHIP1_CAP0SRC(0x7)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_RX             CFGCHIP1_CAP0SRC(0x8)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_TX             CFGCHIP1_CAP0SRC(0x9)
+#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC           CFGCHIP1_CAP0SRC(0xa)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD   CFGCHIP1_CAP0SRC(0xb)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_RX             CFGCHIP1_CAP0SRC(0xc)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_TX             CFGCHIP1_CAP0SRC(0xd)
+#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC           CFGCHIP1_CAP0SRC(0xe)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD   CFGCHIP1_CAP0SRC(0xf)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_RX             CFGCHIP1_CAP0SRC(0x10)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_TX             CFGCHIP1_CAP0SRC(0x11)
+#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC           CFGCHIP1_CAP0SRC(0x12)
+#define CFGCHIP1_HPIBYTEAD                      BIT(16)
+#define CFGCHIP1_HPIENA                         BIT(15)
+#define CFGCHIP0_EDMA31TC0DBS(n)                ((n) << 13)
+#define CFGCHIP0_EDMA31TC0DBS_MASK              CFGCHIP0_EDMA31TC0DBS(0x3)
+#define CFGCHIP0_EDMA31TC0DBS_16                CFGCHIP0_EDMA31TC0DBS(0x0)
+#define CFGCHIP0_EDMA31TC0DBS_32                CFGCHIP0_EDMA31TC0DBS(0x1)
+#define CFGCHIP0_EDMA31TC0DBS_64                CFGCHIP0_EDMA31TC0DBS(0x2)
+#define CFGCHIP1_TBCLKSYNC                      BIT(12)
+#define CFGCHIP1_AMUTESEL0(n)                   ((n) << 0)
+#define CFGCHIP1_AMUTESEL0_MASK                 CFGCHIP1_AMUTESEL0(0xf)
+#define CFGCHIP1_AMUTESEL0_LOW                  CFGCHIP1_AMUTESEL0(0x0)
+#define CFGCHIP1_AMUTESEL0_BANK_0               CFGCHIP1_AMUTESEL0(0x1)
+#define CFGCHIP1_AMUTESEL0_BANK_1               CFGCHIP1_AMUTESEL0(0x2)
+#define CFGCHIP1_AMUTESEL0_BANK_2               CFGCHIP1_AMUTESEL0(0x3)
+#define CFGCHIP1_AMUTESEL0_BANK_3               CFGCHIP1_AMUTESEL0(0x4)
+#define CFGCHIP1_AMUTESEL0_BANK_4               CFGCHIP1_AMUTESEL0(0x5)
+#define CFGCHIP1_AMUTESEL0_BANK_5               CFGCHIP1_AMUTESEL0(0x6)
+#define CFGCHIP1_AMUTESEL0_BANK_6               CFGCHIP1_AMUTESEL0(0x7)
+#define CFGCHIP1_AMUTESEL0_BANK_7               CFGCHIP1_AMUTESEL0(0x8)
+
+/* CFGCHIP2 (USB PHY) register bits */
+#define CFGCHIP2_PHYCLKGD                       BIT(17)
+#define CFGCHIP2_VBUSSENSE                      BIT(16)
+#define CFGCHIP2_RESET                          BIT(15)
+#define CFGCHIP2_OTGMODE(n)                     ((n) << 13)
+#define CFGCHIP2_OTGMODE_MASK                   CFGCHIP2_OTGMODE(0x3)
+#define CFGCHIP2_OTGMODE_NO_OVERRIDE            CFGCHIP2_OTGMODE(0x0)
+#define CFGCHIP2_OTGMODE_FORCE_HOST             CFGCHIP2_OTGMODE(0x1)
+#define CFGCHIP2_OTGMODE_FORCE_DEVICE           CFGCHIP2_OTGMODE(0x2)
+#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW    CFGCHIP2_OTGMODE(0x3)
+#define CFGCHIP2_USB1PHYCLKMUX                  BIT(12)
+#define CFGCHIP2_USB2PHYCLKMUX                  BIT(11)
+#define CFGCHIP2_PHYPWRDN                       BIT(10)
+#define CFGCHIP2_OTGPWRDN                       BIT(9)
+#define CFGCHIP2_DATPOL                         BIT(8)
+#define CFGCHIP2_USB1SUSPENDM                   BIT(7)
+#define CFGCHIP2_PHY_PLLON                      BIT(6)
+#define CFGCHIP2_SESENDEN                       BIT(5)
+#define CFGCHIP2_VBDTCTEN                       BIT(4)
+#define CFGCHIP2_REFFREQ(n)                     ((n) << 0)
+#define CFGCHIP2_REFFREQ_MASK                   CFGCHIP2_REFFREQ(0xf)
+#define CFGCHIP2_REFFREQ_12MHZ                  CFGCHIP2_REFFREQ(0x1)
+#define CFGCHIP2_REFFREQ_24MHZ                  CFGCHIP2_REFFREQ(0x2)
+#define CFGCHIP2_REFFREQ_48MHZ                  CFGCHIP2_REFFREQ(0x3)
+#define CFGCHIP2_REFFREQ_19_2MHZ                CFGCHIP2_REFFREQ(0x4)
+#define CFGCHIP2_REFFREQ_38_4MHZ                CFGCHIP2_REFFREQ(0x5)
+#define CFGCHIP2_REFFREQ_13MHZ                  CFGCHIP2_REFFREQ(0x6)
+#define CFGCHIP2_REFFREQ_26MHZ                  CFGCHIP2_REFFREQ(0x7)
+#define CFGCHIP2_REFFREQ_20MHZ                  CFGCHIP2_REFFREQ(0x8)
+#define CFGCHIP2_REFFREQ_40MHZ                  CFGCHIP2_REFFREQ(0x9)
+
+/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
+#define CFGCHIP3_RMII_SEL                       BIT(8)
+#define CFGCHIP3_UPP_TX_CLKSRC                  BIT(6)
+#define CFGCHIP3_PLL1_MASTER_LOCK               BIT(5)
+#define CFGCHIP3_ASYNC3_CLKSRC                  BIT(4)
+#define CFGCHIP3_PRUEVTSEL                      BIT(3)
+#define CFGCHIP3_DIV45PENA                      BIT(2)
+#define CFGCHIP3_EMA_CLKSRC                     BIT(1)
+
+/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
+#define CFGCHIP4_AMUTECLR0                      BIT(0)
+
+#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */