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authorPaul Burton <paul.burton@imgtec.com>2016-10-05 13:18:21 -0400
committerRalf Baechle <ralf@linux-mips.org>2016-10-06 12:04:20 -0400
commit3f5f0a4475e13345326061f00c68f428232ba2bc (patch)
tree0ad2657c668b23aafab4692d83c7156e55ca138f
parenteed0eabd12ef061821cbfa20d903476e07645320 (diff)
MIPS: generic: Convert SEAD-3 to a generic board
Convert the MIPS SEAD-3 board support to be a generic board, supported by generic kernels. Because the SEAD-3 boot protocol was defined long ago and we don't want to force a switch to the UHI protocol, SEAD-3 is added as a legacy board which is detected by reading the REVISION register. This may technically not be a valid memory read & future work will include attempting to handle that gracefully. In practice since SEAD-3 is the only legacy board supported by the generic kernel so far the read will only happen on SEAD-3 boards, and even once Malta is converted the same REVISION register exists there too. Other boards such as Boston, Ci20 & Ci40 will use the UHI boot protocol & thus not run any of the legacy board detect functions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig37
-rw-r--r--arch/mips/Makefile13
-rw-r--r--arch/mips/boot/dts/mti/Makefile2
-rw-r--r--arch/mips/boot/dts/mti/sead3.dts1
-rw-r--r--arch/mips/configs/generic/board-sead-3.config32
-rw-r--r--arch/mips/configs/sead3_defconfig129
-rw-r--r--arch/mips/configs/sead3micro_defconfig122
-rw-r--r--arch/mips/generic/Kconfig7
-rw-r--r--arch/mips/generic/Makefile2
-rw-r--r--arch/mips/generic/board-sead3.c (renamed from arch/mips/mti-sead3/sead3-dtshim.c)106
-rw-r--r--arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h72
-rw-r--r--arch/mips/include/asm/mach-sead3/irq.h9
-rw-r--r--arch/mips/include/asm/mach-sead3/kernel-entry-init.h21
-rw-r--r--arch/mips/include/asm/mach-sead3/sead3-dtshim.h29
-rw-r--r--arch/mips/include/asm/mach-sead3/war.h24
-rw-r--r--arch/mips/mti-sead3/Makefile15
-rw-r--r--arch/mips/mti-sead3/Platform7
-rw-r--r--arch/mips/mti-sead3/sead3-init.c100
-rw-r--r--arch/mips/mti-sead3/sead3-int.c23
-rw-r--r--arch/mips/mti-sead3/sead3-setup.c39
-rw-r--r--arch/mips/mti-sead3/sead3-time.c91
22 files changed, 152 insertions, 730 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 9c1e8f9f854a..f5f1bdb292de 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -19,7 +19,6 @@ platforms += lasat
19platforms += loongson32 19platforms += loongson32
20platforms += loongson64 20platforms += loongson64
21platforms += mti-malta 21platforms += mti-malta
22platforms += mti-sead3
23platforms += netlogic 22platforms += netlogic
24platforms += paravirt 23platforms += paravirt
25platforms += pic32 24platforms += pic32
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 82b45dc9fa4d..a7d9224c2a50 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -546,41 +546,6 @@ config MACH_PIC32
546 Microchip PIC32 is a family of general-purpose 32 bit MIPS core 546 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
547 microcontrollers. 547 microcontrollers.
548 548
549config MIPS_SEAD3
550 bool "MIPS SEAD3 board"
551 select BOOT_ELF32
552 select BOOT_RAW
553 select BUILTIN_DTB
554 select CEVT_R4K
555 select CSRC_R4K
556 select CLKSRC_MIPS_GIC
557 select COMMON_CLK
558 select CPU_MIPSR2_IRQ_VI
559 select CPU_MIPSR2_IRQ_EI
560 select DMA_NONCOHERENT
561 select IRQ_MIPS_CPU
562 select MIPS_GIC
563 select LIBFDT
564 select MIPS_MSC
565 select SYS_HAS_CPU_MIPS32_R1
566 select SYS_HAS_CPU_MIPS32_R2
567 select SYS_HAS_CPU_MIPS32_R6
568 select SYS_HAS_CPU_MIPS64_R1
569 select SYS_SUPPORTS_32BIT_KERNEL
570 select SYS_SUPPORTS_64BIT_KERNEL
571 select SYS_SUPPORTS_BIG_ENDIAN
572 select SYS_SUPPORTS_LITTLE_ENDIAN
573 select SYS_SUPPORTS_SMARTMIPS
574 select SYS_SUPPORTS_MICROMIPS
575 select SYS_SUPPORTS_MIPS16
576 select SYS_SUPPORTS_RELOCATABLE
577 select USB_EHCI_BIG_ENDIAN_DESC
578 select USB_EHCI_BIG_ENDIAN_MMIO
579 select USE_OF
580 help
581 This enables support for the MIPS Technologies SEAD3 evaluation
582 board.
583
584config NEC_MARKEINS 549config NEC_MARKEINS
585 bool "NEC EMMA2RH Mark-eins board" 550 bool "NEC EMMA2RH Mark-eins board"
586 select SOC_EMMA2RH 551 select SOC_EMMA2RH
@@ -2976,7 +2941,7 @@ endchoice
2976choice 2941choice
2977 prompt "Kernel command line type" if !CMDLINE_OVERRIDE 2942 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2978 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \ 2943 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2979 !MIPS_MALTA && !MIPS_SEAD3 && \ 2944 !MIPS_MALTA && \
2980 !CAVIUM_OCTEON_SOC 2945 !CAVIUM_OCTEON_SOC
2981 default MIPS_CMDLINE_FROM_BOOTLOADER 2946 default MIPS_CMDLINE_FROM_BOOTLOADER
2982 2947
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index f3e768a69a52..fbf40d3c8123 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -488,3 +488,16 @@ $(generic_defconfigs):
488# Prevent generic merge_config rules attempting to merge single fragments 488# Prevent generic merge_config rules attempting to merge single fragments
489# 489#
490$(generic_config_dir)/%.config: ; 490$(generic_config_dir)/%.config: ;
491
492#
493# Legacy defconfig compatibility - these targets used to be real defconfigs but
494# now that the boards have been converted to use the generic kernel they are
495# wrappers around the generic rules above.
496#
497.PHONY: sead3_defconfig
498sead3_defconfig:
499 $(Q)$(MAKE) 32r2el_defconfig BOARDS=sead-3
500
501.PHONY: sead3micro_defconfig
502sead3micro_defconfig:
503 $(Q)$(MAKE) micro32r2el_defconfig BOARDS=sead-3
diff --git a/arch/mips/boot/dts/mti/Makefile b/arch/mips/boot/dts/mti/Makefile
index 144d776cc9f2..fcabd69b7030 100644
--- a/arch/mips/boot/dts/mti/Makefile
+++ b/arch/mips/boot/dts/mti/Makefile
@@ -1,5 +1,5 @@
1dtb-$(CONFIG_MIPS_MALTA) += malta.dtb 1dtb-$(CONFIG_MIPS_MALTA) += malta.dtb
2dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb 2dtb-$(CONFIG_LEGACY_BOARD_SEAD3) += sead3.dtb
3 3
4obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) 4obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
5 5
diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts
index 2579ca51c0b6..b112879a5d9d 100644
--- a/arch/mips/boot/dts/mti/sead3.dts
+++ b/arch/mips/boot/dts/mti/sead3.dts
@@ -10,6 +10,7 @@
10 #address-cells = <1>; 10 #address-cells = <1>;
11 #size-cells = <1>; 11 #size-cells = <1>;
12 compatible = "mti,sead-3"; 12 compatible = "mti,sead-3";
13 model = "MIPS SEAD-3";
13 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
14 15
15 chosen { 16 chosen {
diff --git a/arch/mips/configs/generic/board-sead-3.config b/arch/mips/configs/generic/board-sead-3.config
new file mode 100644
index 000000000000..3b5e1ac579eb
--- /dev/null
+++ b/arch/mips/configs/generic/board-sead-3.config
@@ -0,0 +1,32 @@
1CONFIG_LEGACY_BOARD_SEAD3=y
2
3CONFIG_AUXDISPLAY=y
4CONFIG_IMG_ASCII_LCD=y
5
6CONFIG_NEW_LEDS=y
7CONFIG_LEDS_CLASS=y
8CONFIG_LEDS_SYSCON=y
9
10CONFIG_MMC=y
11CONFIG_MMC_SPI=y
12
13CONFIG_MTD=y
14CONFIG_MTD_BLOCK=y
15CONFIG_MTD_CFI=y
16CONFIG_MTD_CFI_INTELEXT=y
17CONFIG_MTD_OF_PARTS=y
18CONFIG_MTD_PHYSMAP=y
19CONFIG_MTD_PHYSMAP_OF=y
20CONFIG_MTD_UBI=y
21CONFIG_MTD_UBI_GLUEBI=y
22
23CONFIG_NETDEVICES=y
24CONFIG_SMSC911X=y
25CONFIG_SMSC_PHY=y
26
27CONFIG_SERIAL_8250=y
28CONFIG_SERIAL_8250_CONSOLE=y
29CONFIG_SERIAL_OF_PLATFORM=y
30
31CONFIG_USB=y
32CONFIG_USB_EHCI_HCD=y
diff --git a/arch/mips/configs/sead3_defconfig b/arch/mips/configs/sead3_defconfig
deleted file mode 100644
index ab4c465d8025..000000000000
--- a/arch/mips/configs/sead3_defconfig
+++ /dev/null
@@ -1,129 +0,0 @@
1CONFIG_MIPS_SEAD3=y
2CONFIG_CPU_LITTLE_ENDIAN=y
3CONFIG_CPU_MIPS32_R2=y
4CONFIG_HZ_100=y
5CONFIG_SYSVIPC=y
6CONFIG_POSIX_MQUEUE=y
7CONFIG_NO_HZ=y
8CONFIG_HIGH_RES_TIMERS=y
9CONFIG_IKCONFIG=y
10CONFIG_IKCONFIG_PROC=y
11CONFIG_LOG_BUF_SHIFT=15
12CONFIG_EMBEDDED=y
13CONFIG_SLAB=y
14CONFIG_PROFILING=y
15CONFIG_OPROFILE=y
16CONFIG_MODULES=y
17# CONFIG_BLK_DEV_BSG is not set
18CONFIG_CMDLINE_BOOL=y
19CONFIG_CMDLINE="earlycon"
20# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
21CONFIG_NET=y
22CONFIG_PACKET=y
23CONFIG_UNIX=y
24CONFIG_INET=y
25CONFIG_IP_PNP=y
26CONFIG_IP_PNP_DHCP=y
27CONFIG_IP_PNP_BOOTP=y
28# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
29# CONFIG_INET_XFRM_MODE_TUNNEL is not set
30# CONFIG_INET_XFRM_MODE_BEET is not set
31# CONFIG_INET_LRO is not set
32# CONFIG_INET_DIAG is not set
33# CONFIG_IPV6 is not set
34# CONFIG_WIRELESS is not set
35CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
36CONFIG_DEVTMPFS=y
37CONFIG_MTD=y
38CONFIG_MTD_BLOCK=y
39CONFIG_MTD_CFI=y
40CONFIG_MTD_CFI_INTELEXT=y
41CONFIG_MTD_PHYSMAP=y
42CONFIG_MTD_UBI=y
43CONFIG_MTD_UBI_GLUEBI=y
44CONFIG_OF=y
45CONFIG_BLK_DEV_LOOP=y
46CONFIG_BLK_DEV_CRYPTOLOOP=m
47CONFIG_SCSI=y
48# CONFIG_SCSI_PROC_FS is not set
49CONFIG_BLK_DEV_SD=y
50CONFIG_CHR_DEV_SG=y
51# CONFIG_SCSI_LOWLEVEL is not set
52CONFIG_NETDEVICES=y
53CONFIG_SMSC911X=y
54# CONFIG_NET_VENDOR_WIZNET is not set
55CONFIG_MARVELL_PHY=y
56CONFIG_DAVICOM_PHY=y
57CONFIG_QSEMI_PHY=y
58CONFIG_LXT_PHY=y
59CONFIG_CICADA_PHY=y
60CONFIG_VITESSE_PHY=y
61CONFIG_SMSC_PHY=y
62CONFIG_BROADCOM_PHY=y
63CONFIG_ICPLUS_PHY=y
64# CONFIG_WLAN is not set
65# CONFIG_INPUT_MOUSEDEV is not set
66# CONFIG_INPUT_KEYBOARD is not set
67# CONFIG_INPUT_MOUSE is not set
68# CONFIG_SERIO is not set
69# CONFIG_CONSOLE_TRANSLATIONS is not set
70CONFIG_VT_HW_CONSOLE_BINDING=y
71CONFIG_LEGACY_PTY_COUNT=32
72CONFIG_SERIAL_8250=y
73CONFIG_SERIAL_8250_CONSOLE=y
74CONFIG_SERIAL_8250_NR_UARTS=2
75CONFIG_SERIAL_8250_RUNTIME_UARTS=2
76CONFIG_SERIAL_OF_PLATFORM=y
77# CONFIG_HW_RANDOM is not set
78CONFIG_I2C=y
79# CONFIG_I2C_COMPAT is not set
80CONFIG_I2C_CHARDEV=y
81# CONFIG_I2C_HELPER_AUTO is not set
82CONFIG_SPI=y
83CONFIG_POWER_RESET=y
84CONFIG_POWER_RESET_RESTART=y
85CONFIG_POWER_RESET_SYSCON=y
86CONFIG_SENSORS_ADT7475=y
87CONFIG_BACKLIGHT_LCD_SUPPORT=y
88CONFIG_LCD_CLASS_DEVICE=y
89CONFIG_BACKLIGHT_CLASS_DEVICE=y
90# CONFIG_VGA_CONSOLE is not set
91CONFIG_USB=y
92CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
93CONFIG_USB_EHCI_HCD=y
94CONFIG_USB_EHCI_ROOT_HUB_TT=y
95CONFIG_USB_STORAGE=y
96CONFIG_MMC=y
97CONFIG_MMC_DEBUG=y
98CONFIG_MMC_SPI=y
99CONFIG_NEW_LEDS=y
100CONFIG_LEDS_CLASS=y
101CONFIG_LEDS_SYSCON=y
102CONFIG_LEDS_TRIGGERS=y
103CONFIG_LEDS_TRIGGER_HEARTBEAT=y
104CONFIG_RTC_CLASS=y
105CONFIG_RTC_DRV_M41T80=y
106CONFIG_EXT3_FS=y
107# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
108CONFIG_XFS_FS=y
109CONFIG_XFS_QUOTA=y
110CONFIG_XFS_POSIX_ACL=y
111CONFIG_QUOTA=y
112# CONFIG_PRINT_QUOTA_WARNING is not set
113CONFIG_MSDOS_FS=m
114CONFIG_VFAT_FS=m
115CONFIG_TMPFS=y
116CONFIG_JFFS2_FS=y
117CONFIG_NFS_FS=y
118CONFIG_ROOT_NFS=y
119CONFIG_NLS_CODEPAGE_437=y
120CONFIG_NLS_ASCII=y
121CONFIG_NLS_ISO8859_1=y
122CONFIG_NLS_ISO8859_15=y
123CONFIG_NLS_UTF8=y
124# CONFIG_FTRACE is not set
125CONFIG_CRYPTO_CBC=y
126CONFIG_CRYPTO_ECB=y
127CONFIG_CRYPTO_ARC4=y
128# CONFIG_CRYPTO_ANSI_CPRNG is not set
129# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/configs/sead3micro_defconfig b/arch/mips/configs/sead3micro_defconfig
deleted file mode 100644
index cd91a775c74e..000000000000
--- a/arch/mips/configs/sead3micro_defconfig
+++ /dev/null
@@ -1,122 +0,0 @@
1CONFIG_MIPS_SEAD3=y
2CONFIG_CPU_LITTLE_ENDIAN=y
3CONFIG_CPU_MIPS32_R2=y
4CONFIG_CPU_MICROMIPS=y
5CONFIG_HZ_100=y
6CONFIG_SYSVIPC=y
7CONFIG_POSIX_MQUEUE=y
8CONFIG_NO_HZ=y
9CONFIG_HIGH_RES_TIMERS=y
10CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y
12CONFIG_LOG_BUF_SHIFT=15
13CONFIG_EMBEDDED=y
14CONFIG_SLAB=y
15CONFIG_PROFILING=y
16CONFIG_OPROFILE=y
17CONFIG_MODULES=y
18# CONFIG_BLK_DEV_BSG is not set
19# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
20CONFIG_NET=y
21CONFIG_PACKET=y
22CONFIG_UNIX=y
23CONFIG_INET=y
24CONFIG_IP_PNP=y
25CONFIG_IP_PNP_DHCP=y
26CONFIG_IP_PNP_BOOTP=y
27# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
28# CONFIG_INET_XFRM_MODE_TUNNEL is not set
29# CONFIG_INET_XFRM_MODE_BEET is not set
30# CONFIG_INET_LRO is not set
31# CONFIG_INET_DIAG is not set
32# CONFIG_IPV6 is not set
33# CONFIG_WIRELESS is not set
34CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
35CONFIG_DEVTMPFS=y
36CONFIG_MTD=y
37CONFIG_MTD_BLOCK=y
38CONFIG_MTD_CFI=y
39CONFIG_MTD_CFI_INTELEXT=y
40CONFIG_MTD_PHYSMAP=y
41CONFIG_MTD_UBI=y
42CONFIG_MTD_UBI_GLUEBI=y
43CONFIG_BLK_DEV_LOOP=y
44CONFIG_BLK_DEV_CRYPTOLOOP=m
45CONFIG_SCSI=y
46# CONFIG_SCSI_PROC_FS is not set
47CONFIG_BLK_DEV_SD=y
48CONFIG_CHR_DEV_SG=y
49# CONFIG_SCSI_LOWLEVEL is not set
50CONFIG_NETDEVICES=y
51CONFIG_SMSC911X=y
52# CONFIG_NET_VENDOR_WIZNET is not set
53CONFIG_MARVELL_PHY=y
54CONFIG_DAVICOM_PHY=y
55CONFIG_QSEMI_PHY=y
56CONFIG_LXT_PHY=y
57CONFIG_CICADA_PHY=y
58CONFIG_VITESSE_PHY=y
59CONFIG_SMSC_PHY=y
60CONFIG_BROADCOM_PHY=y
61CONFIG_ICPLUS_PHY=y
62# CONFIG_WLAN is not set
63# CONFIG_INPUT_MOUSEDEV is not set
64# CONFIG_INPUT_KEYBOARD is not set
65# CONFIG_INPUT_MOUSE is not set
66# CONFIG_SERIO is not set
67# CONFIG_CONSOLE_TRANSLATIONS is not set
68CONFIG_VT_HW_CONSOLE_BINDING=y
69CONFIG_LEGACY_PTY_COUNT=32
70CONFIG_SERIAL_8250=y
71CONFIG_SERIAL_8250_CONSOLE=y
72CONFIG_SERIAL_8250_NR_UARTS=2
73CONFIG_SERIAL_8250_RUNTIME_UARTS=2
74# CONFIG_HW_RANDOM is not set
75CONFIG_I2C=y
76# CONFIG_I2C_COMPAT is not set
77CONFIG_I2C_CHARDEV=y
78# CONFIG_I2C_HELPER_AUTO is not set
79CONFIG_SPI=y
80CONFIG_SENSORS_ADT7475=y
81CONFIG_BACKLIGHT_LCD_SUPPORT=y
82CONFIG_LCD_CLASS_DEVICE=y
83CONFIG_BACKLIGHT_CLASS_DEVICE=y
84# CONFIG_VGA_CONSOLE is not set
85CONFIG_USB=y
86CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
87CONFIG_USB_EHCI_HCD=y
88CONFIG_USB_EHCI_ROOT_HUB_TT=y
89CONFIG_USB_STORAGE=y
90CONFIG_MMC=y
91CONFIG_MMC_DEBUG=y
92CONFIG_MMC_SPI=y
93CONFIG_NEW_LEDS=y
94CONFIG_LEDS_CLASS=y
95CONFIG_LEDS_TRIGGERS=y
96CONFIG_LEDS_TRIGGER_HEARTBEAT=y
97CONFIG_RTC_CLASS=y
98CONFIG_RTC_DRV_M41T80=y
99CONFIG_EXT3_FS=y
100# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
101CONFIG_XFS_FS=y
102CONFIG_XFS_QUOTA=y
103CONFIG_XFS_POSIX_ACL=y
104CONFIG_QUOTA=y
105# CONFIG_PRINT_QUOTA_WARNING is not set
106CONFIG_MSDOS_FS=m
107CONFIG_VFAT_FS=m
108CONFIG_TMPFS=y
109CONFIG_JFFS2_FS=y
110CONFIG_NFS_FS=y
111CONFIG_ROOT_NFS=y
112CONFIG_NLS_CODEPAGE_437=y
113CONFIG_NLS_ASCII=y
114CONFIG_NLS_ISO8859_1=y
115CONFIG_NLS_ISO8859_15=y
116CONFIG_NLS_UTF8=y
117# CONFIG_FTRACE is not set
118CONFIG_CRYPTO_CBC=y
119CONFIG_CRYPTO_ECB=y
120CONFIG_CRYPTO_ARC4=y
121# CONFIG_CRYPTO_ANSI_CPRNG is not set
122# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index baddb0646b23..a606b3f9196c 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -9,4 +9,11 @@ config LEGACY_BOARDS
9 kernel is booted without being provided with an FDT via the UHI 9 kernel is booted without being provided with an FDT via the UHI
10 boot protocol. 10 boot protocol.
11 11
12config LEGACY_BOARD_SEAD3
13 bool "Support MIPS SEAD-3 boards"
14 select LEGACY_BOARDS
15 help
16 Enable this to include support for booting on MIPS SEAD-3 FPGA-based
17 development boards, which boot using a legacy boot protocol.
18
12endif 19endif
diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
index 26e64207f7ad..7c66494151db 100644
--- a/arch/mips/generic/Makefile
+++ b/arch/mips/generic/Makefile
@@ -11,3 +11,5 @@
11obj-y += init.o 11obj-y += init.o
12obj-y += irq.o 12obj-y += irq.o
13obj-y += proc.o 13obj-y += proc.o
14
15obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
diff --git a/arch/mips/mti-sead3/sead3-dtshim.c b/arch/mips/generic/board-sead3.c
index d6b0708d7a6f..f4ae0584a33b 100644
--- a/arch/mips/mti-sead3/sead3-dtshim.c
+++ b/arch/mips/generic/board-sead3.c
@@ -4,11 +4,11 @@
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your 7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version. 8 * option) any later version.
9 */ 9 */
10 10
11#define pr_fmt(fmt) "sead3-dtshim: " fmt 11#define pr_fmt(fmt) "sead3: " fmt
12 12
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/libfdt.h> 14#include <linux/libfdt.h>
@@ -16,13 +16,49 @@
16 16
17#include <asm/fw/fw.h> 17#include <asm/fw/fw.h>
18#include <asm/io.h> 18#include <asm/io.h>
19#include <asm/machine.h>
19 20
20#define SEAD_CONFIG CKSEG1ADDR(0x1b100110) 21#define SEAD_CONFIG CKSEG1ADDR(0x1b100110)
21#define SEAD_CONFIG_GIC_PRESENT BIT(1) 22#define SEAD_CONFIG_GIC_PRESENT BIT(1)
22 23
23static unsigned char fdt_buf[16 << 10] __initdata; 24#define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
25#define MIPS_REVISION_MACHINE (0xf << 4)
26#define MIPS_REVISION_MACHINE_SEAD3 (0x4 << 4)
24 27
25static int append_memory(void *fdt) 28static __init bool sead3_detect(void)
29{
30 uint32_t rev;
31
32 rev = __raw_readl((void *)MIPS_REVISION);
33 return (rev & MIPS_REVISION_MACHINE) == MIPS_REVISION_MACHINE_SEAD3;
34}
35
36static __init int append_cmdline(void *fdt)
37{
38 int err, chosen_off;
39
40 /* find or add chosen node */
41 chosen_off = fdt_path_offset(fdt, "/chosen");
42 if (chosen_off == -FDT_ERR_NOTFOUND)
43 chosen_off = fdt_path_offset(fdt, "/chosen@0");
44 if (chosen_off == -FDT_ERR_NOTFOUND)
45 chosen_off = fdt_add_subnode(fdt, 0, "chosen");
46 if (chosen_off < 0) {
47 pr_err("Unable to find or add DT chosen node: %d\n",
48 chosen_off);
49 return chosen_off;
50 }
51
52 err = fdt_setprop_string(fdt, chosen_off, "bootargs", fw_getcmdline());
53 if (err) {
54 pr_err("Unable to set bootargs property: %d\n", err);
55 return err;
56 }
57
58 return 0;
59}
60
61static __init int append_memory(void *fdt)
26{ 62{
27 unsigned long phys_memsize, memsize; 63 unsigned long phys_memsize, memsize;
28 __be32 mem_array[2]; 64 __be32 mem_array[2];
@@ -89,7 +125,7 @@ static int append_memory(void *fdt)
89 return 0; 125 return 0;
90} 126}
91 127
92static int remove_gic(void *fdt) 128static __init int remove_gic(void *fdt)
93{ 129{
94 const unsigned int cpu_ehci_int = 2; 130 const unsigned int cpu_ehci_int = 2;
95 const unsigned int cpu_uart_int = 4; 131 const unsigned int cpu_uart_int = 4;
@@ -163,7 +199,7 @@ static int remove_gic(void *fdt)
163 return err; 199 return err;
164 } 200 }
165 201
166 ehci_off = fdt_node_offset_by_compatible(fdt, -1, "mti,sead3-ehci"); 202 ehci_off = fdt_node_offset_by_compatible(fdt, -1, "generic-ehci");
167 if (ehci_off < 0) { 203 if (ehci_off < 0) {
168 pr_err("unable to find EHCI DT node: %d\n", ehci_off); 204 pr_err("unable to find EHCI DT node: %d\n", ehci_off);
169 return ehci_off; 205 return ehci_off;
@@ -178,7 +214,7 @@ static int remove_gic(void *fdt)
178 return 0; 214 return 0;
179} 215}
180 216
181static int serial_config(void *fdt) 217static __init int serial_config(void *fdt)
182{ 218{
183 const char *yamontty, *mode_var; 219 const char *yamontty, *mode_var;
184 char mode_var_name[9], path[18], parity; 220 char mode_var_name[9], path[18], parity;
@@ -257,21 +293,28 @@ static int serial_config(void *fdt)
257 return 0; 293 return 0;
258} 294}
259 295
260void __init *sead3_dt_shim(void *fdt) 296static __init const void *sead3_fixup_fdt(const void *fdt,
297 const void *match_data)
261{ 298{
299 static unsigned char fdt_buf[16 << 10] __initdata;
262 int err; 300 int err;
263 301
264 if (fdt_check_header(fdt)) 302 if (fdt_check_header(fdt))
265 panic("Corrupt DT"); 303 panic("Corrupt DT");
266 304
267 /* if this isn't SEAD3, leave the DT alone */ 305 /* if this isn't SEAD3, something went wrong */
268 if (fdt_node_check_compatible(fdt, 0, "mti,sead-3")) 306 BUG_ON(fdt_node_check_compatible(fdt, 0, "mti,sead-3"));
269 return fdt; 307
308 fw_init_cmdline();
270 309
271 err = fdt_open_into(fdt, fdt_buf, sizeof(fdt_buf)); 310 err = fdt_open_into(fdt, fdt_buf, sizeof(fdt_buf));
272 if (err) 311 if (err)
273 panic("Unable to open FDT: %d", err); 312 panic("Unable to open FDT: %d", err);
274 313
314 err = append_cmdline(fdt_buf);
315 if (err)
316 panic("Unable to patch FDT: %d", err);
317
275 err = append_memory(fdt_buf); 318 err = append_memory(fdt_buf);
276 if (err) 319 if (err)
277 panic("Unable to patch FDT: %d", err); 320 panic("Unable to patch FDT: %d", err);
@@ -290,3 +333,44 @@ void __init *sead3_dt_shim(void *fdt)
290 333
291 return fdt_buf; 334 return fdt_buf;
292} 335}
336
337static __init unsigned int sead3_measure_hpt_freq(void)
338{
339 void __iomem *status_reg = (void __iomem *)0xbf000410;
340 unsigned int freq, orig, tick = 0;
341 unsigned long flags;
342
343 local_irq_save(flags);
344
345 orig = readl(status_reg) & 0x2; /* get original sample */
346 /* wait for transition */
347 while ((readl(status_reg) & 0x2) == orig)
348 ;
349 orig = orig ^ 0x2; /* flip the bit */
350
351 write_c0_count(0);
352
353 /* wait 1 second (the sampling clock transitions every 10ms) */
354 while (tick < 100) {
355 /* wait for transition */
356 while ((readl(status_reg) & 0x2) == orig)
357 ;
358 orig = orig ^ 0x2; /* flip the bit */
359 tick++;
360 }
361
362 freq = read_c0_count();
363
364 local_irq_restore(flags);
365
366 return freq;
367}
368
369extern char __dtb_sead3_begin[];
370
371MIPS_MACHINE(sead3) = {
372 .fdt = __dtb_sead3_begin,
373 .detect = sead3_detect,
374 .fixup_fdt = sead3_fixup_fdt,
375 .measure_hpt_freq = sead3_measure_hpt_freq,
376};
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
deleted file mode 100644
index bfbd7035d4c5..000000000000
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Chris Dearman
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8 */
9#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
11
12
13/*
14 * CPU feature overrides for MIPS boards
15 */
16#ifdef CONFIG_CPU_MIPS32
17#define cpu_has_tlb 1
18#define cpu_has_4kex 1
19#define cpu_has_4k_cache 1
20/* #define cpu_has_fpu ? */
21/* #define cpu_has_32fpr ? */
22#define cpu_has_counter 1
23/* #define cpu_has_watch ? */
24#define cpu_has_divec 1
25#define cpu_has_vce 0
26/* #define cpu_has_cache_cdex_p ? */
27/* #define cpu_has_cache_cdex_s ? */
28/* #define cpu_has_prefetch ? */
29#define cpu_has_mcheck 1
30/* #define cpu_has_ejtag ? */
31#ifdef CONFIG_CPU_MICROMIPS
32#define cpu_has_llsc 0
33#else
34#define cpu_has_llsc 1
35#endif
36/* #define cpu_has_vtag_icache ? */
37/* #define cpu_has_dc_aliases ? */
38/* #define cpu_has_ic_fills_f_dc ? */
39#define cpu_has_nofpuex 0
40/* #define cpu_has_64bits ? */
41/* #define cpu_has_64bit_zero_reg ? */
42/* #define cpu_has_inclusive_pcaches ? */
43#define cpu_icache_snoops_remote_store 1
44#endif
45
46#ifdef CONFIG_CPU_MIPS64
47#define cpu_has_tlb 1
48#define cpu_has_4kex 1
49#define cpu_has_4k_cache 1
50/* #define cpu_has_fpu ? */
51/* #define cpu_has_32fpr ? */
52#define cpu_has_counter 1
53/* #define cpu_has_watch ? */
54#define cpu_has_divec 1
55#define cpu_has_vce 0
56/* #define cpu_has_cache_cdex_p ? */
57/* #define cpu_has_cache_cdex_s ? */
58/* #define cpu_has_prefetch ? */
59#define cpu_has_mcheck 1
60/* #define cpu_has_ejtag ? */
61#define cpu_has_llsc 1
62/* #define cpu_has_vtag_icache ? */
63/* #define cpu_has_dc_aliases ? */
64/* #define cpu_has_ic_fills_f_dc ? */
65#define cpu_has_nofpuex 0
66/* #define cpu_has_64bits ? */
67/* #define cpu_has_64bit_zero_reg ? */
68/* #define cpu_has_inclusive_pcaches ? */
69#define cpu_icache_snoops_remote_store 1
70#endif
71
72#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h
deleted file mode 100644
index 5d154cfbcf4c..000000000000
--- a/arch/mips/include/asm/mach-sead3/irq.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef __ASM_MACH_MIPS_IRQ_H
2#define __ASM_MACH_MIPS_IRQ_H
3
4#define NR_IRQS 256
5
6
7#include_next <irq.h>
8
9#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h
deleted file mode 100644
index 6cccd4d558d7..000000000000
--- a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Chris Dearman (chris@mips.com)
7 * Copyright (C) 2007 Mips Technologies, Inc.
8 */
9#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
10#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
11
12 .macro kernel_entry_setup
13 .endm
14
15/*
16 * Do SMP slave processor setup necessary before we can safely execute C code.
17 */
18 .macro smp_slave_setup
19 .endm
20
21#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-sead3/sead3-dtshim.h b/arch/mips/include/asm/mach-sead3/sead3-dtshim.h
deleted file mode 100644
index f5d7d9c9dd17..000000000000
--- a/arch/mips/include/asm/mach-sead3/sead3-dtshim.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (C) 2016 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __MIPS_SEAD3_DTSHIM_H__
12#define __MIPS_SEAD3_DTSHIM_H__
13
14#include <linux/init.h>
15
16#ifdef CONFIG_MIPS_SEAD3
17
18extern void __init *sead3_dt_shim(void *fdt);
19
20#else /* !CONFIG_MIPS_SEAD3 */
21
22static inline void *sead3_dt_shim(void *fdt)
23{
24 return fdt;
25}
26
27#endif /* !CONFIG_MIPS_SEAD3 */
28
29#endif /* __MIPS_SEAD3_DTSHIM_H__ */
diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h
deleted file mode 100644
index d068fc411f47..000000000000
--- a/arch/mips/include/asm/mach-sead3/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
9#define __ASM_MIPS_MACH_MIPS_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 1
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile
deleted file mode 100644
index 1674b9cf7527..000000000000
--- a/arch/mips/mti-sead3/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
1#
2# Carsten Langgaard, carstenl@mips.com
3# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4#
5# Copyright (C) 2008 Wind River Systems, Inc.
6# written by Ralf Baechle <ralf@linux-mips.org>
7#
8# Copyright (C) 2012 MIPS Technoligies, Inc. All rights reserved.
9# Steven J. Hill <sjhill@mips.com>
10#
11obj-y := sead3-dtshim.o
12obj-y += sead3-init.o
13obj-y += sead3-int.o
14obj-y += sead3-setup.o
15obj-y += sead3-time.o
diff --git a/arch/mips/mti-sead3/Platform b/arch/mips/mti-sead3/Platform
deleted file mode 100644
index 387092427145..000000000000
--- a/arch/mips/mti-sead3/Platform
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# MIPS SEAD-3 board
3#
4platform-$(CONFIG_MIPS_SEAD3) += mti-sead3/
5cflags-$(CONFIG_MIPS_SEAD3) += -I$(srctree)/arch/mips/include/asm/mach-sead3
6load-$(CONFIG_MIPS_SEAD3) += 0xffffffff80100000
7all-$(CONFIG_MIPS_SEAD3) := $(COMPRESSION_FNAME).srec
diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c
deleted file mode 100644
index 50f3fcb0fd80..000000000000
--- a/arch/mips/mti-sead3/sead3-init.c
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/init.h>
9#include <linux/io.h>
10
11#include <asm/bootinfo.h>
12#include <asm/cacheflush.h>
13#include <asm/traps.h>
14#include <asm/mips-boards/generic.h>
15#include <asm/fw/fw.h>
16
17extern char except_vec_nmi;
18extern char except_vec_ejtag_debug;
19
20static void __init mips_nmi_setup(void)
21{
22 void *base;
23
24 base = cpu_has_veic ?
25 (void *)(CAC_BASE + 0xa80) :
26 (void *)(CAC_BASE + 0x380);
27#ifdef CONFIG_CPU_MICROMIPS
28 /*
29 * Decrement the exception vector address by one for microMIPS.
30 */
31 memcpy(base, (&except_vec_nmi - 1), 0x80);
32
33 /*
34 * This is a hack. We do not know if the boot loader was built with
35 * microMIPS instructions or not. If it was not, the NMI exception
36 * code at 0x80000a80 will be taken in MIPS32 mode. The hand coded
37 * assembly below forces us into microMIPS mode if we are a pure
38 * microMIPS kernel. The assembly instructions are:
39 *
40 * 3C1A8000 lui k0,0x8000
41 * 375A0381 ori k0,k0,0x381
42 * 03400008 jr k0
43 * 00000000 nop
44 *
45 * The mode switch occurs by jumping to the unaligned exception
46 * vector address at 0x80000381 which would have been 0x80000380
47 * in MIPS32 mode. The jump to the unaligned address transitions
48 * us into microMIPS mode.
49 */
50 if (!cpu_has_veic) {
51 void *base2 = (void *)(CAC_BASE + 0xa80);
52 *((unsigned int *)base2) = 0x3c1a8000;
53 *((unsigned int *)base2 + 1) = 0x375a0381;
54 *((unsigned int *)base2 + 2) = 0x03400008;
55 *((unsigned int *)base2 + 3) = 0x00000000;
56 flush_icache_range((unsigned long)base2,
57 (unsigned long)base2 + 0x10);
58 }
59#else
60 memcpy(base, &except_vec_nmi, 0x80);
61#endif
62 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
63}
64
65static void __init mips_ejtag_setup(void)
66{
67 void *base;
68
69 base = cpu_has_veic ?
70 (void *)(CAC_BASE + 0xa00) :
71 (void *)(CAC_BASE + 0x300);
72#ifdef CONFIG_CPU_MICROMIPS
73 /* Deja vu... */
74 memcpy(base, (&except_vec_ejtag_debug - 1), 0x80);
75 if (!cpu_has_veic) {
76 void *base2 = (void *)(CAC_BASE + 0xa00);
77 *((unsigned int *)base2) = 0x3c1a8000;
78 *((unsigned int *)base2 + 1) = 0x375a0301;
79 *((unsigned int *)base2 + 2) = 0x03400008;
80 *((unsigned int *)base2 + 3) = 0x00000000;
81 flush_icache_range((unsigned long)base2,
82 (unsigned long)base2 + 0x10);
83 }
84#else
85 memcpy(base, &except_vec_ejtag_debug, 0x80);
86#endif
87 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
88}
89
90void __init prom_init(void)
91{
92 board_nmi_handler_setup = mips_nmi_setup;
93 board_ejtag_handler_setup = mips_ejtag_setup;
94
95 fw_init_cmdline();
96}
97
98void __init prom_free_prom_memory(void)
99{
100}
diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c
deleted file mode 100644
index 2e6b73244ecd..000000000000
--- a/arch/mips/mti-sead3/sead3-int.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/init.h>
9#include <linux/irqchip.h>
10#include <linux/irqchip/mips-gic.h>
11
12#include <asm/cpu-info.h>
13#include <asm/irq.h>
14
15void __init arch_init_irq(void)
16{
17 irqchip_init();
18
19 pr_info("GIC: %spresent\n", (gic_present) ? "" : "not ");
20 pr_info("EIC: %s\n",
21 (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off");
22}
23
diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c
deleted file mode 100644
index c915e54f10ac..000000000000
--- a/arch/mips/mti-sead3/sead3-setup.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
8 */
9#include <linux/init.h>
10#include <linux/libfdt.h>
11#include <linux/of_fdt.h>
12
13#include <asm/prom.h>
14
15#include <asm/mach-sead3/sead3-dtshim.h>
16#include <asm/mips-boards/generic.h>
17
18const char *get_system_type(void)
19{
20 return "MIPS SEAD3";
21}
22
23void __init *plat_get_fdt(void)
24{
25 return (void *)__dtb_start;
26}
27
28void __init plat_mem_setup(void)
29{
30 void *fdt = plat_get_fdt();
31
32 fdt = sead3_dt_shim(fdt);
33 __dt_setup_arch(fdt);
34}
35
36void __init device_tree_init(void)
37{
38 unflatten_and_copy_device_tree();
39}
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
deleted file mode 100644
index 71feb5194478..000000000000
--- a/arch/mips/mti-sead3/sead3-time.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/init.h>
9#include <linux/irqchip/mips-gic.h>
10
11#include <asm/cpu.h>
12#include <asm/setup.h>
13#include <asm/time.h>
14#include <asm/irq.h>
15#include <asm/mips-boards/generic.h>
16
17static void __iomem *status_reg = (void __iomem *)0xbf000410;
18
19/*
20 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect.
21 */
22static unsigned int __init estimate_cpu_frequency(void)
23{
24 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
25 unsigned int tick = 0;
26 unsigned int freq;
27 unsigned int orig;
28 unsigned long flags;
29
30 local_irq_save(flags);
31
32 orig = readl(status_reg) & 0x2; /* get original sample */
33 /* wait for transition */
34 while ((readl(status_reg) & 0x2) == orig)
35 ;
36 orig = orig ^ 0x2; /* flip the bit */
37
38 write_c0_count(0);
39
40 /* wait 1 second (the sampling clock transitions every 10ms) */
41 while (tick < 100) {
42 /* wait for transition */
43 while ((readl(status_reg) & 0x2) == orig)
44 ;
45 orig = orig ^ 0x2; /* flip the bit */
46 tick++;
47 }
48
49 freq = read_c0_count();
50
51 local_irq_restore(flags);
52
53 mips_hpt_frequency = freq;
54
55 /* Adjust for processor */
56 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
57 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
58 freq *= 2;
59
60 freq += 5000; /* rounding */
61 freq -= freq%10000;
62
63 return freq ;
64}
65
66int get_c0_perfcount_int(void)
67{
68 if (gic_present)
69 return gic_get_c0_perfcount_int();
70 if (cp0_perfcount_irq >= 0)
71 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
72 return -1;
73}
74EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
75
76unsigned int get_c0_compare_int(void)
77{
78 if (gic_present)
79 return gic_get_c0_compare_int();
80 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
81}
82
83void __init plat_time_init(void)
84{
85 unsigned int est_freq;
86
87 est_freq = estimate_cpu_frequency();
88
89 pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000),
90 (est_freq % 1000000) * 100 / 1000000);
91}
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-29 05:35:59 -0400