Merge tag 'iio-fixes-for-5.4a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-linus

Jonathan writes:

First set of IIO fixes for the 5.4 cycle.

* adis16400
  - Make sure to free memory on a few failure paths.
* adxl372
  - Fix wrong fifo depth
  - Fix wrong indexing of data from the fifo.
  - Perform a reset at startup to avoid a problem with inconsistent state.
* axp288
  - This is a fix for a fix.  The original fix made sure we kept the
    configuration from some firmwares to preserve a bias current.
    Unfortunately it appears the previous behaviour was working around
    a buggy firmware by overwriting the wrong value it had.  Hence
    a regression was seen.
* bmc150
  - Fix the centre temperature.  This was due to an error in one of the
    datasheets.
* hx711
  - Fix an issue where a badly timed interrupt could lead to a control
    line being high long enough to put the device into a low power state.
* meson_sar_adc
  - Fix a case where the irq was enabled before everything it uses was
    allocated.
* st_lsm6dsx
  - Ensure we don't set the sensor sensitivity to 0 as it will force
    all readings to 0.
  - Fix a wait time for the slave i2c controller when the accelerometer
    is not enabled.
* stm32-adc
  - Precursor for fix. Move a set of register definitions to a header.
  - Fix a race when several ADCs are in use with some using interrupts
    to control the dataflow and some using DMA.
* vcnl4000
  - Fix a garbage of_match_table in which a string was passed instead
    of the intended enum.

* tag 'iio-fixes-for-5.4a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio:
  iio: Fix an undefied reference error in noa1305_probe
  iio: light: opt3001: fix mutex unlock race
  iio: adc: ad799x: fix probe error handling
  iio: light: add missing vcnl4040 of_compatible
  iio: light: fix vcnl4000 devicetree hooks
  iio: imu: st_lsm6dsx: fix waitime for st_lsm6dsx i2c controller
  iio: adc: axp288: Override TS pin bias current for some models
  iio: imu: adis16400: fix memory leak
  iio: imu: adis16400: release allocated memory on failure
  iio: adc: stm32-adc: fix a race when using several adcs with dma and irq
  iio: adc: stm32-adc: move registers definitions
  iio: accel: adxl372: Perform a reset at start up
  iio: accel: adxl372: Fix push to buffers lost samples
  iio: accel: adxl372: Fix/remove limitation for FIFO samples
  iio: adc: hx711: fix bug in sampling of data
  iio: fix center temperature of bmc150-accel-core
  iio: imu: st_lsm6dsx: forbid 0 sensor sensitivity
  iio: adc: meson_saradc: Fix memory allocation order

16 files changed, 290 insertions, 182 deletions

diff --git a/drivers/iio/accel/adxl372.c b/drivers/iio/accel/adxl372.c
index 055227cb3d43..67b8817995c0 100644
--- a/drivers/iio/accel/adxl372.c
+++ b/drivers/iio/accel/adxl372.c
@@ -474,12 +474,17 @@ static int adxl372_configure_fifo(struct adxl372_state *st)
         if (ret < 0)
                 return ret;
 
-        fifo_samples = st->watermark & 0xFF;
+        /*
+         * watermark stores the number of sets; we need to write the FIFO
+         * registers with the number of samples
+         */
+        fifo_samples = (st->watermark * st->fifo_set_size);
         fifo_ctl = ADXL372_FIFO_CTL_FORMAT_MODE(st->fifo_format) |
                    ADXL372_FIFO_CTL_MODE_MODE(st->fifo_mode) |
-                   ADXL372_FIFO_CTL_SAMPLES_MODE(st->watermark);
+                   ADXL372_FIFO_CTL_SAMPLES_MODE(fifo_samples);
 
-        ret = regmap_write(st->regmap, ADXL372_FIFO_SAMPLES, fifo_samples);
+        ret = regmap_write(st->regmap,
+                           ADXL372_FIFO_SAMPLES, fifo_samples & 0xFF);
         if (ret < 0)
                 return ret;
 
@@ -548,8 +553,7 @@ static irqreturn_t adxl372_trigger_handler(int irq, void  *p)
                         goto err;
 
                 /* Each sample is 2 bytes */
-                for (i = 0; i < fifo_entries * sizeof(u16);
-                     i += st->fifo_set_size * sizeof(u16))
+                for (i = 0; i < fifo_entries; i += st->fifo_set_size)
                         iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
         }
 err:
@@ -571,6 +575,14 @@ static int adxl372_setup(struct adxl372_state *st)
                 return -ENODEV;
         }
 
+        /*
+         * Perform a software reset to make sure the device is in a consistent
+         * state after start up.
+         */
+        ret = regmap_write(st->regmap, ADXL372_RESET, ADXL372_RESET_CODE);
+        if (ret < 0)
+                return ret;
+
         ret = adxl372_set_op_mode(st, ADXL372_STANDBY);
         if (ret < 0)
                 return ret;
diff --git a/drivers/iio/accel/bmc150-accel-core.c b/drivers/iio/accel/bmc150-accel-core.c
index cf6c0e3a83d3..121b4e89f038 100644
--- a/drivers/iio/accel/bmc150-accel-core.c
+++ b/drivers/iio/accel/bmc150-accel-core.c
@@ -117,7 +117,7 @@
 #define BMC150_ACCEL_SLEEP_1_SEC                0x0F
 
 #define BMC150_ACCEL_REG_TEMP                   0x08
-#define BMC150_ACCEL_TEMP_CENTER_VAL            24
+#define BMC150_ACCEL_TEMP_CENTER_VAL            23
 
 #define BMC150_ACCEL_AXIS_TO_REG(axis)  (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
 #define BMC150_AUTO_SUSPEND_DELAY_MS            2000
diff --git a/drivers/iio/adc/ad799x.c b/drivers/iio/adc/ad799x.c
index 5a3ca5904ded..f658012baad8 100644
--- a/drivers/iio/adc/ad799x.c
+++ b/drivers/iio/adc/ad799x.c
@@ -810,10 +810,10 @@ static int ad799x_probe(struct i2c_client *client,
 
         ret = ad799x_write_config(st, st->chip_config->default_config);
         if (ret < 0)
-                goto error_disable_reg;
+                goto error_disable_vref;
         ret = ad799x_read_config(st);
         if (ret < 0)
-                goto error_disable_reg;
+                goto error_disable_vref;
         st->config = ret;
 
         ret = iio_triggered_buffer_setup(indio_dev, NULL,
diff --git a/drivers/iio/adc/axp288_adc.c b/drivers/iio/adc/axp288_adc.c
index adc9cf7a075d..8ea2aed6d6f5 100644
--- a/drivers/iio/adc/axp288_adc.c
+++ b/drivers/iio/adc/axp288_adc.c
@@ -7,6 +7,7 @@
  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  */
 
+#include <linux/dmi.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
@@ -25,6 +26,11 @@
 #define AXP288_ADC_EN_MASK                              0xF0
 #define AXP288_ADC_TS_ENABLE                            0x01
 
+#define AXP288_ADC_TS_BIAS_MASK                         GENMASK(5, 4)
+#define AXP288_ADC_TS_BIAS_20UA                         (0 << 4)
+#define AXP288_ADC_TS_BIAS_40UA                         (1 << 4)
+#define AXP288_ADC_TS_BIAS_60UA                         (2 << 4)
+#define AXP288_ADC_TS_BIAS_80UA                         (3 << 4)
 #define AXP288_ADC_TS_CURRENT_ON_OFF_MASK               GENMASK(1, 0)
 #define AXP288_ADC_TS_CURRENT_OFF                       (0 << 0)
 #define AXP288_ADC_TS_CURRENT_ON_WHEN_CHARGING          (1 << 0)
@@ -177,10 +183,36 @@ static int axp288_adc_read_raw(struct iio_dev *indio_dev,
         return ret;
 }
 
+/*
+ * We rely on the machine's firmware to correctly setup the TS pin bias current
+ * at boot. This lists systems with broken fw where we need to set it ourselves.
+ */
+static const struct dmi_system_id axp288_adc_ts_bias_override[] = {
+        {
+                /* Lenovo Ideapad 100S (11 inch) */
+                .matches = {
+                  DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+                  DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo ideapad 100S-11IBY"),
+                },
+                .driver_data = (void *)(uintptr_t)AXP288_ADC_TS_BIAS_80UA,
+        },
+        {}
+};
+
 static int axp288_adc_initialize(struct axp288_adc_info *info)
 {
+        const struct dmi_system_id *bias_override;
         int ret, adc_enable_val;
 
+        bias_override = dmi_first_match(axp288_adc_ts_bias_override);
+        if (bias_override) {
+                ret = regmap_update_bits(info->regmap, AXP288_ADC_TS_PIN_CTRL,
+                                         AXP288_ADC_TS_BIAS_MASK,
+                                         (uintptr_t)bias_override->driver_data);
+                if (ret)
+                        return ret;
+        }
+
         /*
          * Determine if the TS pin is enabled and set the TS current-source
          * accordingly.
diff --git a/drivers/iio/adc/hx711.c b/drivers/iio/adc/hx711.c
index 88c7fe15003b..62e6c8badd22 100644
--- a/drivers/iio/adc/hx711.c
+++ b/drivers/iio/adc/hx711.c
@@ -100,14 +100,14 @@ struct hx711_data {
 
 static int hx711_cycle(struct hx711_data *hx711_data)
 {
-        int val;
+        unsigned long flags;
 
         /*
          * if preempted for more then 60us while PD_SCK is high:
          * hx711 is going in reset
          * ==> measuring is false
          */
-        preempt_disable();
+        local_irq_save(flags);
         gpiod_set_value(hx711_data->gpiod_pd_sck, 1);
 
         /*
@@ -117,7 +117,6 @@ static int hx711_cycle(struct hx711_data *hx711_data)
          */
         ndelay(hx711_data->data_ready_delay_ns);
 
-        val = gpiod_get_value(hx711_data->gpiod_dout);
         /*
          * here we are not waiting for 0.2 us as suggested by the datasheet,
          * because the oscilloscope showed in a test scenario
@@ -125,7 +124,7 @@ static int hx711_cycle(struct hx711_data *hx711_data)
          * and 0.56 us for PD_SCK low on TI Sitara with 800 MHz
          */
         gpiod_set_value(hx711_data->gpiod_pd_sck, 0);
-        preempt_enable();
+        local_irq_restore(flags);
 
         /*
          * make it a square wave for addressing cases with capacitance on
@@ -133,7 +132,8 @@ static int hx711_cycle(struct hx711_data *hx711_data)
          */
         ndelay(hx711_data->data_ready_delay_ns);
 
-        return val;
+        /* sample as late as possible */
+        return gpiod_get_value(hx711_data->gpiod_dout);
 }
 
 static int hx711_read(struct hx711_data *hx711_data)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 7b28d045d271..7b27306330a3 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -1219,6 +1219,11 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
         if (IS_ERR(base))
                 return PTR_ERR(base);
 
+        priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+                                             priv->param->regmap_config);
+        if (IS_ERR(priv->regmap))
+                return PTR_ERR(priv->regmap);
+
         irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
         if (!irq)
                 return -EINVAL;
@@ -1228,11 +1233,6 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
         if (ret)
                 return ret;
 
-        priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
-                                             priv->param->regmap_config);
-        if (IS_ERR(priv->regmap))
-                return PTR_ERR(priv->regmap);
-
         priv->clkin = devm_clk_get(&pdev->dev, "clkin");
         if (IS_ERR(priv->clkin)) {
                 dev_err(&pdev->dev, "failed to get clkin\n");
diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
index 9b85fefc0a96..93a096a91f8c 100644
--- a/drivers/iio/adc/stm32-adc-core.c
+++ b/drivers/iio/adc/stm32-adc-core.c
@@ -24,33 +24,6 @@
 
 #include "stm32-adc-core.h"
 
-/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
-#define STM32F4_ADC_CSR                 (STM32_ADCX_COMN_OFFSET + 0x00)
-#define STM32F4_ADC_CCR                 (STM32_ADCX_COMN_OFFSET + 0x04)
-
-/* STM32F4_ADC_CSR - bit fields */
-#define STM32F4_EOC3                    BIT(17)
-#define STM32F4_EOC2                    BIT(9)
-#define STM32F4_EOC1                    BIT(1)
-
-/* STM32F4_ADC_CCR - bit fields */
-#define STM32F4_ADC_ADCPRE_SHIFT        16
-#define STM32F4_ADC_ADCPRE_MASK         GENMASK(17, 16)
-
-/* STM32H7 - common registers for all ADC instances */
-#define STM32H7_ADC_CSR                 (STM32_ADCX_COMN_OFFSET + 0x00)
-#define STM32H7_ADC_CCR                 (STM32_ADCX_COMN_OFFSET + 0x08)
-
-/* STM32H7_ADC_CSR - bit fields */
-#define STM32H7_EOC_SLV                 BIT(18)
-#define STM32H7_EOC_MST                 BIT(2)
-
-/* STM32H7_ADC_CCR - bit fields */
-#define STM32H7_PRESC_SHIFT             18
-#define STM32H7_PRESC_MASK              GENMASK(21, 18)
-#define STM32H7_CKMODE_SHIFT            16
-#define STM32H7_CKMODE_MASK             GENMASK(17, 16)
-
 #define STM32_ADC_CORE_SLEEP_DELAY_MS   2000
 
 /* SYSCFG registers */
@@ -71,6 +44,8 @@
  * @eoc1:       adc1 end of conversion flag in @csr
  * @eoc2:       adc2 end of conversion flag in @csr
  * @eoc3:       adc3 end of conversion flag in @csr
+ * @ier:        interrupt enable register offset for each adc
+ * @eocie_msk:  end of conversion interrupt enable mask in @ier
  */
 struct stm32_adc_common_regs {
         u32 csr;
@@ -78,6 +53,8 @@ struct stm32_adc_common_regs {
         u32 eoc1_msk;
         u32 eoc2_msk;
         u32 eoc3_msk;
+        u32 ier;
+        u32 eocie_msk;
 };
 
 struct stm32_adc_priv;
@@ -303,6 +280,8 @@ static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
         .eoc1_msk = STM32F4_EOC1,
         .eoc2_msk = STM32F4_EOC2,
         .eoc3_msk = STM32F4_EOC3,
+        .ier = STM32F4_ADC_CR1,
+        .eocie_msk = STM32F4_EOCIE,
 };
 
 /* STM32H7 common registers definitions */
@@ -311,8 +290,24 @@ static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
         .ccr = STM32H7_ADC_CCR,
         .eoc1_msk = STM32H7_EOC_MST,
         .eoc2_msk = STM32H7_EOC_SLV,
+        .ier = STM32H7_ADC_IER,
+        .eocie_msk = STM32H7_EOCIE,
+};
+
+static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
+        0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
 };
 
+static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
+                                          unsigned int adc)
+{
+        u32 ier, offset = stm32_adc_offset[adc];
+
+        ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
+
+        return ier & priv->cfg->regs->eocie_msk;
+}
+
 /* ADC common interrupt for all instances */
 static void stm32_adc_irq_handler(struct irq_desc *desc)
 {
@@ -323,13 +318,28 @@ static void stm32_adc_irq_handler(struct irq_desc *desc)
         chained_irq_enter(chip, desc);
         status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
 
-        if (status & priv->cfg->regs->eoc1_msk)
+        /*
+         * End of conversion may be handled by using IRQ or DMA. There may be a
+         * race here when two conversions complete at the same time on several
+         * ADCs. EOC may be read 'set' for several ADCs, with:
+         * - an ADC configured to use DMA (EOC triggers the DMA request, and
+         *   is then automatically cleared by DR read in hardware)
+         * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
+         *   be called in this case)
+         * So both EOC status bit in CSR and EOCIE control bit must be checked
+         * before invoking the interrupt handler (e.g. call ISR only for
+         * IRQ-enabled ADCs).
+         */
+        if (status & priv->cfg->regs->eoc1_msk &&
+            stm32_adc_eoc_enabled(priv, 0))
                 generic_handle_irq(irq_find_mapping(priv->domain, 0));
 
-        if (status & priv->cfg->regs->eoc2_msk)
+        if (status & priv->cfg->regs->eoc2_msk &&
+            stm32_adc_eoc_enabled(priv, 1))
                 generic_handle_irq(irq_find_mapping(priv->domain, 1));
 
-        if (status & priv->cfg->regs->eoc3_msk)
+        if (status & priv->cfg->regs->eoc3_msk &&
+            stm32_adc_eoc_enabled(priv, 2))
                 generic_handle_irq(irq_find_mapping(priv->domain, 2));
 
         chained_irq_exit(chip, desc);
diff --git a/drivers/iio/adc/stm32-adc-core.h b/drivers/iio/adc/stm32-adc-core.h
index 8af507b3f32d..2579d514c2a3 100644
--- a/drivers/iio/adc/stm32-adc-core.h
+++ b/drivers/iio/adc/stm32-adc-core.h
@@ -25,8 +25,145 @@
  * --------------------------------------------------------
  */
 #define STM32_ADC_MAX_ADCS              3
+#define STM32_ADC_OFFSET                0x100
 #define STM32_ADCX_COMN_OFFSET          0x300
 
+/* STM32F4 - Registers for each ADC instance */
+#define STM32F4_ADC_SR                  0x00
+#define STM32F4_ADC_CR1                 0x04
+#define STM32F4_ADC_CR2                 0x08
+#define STM32F4_ADC_SMPR1               0x0C
+#define STM32F4_ADC_SMPR2               0x10
+#define STM32F4_ADC_HTR                 0x24
+#define STM32F4_ADC_LTR                 0x28
+#define STM32F4_ADC_SQR1                0x2C
+#define STM32F4_ADC_SQR2                0x30
+#define STM32F4_ADC_SQR3                0x34
+#define STM32F4_ADC_JSQR                0x38
+#define STM32F4_ADC_JDR1                0x3C
+#define STM32F4_ADC_JDR2                0x40
+#define STM32F4_ADC_JDR3                0x44
+#define STM32F4_ADC_JDR4                0x48
+#define STM32F4_ADC_DR                  0x4C
+
+/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
+#define STM32F4_ADC_CSR                 (STM32_ADCX_COMN_OFFSET + 0x00)
+#define STM32F4_ADC_CCR                 (STM32_ADCX_COMN_OFFSET + 0x04)
+
+/* STM32F4_ADC_SR - bit fields */
+#define STM32F4_STRT                    BIT(4)
+#define STM32F4_EOC                     BIT(1)
+
+/* STM32F4_ADC_CR1 - bit fields */
+#define STM32F4_RES_SHIFT               24
+#define STM32F4_RES_MASK                GENMASK(25, 24)
+#define STM32F4_SCAN                    BIT(8)
+#define STM32F4_EOCIE                   BIT(5)
+
+/* STM32F4_ADC_CR2 - bit fields */
+#define STM32F4_SWSTART                 BIT(30)
+#define STM32F4_EXTEN_SHIFT             28
+#define STM32F4_EXTEN_MASK              GENMASK(29, 28)
+#define STM32F4_EXTSEL_SHIFT            24
+#define STM32F4_EXTSEL_MASK             GENMASK(27, 24)
+#define STM32F4_EOCS                    BIT(10)
+#define STM32F4_DDS                     BIT(9)
+#define STM32F4_DMA                     BIT(8)
+#define STM32F4_ADON                    BIT(0)
+
+/* STM32F4_ADC_CSR - bit fields */
+#define STM32F4_EOC3                    BIT(17)
+#define STM32F4_EOC2                    BIT(9)
+#define STM32F4_EOC1                    BIT(1)
+
+/* STM32F4_ADC_CCR - bit fields */
+#define STM32F4_ADC_ADCPRE_SHIFT        16
+#define STM32F4_ADC_ADCPRE_MASK         GENMASK(17, 16)
+
+/* STM32H7 - Registers for each ADC instance */
+#define STM32H7_ADC_ISR                 0x00
+#define STM32H7_ADC_IER                 0x04
+#define STM32H7_ADC_CR                  0x08
+#define STM32H7_ADC_CFGR                0x0C
+#define STM32H7_ADC_SMPR1               0x14
+#define STM32H7_ADC_SMPR2               0x18
+#define STM32H7_ADC_PCSEL               0x1C
+#define STM32H7_ADC_SQR1                0x30
+#define STM32H7_ADC_SQR2                0x34
+#define STM32H7_ADC_SQR3                0x38
+#define STM32H7_ADC_SQR4                0x3C
+#define STM32H7_ADC_DR                  0x40
+#define STM32H7_ADC_DIFSEL              0xC0
+#define STM32H7_ADC_CALFACT             0xC4
+#define STM32H7_ADC_CALFACT2            0xC8
+
+/* STM32H7 - common registers for all ADC instances */
+#define STM32H7_ADC_CSR                 (STM32_ADCX_COMN_OFFSET + 0x00)
+#define STM32H7_ADC_CCR                 (STM32_ADCX_COMN_OFFSET + 0x08)
+
+/* STM32H7_ADC_ISR - bit fields */
+#define STM32MP1_VREGREADY              BIT(12)
+#define STM32H7_EOC                     BIT(2)
+#define STM32H7_ADRDY                   BIT(0)
+
+/* STM32H7_ADC_IER - bit fields */
+#define STM32H7_EOCIE                   STM32H7_EOC
+
+/* STM32H7_ADC_CR - bit fields */
+#define STM32H7_ADCAL                   BIT(31)
+#define STM32H7_ADCALDIF                BIT(30)
+#define STM32H7_DEEPPWD                 BIT(29)
+#define STM32H7_ADVREGEN                BIT(28)
+#define STM32H7_LINCALRDYW6             BIT(27)
+#define STM32H7_LINCALRDYW5             BIT(26)
+#define STM32H7_LINCALRDYW4             BIT(25)
+#define STM32H7_LINCALRDYW3             BIT(24)
+#define STM32H7_LINCALRDYW2             BIT(23)
+#define STM32H7_LINCALRDYW1             BIT(22)
+#define STM32H7_ADCALLIN                BIT(16)
+#define STM32H7_BOOST                   BIT(8)
+#define STM32H7_ADSTP                   BIT(4)
+#define STM32H7_ADSTART                 BIT(2)
+#define STM32H7_ADDIS                   BIT(1)
+#define STM32H7_ADEN                    BIT(0)
+
+/* STM32H7_ADC_CFGR bit fields */
+#define STM32H7_EXTEN_SHIFT             10
+#define STM32H7_EXTEN_MASK              GENMASK(11, 10)
+#define STM32H7_EXTSEL_SHIFT            5
+#define STM32H7_EXTSEL_MASK             GENMASK(9, 5)
+#define STM32H7_RES_SHIFT               2
+#define STM32H7_RES_MASK                GENMASK(4, 2)
+#define STM32H7_DMNGT_SHIFT             0
+#define STM32H7_DMNGT_MASK              GENMASK(1, 0)
+
+enum stm32h7_adc_dmngt {
+        STM32H7_DMNGT_DR_ONLY,          /* Regular data in DR only */
+        STM32H7_DMNGT_DMA_ONESHOT,      /* DMA one shot mode */
+        STM32H7_DMNGT_DFSDM,            /* DFSDM mode */
+        STM32H7_DMNGT_DMA_CIRC,         /* DMA circular mode */
+};
+
+/* STM32H7_ADC_CALFACT - bit fields */
+#define STM32H7_CALFACT_D_SHIFT         16
+#define STM32H7_CALFACT_D_MASK          GENMASK(26, 16)
+#define STM32H7_CALFACT_S_SHIFT         0
+#define STM32H7_CALFACT_S_MASK          GENMASK(10, 0)
+
+/* STM32H7_ADC_CALFACT2 - bit fields */
+#define STM32H7_LINCALFACT_SHIFT        0
+#define STM32H7_LINCALFACT_MASK         GENMASK(29, 0)
+
+/* STM32H7_ADC_CSR - bit fields */
+#define STM32H7_EOC_SLV                 BIT(18)
+#define STM32H7_EOC_MST                 BIT(2)
+
+/* STM32H7_ADC_CCR - bit fields */
+#define STM32H7_PRESC_SHIFT             18
+#define STM32H7_PRESC_MASK              GENMASK(21, 18)
+#define STM32H7_CKMODE_SHIFT            16
+#define STM32H7_CKMODE_MASK             GENMASK(17, 16)
+
 /**
  * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
  * @base:               control registers base cpu addr
diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
index 6a7dd08b1e0b..663f8a5012d6 100644
--- a/drivers/iio/adc/stm32-adc.c
+++ b/drivers/iio/adc/stm32-adc.c
@@ -28,115 +28,6 @@
 
 #include "stm32-adc-core.h"
 
-/* STM32F4 - Registers for each ADC instance */
-#define STM32F4_ADC_SR                  0x00
-#define STM32F4_ADC_CR1                 0x04
-#define STM32F4_ADC_CR2                 0x08
-#define STM32F4_ADC_SMPR1               0x0C
-#define STM32F4_ADC_SMPR2               0x10
-#define STM32F4_ADC_HTR                 0x24
-#define STM32F4_ADC_LTR                 0x28
-#define STM32F4_ADC_SQR1                0x2C
-#define STM32F4_ADC_SQR2                0x30
-#define STM32F4_ADC_SQR3                0x34
-#define STM32F4_ADC_JSQR                0x38
-#define STM32F4_ADC_JDR1                0x3C
-#define STM32F4_ADC_JDR2                0x40
-#define STM32F4_ADC_JDR3                0x44
-#define STM32F4_ADC_JDR4                0x48
-#define STM32F4_ADC_DR                  0x4C
-
-/* STM32F4_ADC_SR - bit fields */
-#define STM32F4_STRT                    BIT(4)
-#define STM32F4_EOC                     BIT(1)
-
-/* STM32F4_ADC_CR1 - bit fields */
-#define STM32F4_RES_SHIFT               24
-#define STM32F4_RES_MASK                GENMASK(25, 24)
-#define STM32F4_SCAN                    BIT(8)
-#define STM32F4_EOCIE                   BIT(5)
-
-/* STM32F4_ADC_CR2 - bit fields */
-#define STM32F4_SWSTART                 BIT(30)
-#define STM32F4_EXTEN_SHIFT             28
-#define STM32F4_EXTEN_MASK              GENMASK(29, 28)
-#define STM32F4_EXTSEL_SHIFT            24
-#define STM32F4_EXTSEL_MASK             GENMASK(27, 24)
-#define STM32F4_EOCS                    BIT(10)
-#define STM32F4_DDS                     BIT(9)
-#define STM32F4_DMA                     BIT(8)
-#define STM32F4_ADON                    BIT(0)
-
-/* STM32H7 - Registers for each ADC instance */
-#define STM32H7_ADC_ISR                 0x00
-#define STM32H7_ADC_IER                 0x04
-#define STM32H7_ADC_CR                  0x08
-#define STM32H7_ADC_CFGR                0x0C
-#define STM32H7_ADC_SMPR1               0x14
-#define STM32H7_ADC_SMPR2               0x18
-#define STM32H7_ADC_PCSEL               0x1C
-#define STM32H7_ADC_SQR1                0x30
-#define STM32H7_ADC_SQR2                0x34
-#define STM32H7_ADC_SQR3                0x38
-#define STM32H7_ADC_SQR4                0x3C
-#define STM32H7_ADC_DR                  0x40
-#define STM32H7_ADC_DIFSEL              0xC0
-#define STM32H7_ADC_CALFACT             0xC4
-#define STM32H7_ADC_CALFACT2            0xC8
-
-/* STM32H7_ADC_ISR - bit fields */
-#define STM32MP1_VREGREADY              BIT(12)
-#define STM32H7_EOC                     BIT(2)
-#define STM32H7_ADRDY                   BIT(0)
-
-/* STM32H7_ADC_IER - bit fields */
-#define STM32H7_EOCIE                   STM32H7_EOC
-
-/* STM32H7_ADC_CR - bit fields */
-#define STM32H7_ADCAL                   BIT(31)
-#define STM32H7_ADCALDIF                BIT(30)
-#define STM32H7_DEEPPWD                 BIT(29)
-#define STM32H7_ADVREGEN                BIT(28)
-#define STM32H7_LINCALRDYW6             BIT(27)
-#define STM32H7_LINCALRDYW5             BIT(26)
-#define STM32H7_LINCALRDYW4             BIT(25)
-#define STM32H7_LINCALRDYW3             BIT(24)
-#define STM32H7_LINCALRDYW2             BIT(23)
-#define STM32H7_LINCALRDYW1             BIT(22)
-#define STM32H7_ADCALLIN                BIT(16)
-#define STM32H7_BOOST                   BIT(8)
-#define STM32H7_ADSTP                   BIT(4)
-#define STM32H7_ADSTART                 BIT(2)
-#define STM32H7_ADDIS                   BIT(1)
-#define STM32H7_ADEN                    BIT(0)
-
-/* STM32H7_ADC_CFGR bit fields */
-#define STM32H7_EXTEN_SHIFT             10
-#define STM32H7_EXTEN_MASK              GENMASK(11, 10)
-#define STM32H7_EXTSEL_SHIFT            5
-#define STM32H7_EXTSEL_MASK             GENMASK(9, 5)
-#define STM32H7_RES_SHIFT               2
-#define STM32H7_RES_MASK                GENMASK(4, 2)
-#define STM32H7_DMNGT_SHIFT             0
-#define STM32H7_DMNGT_MASK              GENMASK(1, 0)
-
-enum stm32h7_adc_dmngt {
-        STM32H7_DMNGT_DR_ONLY,          /* Regular data in DR only */
-        STM32H7_DMNGT_DMA_ONESHOT,      /* DMA one shot mode */
-        STM32H7_DMNGT_DFSDM,            /* DFSDM mode */
-        STM32H7_DMNGT_DMA_CIRC,         /* DMA circular mode */
-};
-
-/* STM32H7_ADC_CALFACT - bit fields */
-#define STM32H7_CALFACT_D_SHIFT         16
-#define STM32H7_CALFACT_D_MASK          GENMASK(26, 16)
-#define STM32H7_CALFACT_S_SHIFT         0
-#define STM32H7_CALFACT_S_MASK          GENMASK(10, 0)
-
-/* STM32H7_ADC_CALFACT2 - bit fields */
-#define STM32H7_LINCALFACT_SHIFT        0
-#define STM32H7_LINCALFACT_MASK         GENMASK(29, 0)
-
 /* Number of linear calibration shadow registers / LINCALRDYW control bits */
 #define STM32H7_LINCALFACT_NUM          6
 
diff --git a/drivers/iio/imu/adis_buffer.c b/drivers/iio/imu/adis_buffer.c
index 9ac8356d9a95..4998a89d083d 100644
--- a/drivers/iio/imu/adis_buffer.c
+++ b/drivers/iio/imu/adis_buffer.c
@@ -35,8 +35,11 @@ static int adis_update_scan_mode_burst(struct iio_dev *indio_dev,
                 return -ENOMEM;
 
         adis->buffer = kzalloc(burst_length + sizeof(u16), GFP_KERNEL);
-        if (!adis->buffer)
+        if (!adis->buffer) {
+                kfree(adis->xfer);
+                adis->xfer = NULL;
                 return -ENOMEM;
+        }
 
         tx = adis->buffer + burst_length;
         tx[0] = ADIS_READ_REG(adis->burst->reg_cmd);
@@ -78,8 +81,11 @@ int adis_update_scan_mode(struct iio_dev *indio_dev,
                 return -ENOMEM;
 
         adis->buffer = kcalloc(indio_dev->scan_bytes, 2, GFP_KERNEL);
-        if (!adis->buffer)
+        if (!adis->buffer) {
+                kfree(adis->xfer);
+                adis->xfer = NULL;
                 return -ENOMEM;
+        }
 
         rx = adis->buffer;
         tx = rx + scan_count;
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
index 80e42c7dbcbe..0fe6999b8257 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
@@ -99,7 +99,9 @@ struct st_lsm6dsx_fs {
 #define ST_LSM6DSX_FS_LIST_SIZE         4
 struct st_lsm6dsx_fs_table_entry {
         struct st_lsm6dsx_reg reg;
+
         struct st_lsm6dsx_fs fs_avl[ST_LSM6DSX_FS_LIST_SIZE];
+        int fs_len;
 };
 
 /**
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
index 2d3495560136..fd5ebe1e1594 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
@@ -145,6 +145,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
                                 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
                                 .fs_avl[3] = { IIO_G_TO_M_S_2(732), 0x1 },
+                                .fs_len = 4,
                         },
                         [ST_LSM6DSX_ID_GYRO] = {
                                 .reg = {
@@ -154,6 +155,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[0] = {  IIO_DEGREE_TO_RAD(245), 0x0 },
                                 .fs_avl[1] = {  IIO_DEGREE_TO_RAD(500), 0x1 },
                                 .fs_avl[2] = { IIO_DEGREE_TO_RAD(2000), 0x3 },
+                                .fs_len = 3,
                         },
                 },
         },
@@ -215,6 +217,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
                                 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
                                 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
+                                .fs_len = 4,
                         },
                         [ST_LSM6DSX_ID_GYRO] = {
                                 .reg = {
@@ -225,6 +228,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
                                 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
                                 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
+                                .fs_len = 4,
                         },
                 },
                 .decimator = {
@@ -327,6 +331,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
                                 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
                                 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
+                                .fs_len = 4,
                         },
                         [ST_LSM6DSX_ID_GYRO] = {
                                 .reg = {
@@ -337,6 +342,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
                                 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
                                 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
+                                .fs_len = 4,
                         },
                 },
                 .decimator = {
@@ -448,6 +454,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
                                 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
                                 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
+                                .fs_len = 4,
                         },
                         [ST_LSM6DSX_ID_GYRO] = {
                                 .reg = {
@@ -458,6 +465,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
                                 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
                                 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
+                                .fs_len = 4,
                         },
                 },
                 .decimator = {
@@ -563,6 +571,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
                                 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
                                 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
+                                .fs_len = 4,
                         },
                         [ST_LSM6DSX_ID_GYRO] = {
                                 .reg = {
@@ -573,6 +582,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
                                 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
                                 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
+                                .fs_len = 4,
                         },
                 },
                 .batch = {
@@ -693,6 +703,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
                                 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
                                 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
+                                .fs_len = 4,
                         },
                         [ST_LSM6DSX_ID_GYRO] = {
                                 .reg = {
@@ -703,6 +714,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
                                 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
                                 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
+                                .fs_len = 4,
                         },
                 },
                 .batch = {
@@ -800,6 +812,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
                                 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
                                 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
+                                .fs_len = 4,
                         },
                         [ST_LSM6DSX_ID_GYRO] = {
                                 .reg = {
@@ -810,6 +823,7 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
                                 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
                                 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
                                 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
+                                .fs_len = 4,
                         },
                 },
                 .batch = {
@@ -933,11 +947,12 @@ static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor,
         int i, err;
 
         fs_table = &sensor->hw->settings->fs_table[sensor->id];
-        for (i = 0; i < ST_LSM6DSX_FS_LIST_SIZE; i++)
+        for (i = 0; i < fs_table->fs_len; i++) {
                 if (fs_table->fs_avl[i].gain == gain)
                         break;
+        }
 
-        if (i == ST_LSM6DSX_FS_LIST_SIZE)
+        if (i == fs_table->fs_len)
                 return -EINVAL;
 
         data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val,
@@ -1196,18 +1211,13 @@ static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev,
 {
         struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev));
         const struct st_lsm6dsx_fs_table_entry *fs_table;
-        enum st_lsm6dsx_sensor_id id = sensor->id;
         struct st_lsm6dsx_hw *hw = sensor->hw;
         int i, len = 0;
 
-        fs_table = &hw->settings->fs_table[id];
-        for (i = 0; i < ST_LSM6DSX_FS_LIST_SIZE; i++) {
-                if (!fs_table->fs_avl[i].gain)
-                        break;
-
+        fs_table = &hw->settings->fs_table[sensor->id];
+        for (i = 0; i < fs_table->fs_len; i++)
                 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ",
                                  fs_table->fs_avl[i].gain);
-        }
         buf[len - 1] = '\n';
 
         return len;
diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c
index 66fbcd94642d..ea472cf6db7b 100644
--- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c
+++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c
@@ -61,6 +61,7 @@ static const struct st_lsm6dsx_ext_dev_settings st_lsm6dsx_ext_dev_table[] = {
                                 .gain = 1500,
                                 .val = 0x0,
                         }, /* 1500 uG/LSB */
+                        .fs_len = 1,
                 },
                 .temp_comp = {
                         .addr = 0x60,
@@ -92,9 +93,11 @@ static const struct st_lsm6dsx_ext_dev_settings st_lsm6dsx_ext_dev_table[] = {
 static void st_lsm6dsx_shub_wait_complete(struct st_lsm6dsx_hw *hw)
 {
         struct st_lsm6dsx_sensor *sensor;
+        u16 odr;
 
         sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]);
-        msleep((2000U / sensor->odr) + 1);
+        odr = (hw->enable_mask & BIT(ST_LSM6DSX_ID_ACC)) ? sensor->odr : 13;
+        msleep((2000U / odr) + 1);
 }
 
 /**
@@ -555,13 +558,9 @@ static ssize_t st_lsm6dsx_shub_scale_avail(struct device *dev,
         int i, len = 0;
 
         settings = sensor->ext_info.settings;
-        for (i = 0; i < ST_LSM6DSX_FS_LIST_SIZE; i++) {
-                u16 val = settings->fs_table.fs_avl[i].gain;
-
-                if (val > 0)
-                        len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ",
-                                         val);
-        }
+        for (i = 0; i < settings->fs_table.fs_len; i++)
+                len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ",
+                                 settings->fs_table.fs_avl[i].gain);
         buf[len - 1] = '\n';
 
         return len;
diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig
index 08d7e1ef2186..4a1a883dc061 100644
--- a/drivers/iio/light/Kconfig
+++ b/drivers/iio/light/Kconfig
@@ -314,6 +314,7 @@ config MAX44009
 config NOA1305
         tristate "ON Semiconductor NOA1305 ambient light sensor"
         depends on I2C
+        select REGMAP_I2C
         help
          Say Y here if you want to build support for the ON Semiconductor
          NOA1305 ambient light sensor.
diff --git a/drivers/iio/light/opt3001.c b/drivers/iio/light/opt3001.c
index e666879007d2..92004a2563ea 100644
--- a/drivers/iio/light/opt3001.c
+++ b/drivers/iio/light/opt3001.c
@@ -686,6 +686,7 @@ static irqreturn_t opt3001_irq(int irq, void *_iio)
         struct iio_dev *iio = _iio;
         struct opt3001 *opt = iio_priv(iio);
         int ret;
+        bool wake_result_ready_queue = false;
 
         if (!opt->ok_to_ignore_lock)
                 mutex_lock(&opt->lock);
@@ -720,13 +721,16 @@ static irqreturn_t opt3001_irq(int irq, void *_iio)
                 }
                 opt->result = ret;
                 opt->result_ready = true;
-                wake_up(&opt->result_ready_queue);
+                wake_result_ready_queue = true;
         }
 
 out:
         if (!opt->ok_to_ignore_lock)
                 mutex_unlock(&opt->lock);
 
+        if (wake_result_ready_queue)
+                wake_up(&opt->result_ready_queue);
+
         return IRQ_HANDLED;
 }
 
diff --git a/drivers/iio/light/vcnl4000.c b/drivers/iio/light/vcnl4000.c
index 51421ac32517..16dacea9eadf 100644
--- a/drivers/iio/light/vcnl4000.c
+++ b/drivers/iio/light/vcnl4000.c
@@ -398,19 +398,23 @@ static int vcnl4000_probe(struct i2c_client *client,
 static const struct of_device_id vcnl_4000_of_match[] = {
         {
                 .compatible = "vishay,vcnl4000",
-                .data = "VCNL4000",
+                .data = (void *)VCNL4000,
         },
         {
                 .compatible = "vishay,vcnl4010",
-                .data = "VCNL4010",
+                .data = (void *)VCNL4010,
         },
         {
-                .compatible = "vishay,vcnl4010",
-                .data = "VCNL4020",
+                .compatible = "vishay,vcnl4020",
+                .data = (void *)VCNL4010,
+        },
+        {
+                .compatible = "vishay,vcnl4040",
+                .data = (void *)VCNL4040,
         },
         {
                 .compatible = "vishay,vcnl4200",
-                .data = "VCNL4200",
+                .data = (void *)VCNL4200,
         },
         {},
 };