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authorTvrtko Ursulin <tvrtko.ursulin@intel.com>2016-01-19 10:25:17 -0500
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>2016-01-20 05:08:54 -0500
commit3f36b93797bd773eb27e31cf53e3d1f9e64c77ab (patch)
treebd5214b9e34fc730aa842fb88a50091d999536ca
parentbf22045250fafbe733277e13300eaa240ba2104d (diff)
drm/i915: Do not put big intel_crtc_state on the stack
Having this on stack triggers the -Wframe-larger-than=1024 and is not nice to put such big things on the kernel stack anyway. This required a little bit of refactoring to handle the new failure path from vlv_force_pll_on. v2: Corrected some whitespace. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: John Harrison <john.c.harrison@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1453217117-26125-1-git-send-email-tvrtko.ursulin@linux.intel.com
-rw-r--r--drivers/gpu/drm/i915/intel_display.c60
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c8
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h4
3 files changed, 46 insertions, 26 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3260fc639b07..f5c7f9fbb5ff 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7600,26 +7600,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
7600 * in cases where we need the PLL enabled even when @pipe is not going to 7600 * in cases where we need the PLL enabled even when @pipe is not going to
7601 * be enabled. 7601 * be enabled.
7602 */ 7602 */
7603void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, 7603int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7604 const struct dpll *dpll) 7604 const struct dpll *dpll)
7605{ 7605{
7606 struct intel_crtc *crtc = 7606 struct intel_crtc *crtc =
7607 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); 7607 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7608 struct intel_crtc_state pipe_config = { 7608 struct intel_crtc_state *pipe_config;
7609 .base.crtc = &crtc->base, 7609
7610 .pixel_multiplier = 1, 7610 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7611 .dpll = *dpll, 7611 if (!pipe_config)
7612 }; 7612 return -ENOMEM;
7613
7614 pipe_config->base.crtc = &crtc->base;
7615 pipe_config->pixel_multiplier = 1;
7616 pipe_config->dpll = *dpll;
7613 7617
7614 if (IS_CHERRYVIEW(dev)) { 7618 if (IS_CHERRYVIEW(dev)) {
7615 chv_compute_dpll(crtc, &pipe_config); 7619 chv_compute_dpll(crtc, pipe_config);
7616 chv_prepare_pll(crtc, &pipe_config); 7620 chv_prepare_pll(crtc, pipe_config);
7617 chv_enable_pll(crtc, &pipe_config); 7621 chv_enable_pll(crtc, pipe_config);
7618 } else { 7622 } else {
7619 vlv_compute_dpll(crtc, &pipe_config); 7623 vlv_compute_dpll(crtc, pipe_config);
7620 vlv_prepare_pll(crtc, &pipe_config); 7624 vlv_prepare_pll(crtc, pipe_config);
7621 vlv_enable_pll(crtc, &pipe_config); 7625 vlv_enable_pll(crtc, pipe_config);
7622 } 7626 }
7627
7628 kfree(pipe_config);
7629
7630 return 0;
7623} 7631}
7624 7632
7625/** 7633/**
@@ -10793,7 +10801,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 10801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10794 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 10802 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10795 struct drm_display_mode *mode; 10803 struct drm_display_mode *mode;
10796 struct intel_crtc_state pipe_config; 10804 struct intel_crtc_state *pipe_config;
10797 int htot = I915_READ(HTOTAL(cpu_transcoder)); 10805 int htot = I915_READ(HTOTAL(cpu_transcoder));
10798 int hsync = I915_READ(HSYNC(cpu_transcoder)); 10806 int hsync = I915_READ(HSYNC(cpu_transcoder));
10799 int vtot = I915_READ(VTOTAL(cpu_transcoder)); 10807 int vtot = I915_READ(VTOTAL(cpu_transcoder));
@@ -10804,6 +10812,12 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10804 if (!mode) 10812 if (!mode)
10805 return NULL; 10813 return NULL;
10806 10814
10815 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10816 if (!pipe_config) {
10817 kfree(mode);
10818 return NULL;
10819 }
10820
10807 /* 10821 /*
10808 * Construct a pipe_config sufficient for getting the clock info 10822 * Construct a pipe_config sufficient for getting the clock info
10809 * back out of crtc_clock_get. 10823 * back out of crtc_clock_get.
@@ -10811,14 +10825,14 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10811 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need 10825 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10812 * to use a real value here instead. 10826 * to use a real value here instead.
10813 */ 10827 */
10814 pipe_config.cpu_transcoder = (enum transcoder) pipe; 10828 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10815 pipe_config.pixel_multiplier = 1; 10829 pipe_config->pixel_multiplier = 1;
10816 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); 10830 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10817 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); 10831 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10818 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); 10832 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10819 i9xx_crtc_clock_get(intel_crtc, &pipe_config); 10833 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10820 10834
10821 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; 10835 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10822 mode->hdisplay = (htot & 0xffff) + 1; 10836 mode->hdisplay = (htot & 0xffff) + 1;
10823 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 10837 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10824 mode->hsync_start = (hsync & 0xffff) + 1; 10838 mode->hsync_start = (hsync & 0xffff) + 1;
@@ -10830,6 +10844,8 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10830 10844
10831 drm_mode_set_name(mode); 10845 drm_mode_set_name(mode);
10832 10846
10847 kfree(pipe_config);
10848
10833 return mode; 10849 return mode;
10834} 10850}
10835 10851
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 17612548c58d..e2bea710614f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -335,8 +335,12 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
335 release_cl_override = IS_CHERRYVIEW(dev) && 335 release_cl_override = IS_CHERRYVIEW(dev) &&
336 !chv_phy_powergate_ch(dev_priv, phy, ch, true); 336 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
337 337
338 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? 338 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
339 &chv_dpll[0].dpll : &vlv_dpll[0].dpll); 339 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
340 DRM_ERROR("Failed to force on pll for pipe %c!\n",
341 pipe_name(pipe));
342 return;
343 }
340 } 344 }
341 345
342 /* 346 /*
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 15917e3a3352..bc970125ec76 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1154,8 +1154,8 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
1154struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 1154struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1155 struct intel_crtc_state *state); 1155 struct intel_crtc_state *state);
1156 1156
1157void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, 1157int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1158 const struct dpll *dpll); 1158 const struct dpll *dpll);
1159void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); 1159void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1160 1160
1161/* modesetting asserts */ 1161/* modesetting asserts */