diff options
author | Dan Carpenter <dan.carpenter@oracle.com> | 2015-09-16 12:02:54 -0400 |
---|---|---|
committer | Doug Ledford <dledford@redhat.com> | 2015-09-18 11:28:47 -0400 |
commit | 3f2686a2665b4d06753b602fe394b5d87bc7f279 (patch) | |
tree | f11eccbe66cf546fd398f12f57238bd06b28e080 | |
parent | ebe6b2e8bc2cd06a330b3f9be8a4fa3ff44ab026 (diff) |
IB/hfi1: clean up some defines
I added spaces around operators so it matches kernel style because
normally "-1ULL" is a number and " - 1" is a subtract operation. Also
removed some superflous "ULL" types so "1ULL" becomes "1".
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
-rw-r--r-- | drivers/staging/rdma/hfi1/sdma.h | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/staging/rdma/hfi1/sdma.h b/drivers/staging/rdma/hfi1/sdma.h index 1e613fcd8f4c..496086903891 100644 --- a/drivers/staging/rdma/hfi1/sdma.h +++ b/drivers/staging/rdma/hfi1/sdma.h | |||
@@ -109,53 +109,53 @@ | |||
109 | /* | 109 | /* |
110 | * Bits defined in the send DMA descriptor. | 110 | * Bits defined in the send DMA descriptor. |
111 | */ | 111 | */ |
112 | #define SDMA_DESC0_FIRST_DESC_FLAG (1ULL<<63) | 112 | #define SDMA_DESC0_FIRST_DESC_FLAG (1ULL << 63) |
113 | #define SDMA_DESC0_LAST_DESC_FLAG (1ULL<<62) | 113 | #define SDMA_DESC0_LAST_DESC_FLAG (1ULL << 62) |
114 | #define SDMA_DESC0_BYTE_COUNT_SHIFT 48 | 114 | #define SDMA_DESC0_BYTE_COUNT_SHIFT 48 |
115 | #define SDMA_DESC0_BYTE_COUNT_WIDTH 14 | 115 | #define SDMA_DESC0_BYTE_COUNT_WIDTH 14 |
116 | #define SDMA_DESC0_BYTE_COUNT_MASK \ | 116 | #define SDMA_DESC0_BYTE_COUNT_MASK \ |
117 | ((1ULL<<SDMA_DESC0_BYTE_COUNT_WIDTH)-1ULL) | 117 | ((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1) |
118 | #define SDMA_DESC0_BYTE_COUNT_SMASK \ | 118 | #define SDMA_DESC0_BYTE_COUNT_SMASK \ |
119 | (SDMA_DESC0_BYTE_COUNT_MASK<<SDMA_DESC0_BYTE_COUNT_SHIFT) | 119 | (SDMA_DESC0_BYTE_COUNT_MASK << SDMA_DESC0_BYTE_COUNT_SHIFT) |
120 | #define SDMA_DESC0_PHY_ADDR_SHIFT 0 | 120 | #define SDMA_DESC0_PHY_ADDR_SHIFT 0 |
121 | #define SDMA_DESC0_PHY_ADDR_WIDTH 48 | 121 | #define SDMA_DESC0_PHY_ADDR_WIDTH 48 |
122 | #define SDMA_DESC0_PHY_ADDR_MASK \ | 122 | #define SDMA_DESC0_PHY_ADDR_MASK \ |
123 | ((1ULL<<SDMA_DESC0_PHY_ADDR_WIDTH)-1ULL) | 123 | ((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1) |
124 | #define SDMA_DESC0_PHY_ADDR_SMASK \ | 124 | #define SDMA_DESC0_PHY_ADDR_SMASK \ |
125 | (SDMA_DESC0_PHY_ADDR_MASK<<SDMA_DESC0_PHY_ADDR_SHIFT) | 125 | (SDMA_DESC0_PHY_ADDR_MASK << SDMA_DESC0_PHY_ADDR_SHIFT) |
126 | 126 | ||
127 | #define SDMA_DESC1_HEADER_UPDATE1_SHIFT 32 | 127 | #define SDMA_DESC1_HEADER_UPDATE1_SHIFT 32 |
128 | #define SDMA_DESC1_HEADER_UPDATE1_WIDTH 32 | 128 | #define SDMA_DESC1_HEADER_UPDATE1_WIDTH 32 |
129 | #define SDMA_DESC1_HEADER_UPDATE1_MASK \ | 129 | #define SDMA_DESC1_HEADER_UPDATE1_MASK \ |
130 | ((1ULL<<SDMA_DESC1_HEADER_UPDATE1_WIDTH)-1ULL) | 130 | ((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1) |
131 | #define SDMA_DESC1_HEADER_UPDATE1_SMASK \ | 131 | #define SDMA_DESC1_HEADER_UPDATE1_SMASK \ |
132 | (SDMA_DESC1_HEADER_UPDATE1_MASK<<SDMA_DESC1_HEADER_UPDATE1_SHIFT) | 132 | (SDMA_DESC1_HEADER_UPDATE1_MASK << SDMA_DESC1_HEADER_UPDATE1_SHIFT) |
133 | #define SDMA_DESC1_HEADER_MODE_SHIFT 13 | 133 | #define SDMA_DESC1_HEADER_MODE_SHIFT 13 |
134 | #define SDMA_DESC1_HEADER_MODE_WIDTH 3 | 134 | #define SDMA_DESC1_HEADER_MODE_WIDTH 3 |
135 | #define SDMA_DESC1_HEADER_MODE_MASK \ | 135 | #define SDMA_DESC1_HEADER_MODE_MASK \ |
136 | ((1ULL<<SDMA_DESC1_HEADER_MODE_WIDTH)-1ULL) | 136 | ((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1) |
137 | #define SDMA_DESC1_HEADER_MODE_SMASK \ | 137 | #define SDMA_DESC1_HEADER_MODE_SMASK \ |
138 | (SDMA_DESC1_HEADER_MODE_MASK<<SDMA_DESC1_HEADER_MODE_SHIFT) | 138 | (SDMA_DESC1_HEADER_MODE_MASK << SDMA_DESC1_HEADER_MODE_SHIFT) |
139 | #define SDMA_DESC1_HEADER_INDEX_SHIFT 8 | 139 | #define SDMA_DESC1_HEADER_INDEX_SHIFT 8 |
140 | #define SDMA_DESC1_HEADER_INDEX_WIDTH 5 | 140 | #define SDMA_DESC1_HEADER_INDEX_WIDTH 5 |
141 | #define SDMA_DESC1_HEADER_INDEX_MASK \ | 141 | #define SDMA_DESC1_HEADER_INDEX_MASK \ |
142 | ((1ULL<<SDMA_DESC1_HEADER_INDEX_WIDTH)-1ULL) | 142 | ((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1) |
143 | #define SDMA_DESC1_HEADER_INDEX_SMASK \ | 143 | #define SDMA_DESC1_HEADER_INDEX_SMASK \ |
144 | (SDMA_DESC1_HEADER_INDEX_MASK<<SDMA_DESC1_HEADER_INDEX_SHIFT) | 144 | (SDMA_DESC1_HEADER_INDEX_MASK << SDMA_DESC1_HEADER_INDEX_SHIFT) |
145 | #define SDMA_DESC1_HEADER_DWS_SHIFT 4 | 145 | #define SDMA_DESC1_HEADER_DWS_SHIFT 4 |
146 | #define SDMA_DESC1_HEADER_DWS_WIDTH 4 | 146 | #define SDMA_DESC1_HEADER_DWS_WIDTH 4 |
147 | #define SDMA_DESC1_HEADER_DWS_MASK \ | 147 | #define SDMA_DESC1_HEADER_DWS_MASK \ |
148 | ((1ULL<<SDMA_DESC1_HEADER_DWS_WIDTH)-1ULL) | 148 | ((1ULL << SDMA_DESC1_HEADER_DWS_WIDTH) - 1) |
149 | #define SDMA_DESC1_HEADER_DWS_SMASK \ | 149 | #define SDMA_DESC1_HEADER_DWS_SMASK \ |
150 | (SDMA_DESC1_HEADER_DWS_MASK<<SDMA_DESC1_HEADER_DWS_SHIFT) | 150 | (SDMA_DESC1_HEADER_DWS_MASK << SDMA_DESC1_HEADER_DWS_SHIFT) |
151 | #define SDMA_DESC1_GENERATION_SHIFT 2 | 151 | #define SDMA_DESC1_GENERATION_SHIFT 2 |
152 | #define SDMA_DESC1_GENERATION_WIDTH 2 | 152 | #define SDMA_DESC1_GENERATION_WIDTH 2 |
153 | #define SDMA_DESC1_GENERATION_MASK \ | 153 | #define SDMA_DESC1_GENERATION_MASK \ |
154 | ((1ULL<<SDMA_DESC1_GENERATION_WIDTH)-1ULL) | 154 | ((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1) |
155 | #define SDMA_DESC1_GENERATION_SMASK \ | 155 | #define SDMA_DESC1_GENERATION_SMASK \ |
156 | (SDMA_DESC1_GENERATION_MASK<<SDMA_DESC1_GENERATION_SHIFT) | 156 | (SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT) |
157 | #define SDMA_DESC1_INT_REQ_FLAG (1ULL<<1) | 157 | #define SDMA_DESC1_INT_REQ_FLAG (1ULL << 1) |
158 | #define SDMA_DESC1_HEAD_TO_HOST_FLAG (1ULL<<0) | 158 | #define SDMA_DESC1_HEAD_TO_HOST_FLAG (1ULL << 0) |
159 | 159 | ||
160 | enum sdma_states { | 160 | enum sdma_states { |
161 | sdma_state_s00_hw_down, | 161 | sdma_state_s00_hw_down, |