net/mlx5_core: Introduce offload arithmetic hardware capabilities

Define the necessary hardware structures for the offload
arithmetic capabilities and read/cache them on driver load.

Signed-off-by: Sagi Grimberg <sagig@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Reviewed-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>

3 files changed, 42 insertions, 1 deletions

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
index fe6dfd8697f4..75c7ae6a5cc4 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
@@ -145,6 +145,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
                         return err;
         }
 
+        if (MLX5_CAP_GEN(dev, vector_calc)) {
+                err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC);
+                if (err)
+                        return err;
+        }
+
         return 0;
 }
 
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 9566b3b3b2c5..4b531c44b3c7 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -1219,6 +1219,8 @@ enum mlx5_cap_type {
         MLX5_CAP_FLOW_TABLE,
         MLX5_CAP_ESWITCH_FLOW_TABLE,
         MLX5_CAP_ESWITCH,
+        MLX5_CAP_RESERVED,
+        MLX5_CAP_VECTOR_CALC,
         /* NUM OF CAP Types */
         MLX5_CAP_NUM
 };
@@ -1281,6 +1283,10 @@ enum mlx5_cap_type {
 #define MLX5_CAP_ODP(mdev, cap)\
         MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
 
+#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
+        MLX5_GET(vector_calc_cap, \
+                 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
+
 enum {
         MLX5_CMD_STAT_OK                        = 0x0,
         MLX5_CMD_STAT_INT_ERR                   = 0x1,
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index a3cacab22849..ad0a44b1592c 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -616,6 +616,33 @@ struct mlx5_ifc_odp_cap_bits {
         u8         reserved_at_e0[0x720];
 };
 
+struct mlx5_ifc_calc_op {
+        u8        reserved_at_0[0x10];
+        u8        reserved_at_10[0x9];
+        u8        op_swap_endianness[0x1];
+        u8        op_min[0x1];
+        u8        op_xor[0x1];
+        u8        op_or[0x1];
+        u8        op_and[0x1];
+        u8        op_max[0x1];
+        u8        op_add[0x1];
+};
+
+struct mlx5_ifc_vector_calc_cap_bits {
+        u8         calc_matrix[0x1];
+        u8         reserved_at_1[0x1f];
+        u8         reserved_at_20[0x8];
+        u8         max_vec_count[0x8];
+        u8         reserved_at_30[0xd];
+        u8         max_chunk_size[0x3];
+        struct mlx5_ifc_calc_op calc0;
+        struct mlx5_ifc_calc_op calc1;
+        struct mlx5_ifc_calc_op calc2;
+        struct mlx5_ifc_calc_op calc3;
+
+        u8         reserved_at_e0[0x720];
+};
+
 enum {
         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
         MLX5_WQ_TYPE_CYCLIC       = 0x1,
@@ -770,7 +797,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
         u8         cd[0x1];
         u8         reserved_at_22c[0x1];
         u8         apm[0x1];
-        u8         reserved_at_22e[0x2];
+        u8         vector_calc[0x1];
+        u8         reserved_at_22f[0x1];
         u8         imaicl[0x1];
         u8         reserved_at_231[0x4];
         u8         qkv[0x1];
@@ -1940,6 +1968,7 @@ union mlx5_ifc_hca_cap_union_bits {
         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
+        struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
         u8         reserved_at_0[0x8000];
 };