diff options
author | Dave Airlie <airlied@redhat.com> | 2016-12-07 19:33:26 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2016-12-07 19:33:26 -0500 |
commit | 3eff97b2d6d06fa381f456e5a786d576d62eb95e (patch) | |
tree | a994fe47c843916f2bc86d72b0e9cc1dffe9222b | |
parent | 8166255704edea288bb116375b3c2a47af2fe28c (diff) | |
parent | 7a9e10253e9e52451bbe80ddb2874368dbd240a3 (diff) |
Merge tag 'drm-intel-next-fixes-2016-12-07' of git://anongit.freedesktop.org/git/drm-intel into drm-next
first set of fixes for -next.
* tag 'drm-intel-next-fixes-2016-12-07' of git://anongit.freedesktop.org/git/drm-intel:
drm/i915: Move priority bumping for flips earlier
drm/i915: Hold a reference on the request for its fence chain
drm/i915/audio: fix hdmi audio noise issue
drm/i915/debugfs: Increment return value of gt.next_seqno
drm/i915/debugfs: Drop i915_hws_info
drm/i915: Initialize dev_priv->atomic_cdclk_freq at init time
drm/i915: Fix cdclk vs. dev_cdclk mess when not recomputing things
drm/i915: Make skl_write_{plane,cursor}_wm() static
drm/i915: Complete requests in nop_submit_request
drm/i915/gvt: fix lock not released bug for dispatch_workload() err path
drm/i915/gvt: fix getting 64bit bar size error
drm/i915/gvt: fix missing init param.primary
-rw-r--r-- | drivers/gpu/drm/i915/gvt/gvt.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gvt/scheduler.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gvt/vgpu.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_debugfs.c | 27 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_request.c | 34 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_sw_fence.h | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_audio.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 14 |
10 files changed, 63 insertions, 50 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 3d4223e8ebe3..b1a7c8dd4b5f 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h | |||
@@ -361,6 +361,8 @@ static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, | |||
361 | * leave the bit 3 - bit 0 unchanged. | 361 | * leave the bit 3 - bit 0 unchanged. |
362 | */ | 362 | */ |
363 | *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); | 363 | *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); |
364 | } else { | ||
365 | *pval = val; | ||
364 | } | 366 | } |
365 | } | 367 | } |
366 | 368 | ||
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index f898df38dd9a..4db242250235 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c | |||
@@ -177,8 +177,8 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) | |||
177 | rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); | 177 | rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); |
178 | if (IS_ERR(rq)) { | 178 | if (IS_ERR(rq)) { |
179 | gvt_err("fail to allocate gem request\n"); | 179 | gvt_err("fail to allocate gem request\n"); |
180 | workload->status = PTR_ERR(rq); | 180 | ret = PTR_ERR(rq); |
181 | return workload->status; | 181 | goto out; |
182 | } | 182 | } |
183 | 183 | ||
184 | gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq); | 184 | gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq); |
@@ -212,7 +212,8 @@ out: | |||
212 | if (ret) | 212 | if (ret) |
213 | workload->status = ret; | 213 | workload->status = ret; |
214 | 214 | ||
215 | i915_add_request_no_flush(rq); | 215 | if (!IS_ERR_OR_NULL(rq)) |
216 | i915_add_request_no_flush(rq); | ||
216 | mutex_unlock(&dev_priv->drm.struct_mutex); | 217 | mutex_unlock(&dev_priv->drm.struct_mutex); |
217 | return ret; | 218 | return ret; |
218 | } | 219 | } |
@@ -460,7 +461,8 @@ complete: | |||
460 | 461 | ||
461 | complete_current_workload(gvt, ring_id); | 462 | complete_current_workload(gvt, ring_id); |
462 | 463 | ||
463 | i915_gem_request_put(fetch_and_zero(&workload->req)); | 464 | if (workload->req) |
465 | i915_gem_request_put(fetch_and_zero(&workload->req)); | ||
464 | 466 | ||
465 | if (need_force_wake) | 467 | if (need_force_wake) |
466 | intel_uncore_forcewake_put(gvt->dev_priv, | 468 | intel_uncore_forcewake_put(gvt->dev_priv, |
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 4f64845d8a4c..536d2b9d5777 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c | |||
@@ -378,6 +378,7 @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, | |||
378 | struct intel_vgpu *vgpu; | 378 | struct intel_vgpu *vgpu; |
379 | 379 | ||
380 | param.handle = 0; | 380 | param.handle = 0; |
381 | param.primary = 1; | ||
381 | param.low_gm_sz = type->low_gm_size; | 382 | param.low_gm_sz = type->low_gm_size; |
382 | param.high_gm_sz = type->high_gm_size; | 383 | param.high_gm_sz = type->high_gm_size; |
383 | param.fence_sz = type->fence; | 384 | param.fence_sz = type->fence; |
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index b7f42c448a44..791bfc760075 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c | |||
@@ -935,27 +935,6 @@ static int i915_gem_fence_regs_info(struct seq_file *m, void *data) | |||
935 | return 0; | 935 | return 0; |
936 | } | 936 | } |
937 | 937 | ||
938 | static int i915_hws_info(struct seq_file *m, void *data) | ||
939 | { | ||
940 | struct drm_info_node *node = m->private; | ||
941 | struct drm_i915_private *dev_priv = node_to_i915(node); | ||
942 | struct intel_engine_cs *engine; | ||
943 | const u32 *hws; | ||
944 | int i; | ||
945 | |||
946 | engine = dev_priv->engine[(uintptr_t)node->info_ent->data]; | ||
947 | hws = engine->status_page.page_addr; | ||
948 | if (hws == NULL) | ||
949 | return 0; | ||
950 | |||
951 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | ||
952 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | ||
953 | i * 4, | ||
954 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | ||
955 | } | ||
956 | return 0; | ||
957 | } | ||
958 | |||
959 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) | 938 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
960 | 939 | ||
961 | static ssize_t | 940 | static ssize_t |
@@ -1047,7 +1026,7 @@ i915_next_seqno_get(void *data, u64 *val) | |||
1047 | { | 1026 | { |
1048 | struct drm_i915_private *dev_priv = data; | 1027 | struct drm_i915_private *dev_priv = data; |
1049 | 1028 | ||
1050 | *val = atomic_read(&dev_priv->gt.global_timeline.next_seqno); | 1029 | *val = 1 + atomic_read(&dev_priv->gt.global_timeline.next_seqno); |
1051 | return 0; | 1030 | return 0; |
1052 | } | 1031 | } |
1053 | 1032 | ||
@@ -5403,10 +5382,6 @@ static const struct drm_info_list i915_debugfs_list[] = { | |||
5403 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | 5382 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
5404 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, | 5383 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
5405 | {"i915_gem_interrupt", i915_interrupt_info, 0}, | 5384 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
5406 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, | ||
5407 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | ||
5408 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | ||
5409 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, | ||
5410 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, | 5385 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
5411 | {"i915_guc_info", i915_guc_info, 0}, | 5386 | {"i915_guc_info", i915_guc_info, 0}, |
5412 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, | 5387 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 902fa427c196..d0dcaf35b429 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -2764,6 +2764,8 @@ void i915_gem_reset(struct drm_i915_private *dev_priv) | |||
2764 | 2764 | ||
2765 | static void nop_submit_request(struct drm_i915_gem_request *request) | 2765 | static void nop_submit_request(struct drm_i915_gem_request *request) |
2766 | { | 2766 | { |
2767 | i915_gem_request_submit(request); | ||
2768 | intel_engine_init_global_seqno(request->engine, request->global_seqno); | ||
2767 | } | 2769 | } |
2768 | 2770 | ||
2769 | static void i915_gem_cleanup_engine(struct intel_engine_cs *engine) | 2771 | static void i915_gem_cleanup_engine(struct intel_engine_cs *engine) |
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 27e8f257fb39..57194471f8cd 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c | |||
@@ -200,8 +200,8 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) | |||
200 | struct i915_gem_active *active, *next; | 200 | struct i915_gem_active *active, *next; |
201 | 201 | ||
202 | lockdep_assert_held(&request->i915->drm.struct_mutex); | 202 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
203 | GEM_BUG_ON(!i915_sw_fence_done(&request->submit)); | 203 | GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit)); |
204 | GEM_BUG_ON(!i915_sw_fence_done(&request->execute)); | 204 | GEM_BUG_ON(!i915_sw_fence_signaled(&request->execute)); |
205 | GEM_BUG_ON(!i915_gem_request_completed(request)); | 205 | GEM_BUG_ON(!i915_gem_request_completed(request)); |
206 | GEM_BUG_ON(!request->i915->gt.active_requests); | 206 | GEM_BUG_ON(!request->i915->gt.active_requests); |
207 | 207 | ||
@@ -445,11 +445,17 @@ void i915_gem_request_submit(struct drm_i915_gem_request *request) | |||
445 | static int __i915_sw_fence_call | 445 | static int __i915_sw_fence_call |
446 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | 446 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
447 | { | 447 | { |
448 | if (state == FENCE_COMPLETE) { | 448 | struct drm_i915_gem_request *request = |
449 | struct drm_i915_gem_request *request = | 449 | container_of(fence, typeof(*request), submit); |
450 | container_of(fence, typeof(*request), submit); | ||
451 | 450 | ||
451 | switch (state) { | ||
452 | case FENCE_COMPLETE: | ||
452 | request->engine->submit_request(request); | 453 | request->engine->submit_request(request); |
454 | break; | ||
455 | |||
456 | case FENCE_FREE: | ||
457 | i915_gem_request_put(request); | ||
458 | break; | ||
453 | } | 459 | } |
454 | 460 | ||
455 | return NOTIFY_DONE; | 461 | return NOTIFY_DONE; |
@@ -458,6 +464,18 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | |||
458 | static int __i915_sw_fence_call | 464 | static int __i915_sw_fence_call |
459 | execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | 465 | execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
460 | { | 466 | { |
467 | struct drm_i915_gem_request *request = | ||
468 | container_of(fence, typeof(*request), execute); | ||
469 | |||
470 | switch (state) { | ||
471 | case FENCE_COMPLETE: | ||
472 | break; | ||
473 | |||
474 | case FENCE_FREE: | ||
475 | i915_gem_request_put(request); | ||
476 | break; | ||
477 | } | ||
478 | |||
461 | return NOTIFY_DONE; | 479 | return NOTIFY_DONE; |
462 | } | 480 | } |
463 | 481 | ||
@@ -545,8 +563,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, | |||
545 | req->timeline->fence_context, | 563 | req->timeline->fence_context, |
546 | __timeline_get_seqno(req->timeline->common)); | 564 | __timeline_get_seqno(req->timeline->common)); |
547 | 565 | ||
548 | i915_sw_fence_init(&req->submit, submit_notify); | 566 | /* We bump the ref for the fence chain */ |
549 | i915_sw_fence_init(&req->execute, execute_notify); | 567 | i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify); |
568 | i915_sw_fence_init(&i915_gem_request_get(req)->execute, execute_notify); | ||
569 | |||
550 | /* Ensure that the execute fence completes after the submit fence - | 570 | /* Ensure that the execute fence completes after the submit fence - |
551 | * as we complete the execute fence from within the submit fence | 571 | * as we complete the execute fence from within the submit fence |
552 | * callback, its completion would otherwise be visible first. | 572 | * callback, its completion would otherwise be visible first. |
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h b/drivers/gpu/drm/i915/i915_sw_fence.h index 7508d23f823b..0f3185ef7f4e 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.h +++ b/drivers/gpu/drm/i915/i915_sw_fence.h | |||
@@ -75,6 +75,11 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, | |||
75 | unsigned long timeout, | 75 | unsigned long timeout, |
76 | gfp_t gfp); | 76 | gfp_t gfp); |
77 | 77 | ||
78 | static inline bool i915_sw_fence_signaled(const struct i915_sw_fence *fence) | ||
79 | { | ||
80 | return atomic_read(&fence->pending) <= 0; | ||
81 | } | ||
82 | |||
78 | static inline bool i915_sw_fence_done(const struct i915_sw_fence *fence) | 83 | static inline bool i915_sw_fence_done(const struct i915_sw_fence *fence) |
79 | { | 84 | { |
80 | return atomic_read(&fence->pending) < 0; | 85 | return atomic_read(&fence->pending) < 0; |
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 1c509f7410f5..49f10538d4aa 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c | |||
@@ -351,10 +351,13 @@ hsw_hdmi_audio_config_update(struct intel_crtc *intel_crtc, enum port port, | |||
351 | 351 | ||
352 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); | 352 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
353 | 353 | ||
354 | /* | ||
355 | * Let's disable "Enable CTS or M Prog bit" | ||
356 | * and let HW calculate the value | ||
357 | */ | ||
354 | tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); | 358 | tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); |
355 | tmp &= ~AUD_CONFIG_M_MASK; | 359 | tmp &= ~AUD_M_CTS_M_PROG_ENABLE; |
356 | tmp &= ~AUD_M_CTS_M_VALUE_INDEX; | 360 | tmp &= ~AUD_M_CTS_M_VALUE_INDEX; |
357 | tmp |= AUD_M_CTS_M_PROG_ENABLE; | ||
358 | I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); | 361 | I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); |
359 | } | 362 | } |
360 | 363 | ||
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 962aae631f13..cf5cff7b03b8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -12028,7 +12028,6 @@ static void intel_mmio_flip_work_func(struct work_struct *w) | |||
12028 | to_intel_framebuffer(crtc->base.primary->fb); | 12028 | to_intel_framebuffer(crtc->base.primary->fb); |
12029 | struct drm_i915_gem_object *obj = intel_fb->obj; | 12029 | struct drm_i915_gem_object *obj = intel_fb->obj; |
12030 | 12030 | ||
12031 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | ||
12032 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); | 12031 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
12033 | 12032 | ||
12034 | intel_pipe_update_start(crtc); | 12033 | intel_pipe_update_start(crtc); |
@@ -12284,6 +12283,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, | |||
12284 | i915_add_request_no_flush(request); | 12283 | i915_add_request_no_flush(request); |
12285 | } | 12284 | } |
12286 | 12285 | ||
12286 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | ||
12287 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | 12287 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
12288 | to_intel_plane(primary)->frontbuffer_bit); | 12288 | to_intel_plane(primary)->frontbuffer_bit); |
12289 | mutex_unlock(&dev->struct_mutex); | 12289 | mutex_unlock(&dev->struct_mutex); |
@@ -13995,8 +13995,9 @@ static int intel_modeset_checks(struct drm_atomic_state *state) | |||
13995 | 13995 | ||
13996 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | 13996 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", |
13997 | intel_state->cdclk, intel_state->dev_cdclk); | 13997 | intel_state->cdclk, intel_state->dev_cdclk); |
13998 | } else | 13998 | } else { |
13999 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; | 13999 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
14000 | } | ||
14000 | 14001 | ||
14001 | intel_modeset_clear_plls(state); | 14002 | intel_modeset_clear_plls(state); |
14002 | 14003 | ||
@@ -14097,8 +14098,9 @@ static int intel_atomic_check(struct drm_device *dev, | |||
14097 | 14098 | ||
14098 | if (ret) | 14099 | if (ret) |
14099 | return ret; | 14100 | return ret; |
14100 | } else | 14101 | } else { |
14101 | intel_state->cdclk = dev_priv->cdclk_freq; | 14102 | intel_state->cdclk = dev_priv->atomic_cdclk_freq; |
14103 | } | ||
14102 | 14104 | ||
14103 | ret = drm_atomic_helper_check_planes(dev, state); | 14105 | ret = drm_atomic_helper_check_planes(dev, state); |
14104 | if (ret) | 14106 | if (ret) |
@@ -16485,6 +16487,7 @@ int intel_modeset_init(struct drm_device *dev) | |||
16485 | 16487 | ||
16486 | intel_update_czclk(dev_priv); | 16488 | intel_update_czclk(dev_priv); |
16487 | intel_update_cdclk(dev_priv); | 16489 | intel_update_cdclk(dev_priv); |
16490 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | ||
16488 | 16491 | ||
16489 | intel_shared_dpll_init(dev); | 16492 | intel_shared_dpll_init(dev); |
16490 | 16493 | ||
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index bbb1eaf1e6db..d67974eb127a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -3851,10 +3851,10 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv, | |||
3851 | I915_WRITE(reg, val); | 3851 | I915_WRITE(reg, val); |
3852 | } | 3852 | } |
3853 | 3853 | ||
3854 | void skl_write_plane_wm(struct intel_crtc *intel_crtc, | 3854 | static void skl_write_plane_wm(struct intel_crtc *intel_crtc, |
3855 | const struct skl_plane_wm *wm, | 3855 | const struct skl_plane_wm *wm, |
3856 | const struct skl_ddb_allocation *ddb, | 3856 | const struct skl_ddb_allocation *ddb, |
3857 | int plane) | 3857 | int plane) |
3858 | { | 3858 | { |
3859 | struct drm_crtc *crtc = &intel_crtc->base; | 3859 | struct drm_crtc *crtc = &intel_crtc->base; |
3860 | struct drm_device *dev = crtc->dev; | 3860 | struct drm_device *dev = crtc->dev; |
@@ -3875,9 +3875,9 @@ void skl_write_plane_wm(struct intel_crtc *intel_crtc, | |||
3875 | &ddb->y_plane[pipe][plane]); | 3875 | &ddb->y_plane[pipe][plane]); |
3876 | } | 3876 | } |
3877 | 3877 | ||
3878 | void skl_write_cursor_wm(struct intel_crtc *intel_crtc, | 3878 | static void skl_write_cursor_wm(struct intel_crtc *intel_crtc, |
3879 | const struct skl_plane_wm *wm, | 3879 | const struct skl_plane_wm *wm, |
3880 | const struct skl_ddb_allocation *ddb) | 3880 | const struct skl_ddb_allocation *ddb) |
3881 | { | 3881 | { |
3882 | struct drm_crtc *crtc = &intel_crtc->base; | 3882 | struct drm_crtc *crtc = &intel_crtc->base; |
3883 | struct drm_device *dev = crtc->dev; | 3883 | struct drm_device *dev = crtc->dev; |