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authorJack Xiao <Jack.Xiao@amd.com>2019-05-20 00:16:19 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-06-21 19:59:32 -0400
commit3ebab625e6626a0794808a25ea2de5de1ea65646 (patch)
treeb6766445d6f78a3031988f248d997fb19185e27a
parentb1fa87a48e53e05a712386baea39370331d95d72 (diff)
drm/amd: the data retured from PRT is expected to be 0
The dummy page for returning from PRT resides inside system memory, need set system flag bit in VM_L2_CNTL. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c2
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index 231c77aed01b..b7de60a15623 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -135,7 +135,8 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
135 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 135 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
136 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 136 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
137 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 137 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
138 138 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
139 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
139 /* XXX for emulation, Refer to closed source code.*/ 140 /* XXX for emulation, Refer to closed source code.*/
140 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 141 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
141 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 142 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index f65b9c827970..37a1a318ae63 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -121,6 +121,8 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
121 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); 121 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
122 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 122 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
123 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 123 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
124 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
125 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
124 /* XXX for emulation, Refer to closed source code.*/ 126 /* XXX for emulation, Refer to closed source code.*/
125 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 127 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
126 0); 128 0);