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authorOlof Johansson <olof@lixom.net>2015-10-25 20:53:14 -0400
committerOlof Johansson <olof@lixom.net>2015-10-25 20:53:14 -0400
commit3eb52a06d511e97809852ae8e7787a38a05c5ca0 (patch)
treec7f15f5864ba5926771b3a8210249ddac3616cfe
parent41adfe8202d2e7ed64f399e875f12f71a7ef7207 (diff)
parent481b4f1a3f64c529333186a9e94eab41b271e3d8 (diff)
Merge tag 'tegra-for-4.4-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
ARM: tegra: Devicetree changes for v4.4-rc1 Mostly a bunch of updates to the Toradex Apalis and Colibri platforms along with a couple of cleanup patches. * tag 'tegra-for-4.4-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits) ARM: tegra: Use consistent indentation for SATA node ARM: tegra: colibri-eval: Fix power/wakeup key ARM: tegra: colibri-eval: Add comment concerning SD/MMC ARM: tegra: colibri-eval: Fix vendor string of M41T0M6 RTC ARM: tegra: colibri: Properly align pin names ARM: tegra: colibri: Replace eMMC label by comment ARM: tegra: colibri: Activate STMPE811 touch controller ARM: tegra: colibri: Add touch pen interrupt pin muxing ARM: tegra: colibri: Fix comment about 3v3 fixed supply ARM: tegra: colibri: Add pin muxing for on-module power I2C ARM: tegra: colibri: Improve comment about thermal alert pin ARM: tegra: colibri: Fix HDMI supplies ARM: tegra: colibri: Update hardware revisions compatibility ARM: tegra: apalis-eval: Fix power/wakeup key ARM: tegra: apalis-eval: Fix backlight PWM comment ARM: tegra: apalis-eval: Set OTG dr_mode ARM: tegra: apalis-eval: Enable HDA controller ARM: tegra: apalis: Properly align pin names ARM: tegra: apalis: Add digital audio pin muxing ARM: tegra: apalis: Add comment concerning eMMC ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/boot/dts/tegra124-nyan.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi20
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi4
-rw-r--r--arch/arm/boot/dts/tegra30-apalis-eval.dts13
-rw-r--r--arch/arm/boot/dts/tegra30-apalis.dtsi214
-rw-r--r--arch/arm/boot/dts/tegra30-colibri-eval-v3.dts9
-rw-r--r--arch/arm/boot/dts/tegra30-colibri.dtsi196
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi10
8 files changed, 315 insertions, 166 deletions
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index a9aec23e06f2..40c23a0b7cfc 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -159,7 +159,7 @@
159 vin-ldo9-10-supply = <&vdd_5v0_sys>; 159 vin-ldo9-10-supply = <&vdd_5v0_sys>;
160 vin-ldo11-supply = <&vdd_3v3_run>; 160 vin-ldo11-supply = <&vdd_3v3_run>;
161 161
162 sd0 { 162 vdd_cpu: sd0 {
163 regulator-name = "+VDD_CPU_AP"; 163 regulator-name = "+VDD_CPU_AP";
164 regulator-min-microvolt = <700000>; 164 regulator-min-microvolt = <700000>;
165 regulator-max-microvolt = <1350000>; 165 regulator-max-microvolt = <1350000>;
@@ -397,6 +397,13 @@
397 non-removable; 397 non-removable;
398 }; 398 };
399 399
400 /* CPU DFLL clock */
401 clock@0,70110000 {
402 status = "okay";
403 vdd-cpu-supply = <&vdd_cpu>;
404 nvidia,i2c-fs-rate = <400000>;
405 };
406
400 ahub@0,70300000 { 407 ahub@0,70300000 {
401 i2s@0,70301100 { 408 i2s@0,70301100 {
402 status = "okay"; 409 status = "okay";
@@ -487,6 +494,12 @@
487 }; 494 };
488 }; 495 };
489 496
497 cpus {
498 cpu@0 {
499 vdd-cpu-supply = <&vdd_cpu>;
500 };
501 };
502
490 gpio-keys { 503 gpio-keys {
491 compatible = "gpio-keys"; 504 compatible = "gpio-keys";
492 505
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 1e204a6de12c..8aa6e96b5b5c 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -608,26 +608,20 @@
608 608
609 sata@0,70020000 { 609 sata@0,70020000 {
610 compatible = "nvidia,tegra124-ahci"; 610 compatible = "nvidia,tegra124-ahci";
611
612 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 611 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
613 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 612 <0x0 0x70020000 0x0 0x7000>; /* SATA */
614
615 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 613 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
616
617 clocks = <&tegra_car TEGRA124_CLK_SATA>, 614 clocks = <&tegra_car TEGRA124_CLK_SATA>,
618 <&tegra_car TEGRA124_CLK_SATA_OOB>, 615 <&tegra_car TEGRA124_CLK_SATA_OOB>,
619 <&tegra_car TEGRA124_CLK_CML1>, 616 <&tegra_car TEGRA124_CLK_CML1>,
620 <&tegra_car TEGRA124_CLK_PLL_E>; 617 <&tegra_car TEGRA124_CLK_PLL_E>;
621 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 618 clock-names = "sata", "sata-oob", "cml1", "pll_e";
622
623 resets = <&tegra_car 124>, 619 resets = <&tegra_car 124>,
624 <&tegra_car 123>, 620 <&tegra_car 123>,
625 <&tegra_car 129>; 621 <&tegra_car 129>;
626 reset-names = "sata", "sata-oob", "sata-cold"; 622 reset-names = "sata", "sata-oob", "sata-cold";
627
628 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 623 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
629 phy-names = "sata-phy"; 624 phy-names = "sata-phy";
630
631 status = "disabled"; 625 status = "disabled";
632 }; 626 };
633 627
@@ -636,7 +630,7 @@
636 reg = <0x0 0x70030000 0x0 0x10000>; 630 reg = <0x0 0x70030000 0x0 0x10000>;
637 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 631 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&tegra_car TEGRA124_CLK_HDA>, 632 clocks = <&tegra_car TEGRA124_CLK_HDA>,
639 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 633 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
640 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 634 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
641 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 635 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
642 resets = <&tegra_car 125>, /* hda */ 636 resets = <&tegra_car 125>, /* hda */
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index e058709e6d98..0a8d1a6c9ebe 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -601,8 +601,8 @@
601 <&tegra_car TEGRA20_CLK_PLL_E>; 601 <&tegra_car TEGRA20_CLK_PLL_E>;
602 clock-names = "pex", "afi", "pll_e"; 602 clock-names = "pex", "afi", "pll_e";
603 resets = <&tegra_car 70>, 603 resets = <&tegra_car 70>,
604 <&tegra_car 72>, 604 <&tegra_car 72>,
605 <&tegra_car 74>; 605 <&tegra_car 74>;
606 reset-names = "pex", "afi", "pcie_x"; 606 reset-names = "pex", "afi", "pcie_x";
607 status = "disabled"; 607 status = "disabled";
608 608
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 6236bdecb48b..f2879cfcca62 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -126,6 +126,10 @@
126 }; 126 };
127 }; 127 };
128 128
129 hda@70030000 {
130 status = "okay";
131 };
132
129 sd1: sdhci@78000000 { 133 sd1: sdhci@78000000 {
130 status = "okay"; 134 status = "okay";
131 bus-width = <4>; 135 bus-width = <4>;
@@ -149,6 +153,7 @@
149 153
150 usb-phy@7d000000 { 154 usb-phy@7d000000 {
151 status = "okay"; 155 status = "okay";
156 dr_mode = "otg";
152 vbus-supply = <&usbo1_vbus_reg>; 157 vbus-supply = <&usbo1_vbus_reg>;
153 }; 158 };
154 159
@@ -175,7 +180,7 @@
175 backlight: backlight { 180 backlight: backlight {
176 compatible = "pwm-backlight"; 181 compatible = "pwm-backlight";
177 182
178 /* PWM0 */ 183 /* PWM_BKL1 */
179 pwms = <&pwm 0 5000000>; 184 pwms = <&pwm 0 5000000>;
180 brightness-levels = <255 231 223 207 191 159 127 0>; 185 brightness-levels = <255 231 223 207 191 159 127 0>;
181 default-brightness-level = <6>; 186 default-brightness-level = <6>;
@@ -186,10 +191,10 @@
186 gpio-keys { 191 gpio-keys {
187 compatible = "gpio-keys"; 192 compatible = "gpio-keys";
188 193
189 power { 194 wakeup {
190 label = "Power"; 195 label = "WAKE1_MICO";
191 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; 196 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
192 linux,code = <KEY_POWER>; 197 linux,code = <KEY_WAKEUP>;
193 debounce-interval = <10>; 198 debounce-interval = <10>;
194 gpio-key,wakeup; 199 gpio-key,wakeup;
195 }; 200 };
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index a5446cba9804..bf361277fe10 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -1,8 +1,9 @@
1#include "tegra30.dtsi" 1#include "tegra30.dtsi"
2 2
3/* 3/*
4 * Toradex Apalis T30 Device Tree 4 * Toradex Apalis T30 Module Device Tree
5 * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C 5 * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
6 * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
6 */ 7 */
7/ { 8/ {
8 model = "Toradex Apalis T30"; 9 model = "Toradex Apalis T30";
@@ -33,8 +34,8 @@
33 34
34 host1x@50000000 { 35 host1x@50000000 {
35 hdmi@54280000 { 36 hdmi@54280000 {
36 vdd-supply = <&sys_3v3_reg>; 37 vdd-supply = <&avdd_hdmi_3v3_reg>;
37 pll-supply = <&vio_reg>; 38 pll-supply = <&avdd_hdmi_pll_1v8_reg>;
38 39
39 nvidia,hpd-gpio = 40 nvidia,hpd-gpio =
40 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 41 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
@@ -57,25 +58,25 @@
57 58
58 /* Apalis BKL1_PWM */ 59 /* Apalis BKL1_PWM */
59 uart3_rts_n_pc0 { 60 uart3_rts_n_pc0 {
60 nvidia,pins = "uart3_rts_n_pc0"; 61 nvidia,pins = "uart3_rts_n_pc0";
61 nvidia,function = "pwm0"; 62 nvidia,function = "pwm0";
62 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 63 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <TEGRA_PIN_DISABLE>; 64 nvidia,tristate = <TEGRA_PIN_DISABLE>;
64 }; 65 };
65 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ 66 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
66 uart3_cts_n_pa1 { 67 uart3_cts_n_pa1 {
67 nvidia,pins = "uart3_cts_n_pa1"; 68 nvidia,pins = "uart3_cts_n_pa1";
68 nvidia,function = "rsvd1"; 69 nvidia,function = "rsvd2";
69 nvidia,pull = <TEGRA_PIN_PULL_UP>; 70 nvidia,pull = <TEGRA_PIN_PULL_UP>;
70 nvidia,tristate = <TEGRA_PIN_DISABLE>; 71 nvidia,tristate = <TEGRA_PIN_DISABLE>;
71 }; 72 };
72 73
73 /* Apalis CAN1 on SPI6 */ 74 /* Apalis CAN1 on SPI6 */
74 spi2_cs0_n_px3 { 75 spi2_cs0_n_px3 {
75 nvidia,pins = "spi2_cs0_n_px3", 76 nvidia,pins = "spi2_cs0_n_px3",
76 "spi2_miso_px1", 77 "spi2_miso_px1",
77 "spi2_mosi_px0", 78 "spi2_mosi_px0",
78 "spi2_sck_px2"; 79 "spi2_sck_px2";
79 nvidia,function = "spi6"; 80 nvidia,function = "spi6";
80 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 81 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
81 nvidia,tristate = <TEGRA_PIN_DISABLE>; 82 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -91,10 +92,10 @@
91 92
92 /* Apalis CAN2 on SPI4 */ 93 /* Apalis CAN2 on SPI4 */
93 gmi_a16_pj7 { 94 gmi_a16_pj7 {
94 nvidia,pins = "gmi_a16_pj7", 95 nvidia,pins = "gmi_a16_pj7",
95 "gmi_a17_pb0", 96 "gmi_a17_pb0",
96 "gmi_a18_pb1", 97 "gmi_a18_pb1",
97 "gmi_a19_pk7"; 98 "gmi_a19_pk7";
98 nvidia,function = "spi4"; 99 nvidia,function = "spi4";
99 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
100 nvidia,tristate = <TEGRA_PIN_DISABLE>; 101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -108,6 +109,30 @@
108 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 109 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
109 }; 110 };
110 111
112 /* Apalis Digital Audio */
113 clk1_req_pee2 {
114 nvidia,pins = "clk1_req_pee2";
115 nvidia,function = "hda";
116 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
118 };
119 clk2_out_pw5 {
120 nvidia,pins = "clk2_out_pw5";
121 nvidia,function = "extperiph2";
122 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
123 nvidia,tristate = <TEGRA_PIN_DISABLE>;
124 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
125 };
126 dap1_fs_pn0 {
127 nvidia,pins = "dap1_fs_pn0",
128 "dap1_din_pn1",
129 "dap1_dout_pn2",
130 "dap1_sclk_pn3";
131 nvidia,function = "hda";
132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
134 };
135
111 /* Apalis I2C3 */ 136 /* Apalis I2C3 */
112 cam_i2c_scl_pbb1 { 137 cam_i2c_scl_pbb1 {
113 nvidia,pins = "cam_i2c_scl_pbb1", 138 nvidia,pins = "cam_i2c_scl_pbb1",
@@ -122,21 +147,21 @@
122 147
123 /* Apalis MMC1 */ 148 /* Apalis MMC1 */
124 sdmmc3_clk_pa6 { 149 sdmmc3_clk_pa6 {
125 nvidia,pins = "sdmmc3_clk_pa6", 150 nvidia,pins = "sdmmc3_clk_pa6",
126 "sdmmc3_cmd_pa7"; 151 "sdmmc3_cmd_pa7";
127 nvidia,function = "sdmmc3"; 152 nvidia,function = "sdmmc3";
128 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 153 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
129 nvidia,tristate = <TEGRA_PIN_DISABLE>; 154 nvidia,tristate = <TEGRA_PIN_DISABLE>;
130 }; 155 };
131 sdmmc3_dat0_pb7 { 156 sdmmc3_dat0_pb7 {
132 nvidia,pins = "sdmmc3_dat0_pb7", 157 nvidia,pins = "sdmmc3_dat0_pb7",
133 "sdmmc3_dat1_pb6", 158 "sdmmc3_dat1_pb6",
134 "sdmmc3_dat2_pb5", 159 "sdmmc3_dat2_pb5",
135 "sdmmc3_dat3_pb4", 160 "sdmmc3_dat3_pb4",
136 "sdmmc3_dat4_pd1", 161 "sdmmc3_dat4_pd1",
137 "sdmmc3_dat5_pd0", 162 "sdmmc3_dat5_pd0",
138 "sdmmc3_dat6_pd3", 163 "sdmmc3_dat6_pd3",
139 "sdmmc3_dat7_pd4"; 164 "sdmmc3_dat7_pd4";
140 nvidia,function = "sdmmc3"; 165 nvidia,function = "sdmmc3";
141 nvidia,pull = <TEGRA_PIN_PULL_UP>; 166 nvidia,pull = <TEGRA_PIN_PULL_UP>;
142 nvidia,tristate = <TEGRA_PIN_DISABLE>; 167 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -151,32 +176,32 @@
151 }; 176 };
152 177
153 /* Apalis PWM1 */ 178 /* Apalis PWM1 */
154 gpio_pu6 { 179 pu6 {
155 nvidia,pins = "gpio_pu6"; 180 nvidia,pins = "pu6";
156 nvidia,function = "pwm3"; 181 nvidia,function = "pwm3";
157 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 182 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158 nvidia,tristate = <TEGRA_PIN_DISABLE>; 183 nvidia,tristate = <TEGRA_PIN_DISABLE>;
159 }; 184 };
160 185
161 /* Apalis PWM2 */ 186 /* Apalis PWM2 */
162 gpio_pu5 { 187 pu5 {
163 nvidia,pins = "gpio_pu5"; 188 nvidia,pins = "pu5";
164 nvidia,function = "pwm2"; 189 nvidia,function = "pwm2";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>; 191 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 }; 192 };
168 193
169 /* Apalis PWM3 */ 194 /* Apalis PWM3 */
170 gpio_pu4 { 195 pu4 {
171 nvidia,pins = "gpio_pu4"; 196 nvidia,pins = "pu4";
172 nvidia,function = "pwm1"; 197 nvidia,function = "pwm1";
173 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 198 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
174 nvidia,tristate = <TEGRA_PIN_DISABLE>; 199 nvidia,tristate = <TEGRA_PIN_DISABLE>;
175 }; 200 };
176 201
177 /* Apalis PWM4 */ 202 /* Apalis PWM4 */
178 gpio_pu3 { 203 pu3 {
179 nvidia,pins = "gpio_pu3"; 204 nvidia,pins = "pu3";
180 nvidia,function = "pwm0"; 205 nvidia,function = "pwm0";
181 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
182 nvidia,tristate = <TEGRA_PIN_DISABLE>; 207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -198,11 +223,11 @@
198 nvidia,tristate = <TEGRA_PIN_DISABLE>; 223 nvidia,tristate = <TEGRA_PIN_DISABLE>;
199 }; 224 };
200 sdmmc1_cmd_pz1 { 225 sdmmc1_cmd_pz1 {
201 nvidia,pins = "sdmmc1_cmd_pz1", 226 nvidia,pins = "sdmmc1_cmd_pz1",
202 "sdmmc1_dat0_py7", 227 "sdmmc1_dat0_py7",
203 "sdmmc1_dat1_py6", 228 "sdmmc1_dat1_py6",
204 "sdmmc1_dat2_py5", 229 "sdmmc1_dat2_py5",
205 "sdmmc1_dat3_py4"; 230 "sdmmc1_dat3_py4";
206 nvidia,function = "sdmmc1"; 231 nvidia,function = "sdmmc1";
207 nvidia,pull = <TEGRA_PIN_PULL_UP>; 232 nvidia,pull = <TEGRA_PIN_PULL_UP>;
208 nvidia,tristate = <TEGRA_PIN_DISABLE>; 233 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -218,10 +243,10 @@
218 243
219 /* Apalis SPI1 */ 244 /* Apalis SPI1 */
220 spi1_sck_px5 { 245 spi1_sck_px5 {
221 nvidia,pins = "spi1_sck_px5", 246 nvidia,pins = "spi1_sck_px5",
222 "spi1_mosi_px4", 247 "spi1_mosi_px4",
223 "spi1_miso_px7", 248 "spi1_miso_px7",
224 "spi1_cs0_n_px6"; 249 "spi1_cs0_n_px6";
225 nvidia,function = "spi1"; 250 nvidia,function = "spi1";
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 251 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>; 252 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -229,10 +254,10 @@
229 254
230 /* Apalis SPI2 */ 255 /* Apalis SPI2 */
231 lcd_sck_pz4 { 256 lcd_sck_pz4 {
232 nvidia,pins = "lcd_sck_pz4", 257 nvidia,pins = "lcd_sck_pz4",
233 "lcd_sdout_pn5", 258 "lcd_sdout_pn5",
234 "lcd_sdin_pz2", 259 "lcd_sdin_pz2",
235 "lcd_cs0_n_pn4"; 260 "lcd_cs0_n_pn4";
236 nvidia,function = "spi5"; 261 nvidia,function = "spi5";
237 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 262 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
238 nvidia,tristate = <TEGRA_PIN_DISABLE>; 263 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -240,14 +265,14 @@
240 265
241 /* Apalis UART1 */ 266 /* Apalis UART1 */
242 ulpi_data0 { 267 ulpi_data0 {
243 nvidia,pins = "ulpi_data0_po1", 268 nvidia,pins = "ulpi_data0_po1",
244 "ulpi_data1_po2", 269 "ulpi_data1_po2",
245 "ulpi_data2_po3", 270 "ulpi_data2_po3",
246 "ulpi_data3_po4", 271 "ulpi_data3_po4",
247 "ulpi_data4_po5", 272 "ulpi_data4_po5",
248 "ulpi_data5_po6", 273 "ulpi_data5_po6",
249 "ulpi_data6_po7", 274 "ulpi_data6_po7",
250 "ulpi_data7_po0"; 275 "ulpi_data7_po0";
251 nvidia,function = "uarta"; 276 nvidia,function = "uarta";
252 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 277 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristate = <TEGRA_PIN_DISABLE>; 278 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -255,10 +280,10 @@
255 280
256 /* Apalis UART2 */ 281 /* Apalis UART2 */
257 ulpi_clk_py0 { 282 ulpi_clk_py0 {
258 nvidia,pins = "ulpi_clk_py0", 283 nvidia,pins = "ulpi_clk_py0",
259 "ulpi_dir_py1", 284 "ulpi_dir_py1",
260 "ulpi_nxt_py2", 285 "ulpi_nxt_py2",
261 "ulpi_stp_py3"; 286 "ulpi_stp_py3";
262 nvidia,function = "uartd"; 287 nvidia,function = "uartd";
263 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 288 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264 nvidia,tristate = <TEGRA_PIN_DISABLE>; 289 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -266,8 +291,8 @@
266 291
267 /* Apalis UART3 */ 292 /* Apalis UART3 */
268 uart2_rxd_pc3 { 293 uart2_rxd_pc3 {
269 nvidia,pins = "uart2_rxd_pc3", 294 nvidia,pins = "uart2_rxd_pc3",
270 "uart2_txd_pc2"; 295 "uart2_txd_pc2";
271 nvidia,function = "uartb"; 296 nvidia,function = "uartb";
272 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273 nvidia,tristate = <TEGRA_PIN_DISABLE>; 298 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -275,8 +300,8 @@
275 300
276 /* Apalis UART4 */ 301 /* Apalis UART4 */
277 uart3_rxd_pw7 { 302 uart3_rxd_pw7 {
278 nvidia,pins = "uart3_rxd_pw7", 303 nvidia,pins = "uart3_rxd_pw7",
279 "uart3_txd_pw6"; 304 "uart3_txd_pw6";
280 nvidia,function = "uartc"; 305 nvidia,function = "uartc";
281 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 306 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282 nvidia,tristate = <TEGRA_PIN_DISABLE>; 307 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -312,21 +337,21 @@
312 337
313 /* eMMC (On-module) */ 338 /* eMMC (On-module) */
314 sdmmc4_clk_pcc4 { 339 sdmmc4_clk_pcc4 {
315 nvidia,pins = "sdmmc4_clk_pcc4", 340 nvidia,pins = "sdmmc4_clk_pcc4",
316 "sdmmc4_rst_n_pcc3"; 341 "sdmmc4_rst_n_pcc3";
317 nvidia,function = "sdmmc4"; 342 nvidia,function = "sdmmc4";
318 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 343 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
319 nvidia,tristate = <TEGRA_PIN_DISABLE>; 344 nvidia,tristate = <TEGRA_PIN_DISABLE>;
320 }; 345 };
321 sdmmc4_dat0_paa0 { 346 sdmmc4_dat0_paa0 {
322 nvidia,pins = "sdmmc4_dat0_paa0", 347 nvidia,pins = "sdmmc4_dat0_paa0",
323 "sdmmc4_dat1_paa1", 348 "sdmmc4_dat1_paa1",
324 "sdmmc4_dat2_paa2", 349 "sdmmc4_dat2_paa2",
325 "sdmmc4_dat3_paa3", 350 "sdmmc4_dat3_paa3",
326 "sdmmc4_dat4_paa4", 351 "sdmmc4_dat4_paa4",
327 "sdmmc4_dat5_paa5", 352 "sdmmc4_dat5_paa5",
328 "sdmmc4_dat6_paa6", 353 "sdmmc4_dat6_paa6",
329 "sdmmc4_dat7_paa7"; 354 "sdmmc4_dat7_paa7";
330 nvidia,function = "sdmmc4"; 355 nvidia,function = "sdmmc4";
331 nvidia,pull = <TEGRA_PIN_PULL_UP>; 356 nvidia,pull = <TEGRA_PIN_PULL_UP>;
332 nvidia,tristate = <TEGRA_PIN_DISABLE>; 357 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -334,10 +359,10 @@
334 359
335 /* LVDS Transceiver Configuration */ 360 /* LVDS Transceiver Configuration */
336 pbb0 { 361 pbb0 {
337 nvidia,pins = "pbb0", 362 nvidia,pins = "pbb0",
338 "pbb7", 363 "pbb7",
339 "pcc1", 364 "pcc1",
340 "pcc2"; 365 "pcc2";
341 nvidia,function = "rsvd2"; 366 nvidia,function = "rsvd2";
342 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 367 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
343 nvidia,tristate = <TEGRA_PIN_DISABLE>; 368 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -345,10 +370,10 @@
345 nvidia,lock = <TEGRA_PIN_DISABLE>; 370 nvidia,lock = <TEGRA_PIN_DISABLE>;
346 }; 371 };
347 pbb3 { 372 pbb3 {
348 nvidia,pins = "pbb3", 373 nvidia,pins = "pbb3",
349 "pbb4", 374 "pbb4",
350 "pbb5", 375 "pbb5",
351 "pbb6"; 376 "pbb6";
352 nvidia,function = "displayb"; 377 nvidia,function = "displayb";
353 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 378 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354 nvidia,tristate = <TEGRA_PIN_DISABLE>; 379 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -635,6 +660,7 @@
635 nvidia,sys-clock-req-active-high; 660 nvidia,sys-clock-req-active-high;
636 }; 661 };
637 662
663 /* eMMC */
638 sdhci@78000600 { 664 sdhci@78000600 {
639 status = "okay"; 665 status = "okay";
640 bus-width = <8>; 666 bus-width = <8>;
@@ -666,18 +692,40 @@
666 #address-cells = <1>; 692 #address-cells = <1>;
667 #size-cells = <0>; 693 #size-cells = <0>;
668 694
669 sys_3v3_reg: regulator@100 { 695 avdd_hdmi_pll_1v8_reg: regulator@100 {
670 compatible = "regulator-fixed"; 696 compatible = "regulator-fixed";
671 reg = <100>; 697 reg = <100>;
698 regulator-name = "+V1.8_AVDD_HDMI_PLL";
699 regulator-min-microvolt = <1800000>;
700 regulator-max-microvolt = <1800000>;
701 enable-active-high;
702 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
703 vin-supply = <&vio_reg>;
704 };
705
706 sys_3v3_reg: regulator@101 {
707 compatible = "regulator-fixed";
708 reg = <101>;
672 regulator-name = "3v3"; 709 regulator-name = "3v3";
673 regulator-min-microvolt = <3300000>; 710 regulator-min-microvolt = <3300000>;
674 regulator-max-microvolt = <3300000>; 711 regulator-max-microvolt = <3300000>;
675 regulator-always-on; 712 regulator-always-on;
676 }; 713 };
677 714
678 charge_pump_5v0_reg: regulator@101 { 715 avdd_hdmi_3v3_reg: regulator@102 {
679 compatible = "regulator-fixed"; 716 compatible = "regulator-fixed";
680 reg = <101>; 717 reg = <102>;
718 regulator-name = "+V3.3_AVDD_HDMI";
719 regulator-min-microvolt = <3300000>;
720 regulator-max-microvolt = <3300000>;
721 enable-active-high;
722 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
723 vin-supply = <&sys_3v3_reg>;
724 };
725
726 charge_pump_5v0_reg: regulator@103 {
727 compatible = "regulator-fixed";
728 reg = <103>;
681 regulator-name = "5v0"; 729 regulator-name = "5v0";
682 regulator-min-microvolt = <5000000>; 730 regulator-min-microvolt = <5000000>;
683 regulator-max-microvolt = <5000000>; 731 regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
index 4d3ddc585641..3ff019f47d00 100644
--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -55,7 +55,7 @@
55 55
56 /* M41T0M6 real time clock on carrier board */ 56 /* M41T0M6 real time clock on carrier board */
57 rtc@68 { 57 rtc@68 {
58 compatible = "stm,m41t00"; 58 compatible = "st,m41t00";
59 reg = <0x68>; 59 reg = <0x68>;
60 }; 60 };
61 }; 61 };
@@ -84,6 +84,7 @@
84 }; 84 };
85 }; 85 };
86 86
87 /* SD/MMC */
87 sdhci@78000200 { 88 sdhci@78000200 {
88 status = "okay"; 89 status = "okay";
89 bus-width = <4>; 90 bus-width = <4>;
@@ -136,10 +137,10 @@
136 gpio-keys { 137 gpio-keys {
137 compatible = "gpio-keys"; 138 compatible = "gpio-keys";
138 139
139 power { 140 wakeup {
140 label = "Power"; 141 label = "SODIMM pin 45 wakeup";
141 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 142 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
142 linux,code = <KEY_POWER>; 143 linux,code = <KEY_WAKEUP>;
143 debounce-interval = <10>; 144 debounce-interval = <10>;
144 gpio-key,wakeup; 145 gpio-key,wakeup;
145 }; 146 };
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index c4ed1bec4d92..2d8c58fd9357 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -2,8 +2,8 @@
2#include "tegra30.dtsi" 2#include "tegra30.dtsi"
3 3
4/* 4/*
5 * Toradex Colibri T30 Device Tree 5 * Toradex Colibri T30 Module Device Tree
6 * Compatible for Revisions 1.1B/1.1C/1.1D 6 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A
7 */ 7 */
8/ { 8/ {
9 model = "Toradex Colibri T30"; 9 model = "Toradex Colibri T30";
@@ -15,8 +15,8 @@
15 15
16 host1x@50000000 { 16 host1x@50000000 {
17 hdmi@54280000 { 17 hdmi@54280000 {
18 vdd-supply = <&sys_3v3_reg>; 18 vdd-supply = <&avdd_hdmi_3v3_reg>;
19 pll-supply = <&vio_reg>; 19 pll-supply = <&avdd_hdmi_pll_1v8_reg>;
20 20
21 nvidia,hpd-gpio = 21 nvidia,hpd-gpio =
22 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 22 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
@@ -39,7 +39,7 @@
39 39
40 /* Colibri Backlight PWM<A> */ 40 /* Colibri Backlight PWM<A> */
41 sdmmc3_dat3_pb4 { 41 sdmmc3_dat3_pb4 {
42 nvidia,pins = "sdmmc3_dat3_pb4"; 42 nvidia,pins = "sdmmc3_dat3_pb4";
43 nvidia,function = "pwm0"; 43 nvidia,function = "pwm0";
44 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 44 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
45 nvidia,tristate = <TEGRA_PIN_DISABLE>; 45 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -66,15 +66,6 @@
66 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 66 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
67 }; 67 };
68 68
69 /* Thermal alert, need to be disabled */
70 lcd_dc1_pd2 {
71 nvidia,pins = "lcd_dc1_pd2";
72 nvidia,function = "rsvd3";
73 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
76 };
77
78 /* Colibri MMC */ 69 /* Colibri MMC */
79 kb_row10_ps2 { 70 kb_row10_ps2 {
80 nvidia,pins = "kb_row10_ps2"; 71 nvidia,pins = "kb_row10_ps2";
@@ -83,11 +74,11 @@
83 nvidia,tristate = <TEGRA_PIN_DISABLE>; 74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
84 }; 75 };
85 kb_row11_ps3 { 76 kb_row11_ps3 {
86 nvidia,pins = "kb_row11_ps3", 77 nvidia,pins = "kb_row11_ps3",
87 "kb_row12_ps4", 78 "kb_row12_ps4",
88 "kb_row13_ps5", 79 "kb_row13_ps5",
89 "kb_row14_ps6", 80 "kb_row14_ps6",
90 "kb_row15_ps7"; 81 "kb_row15_ps7";
91 nvidia,function = "sdmmc2"; 82 nvidia,function = "sdmmc2";
92 nvidia,pull = <TEGRA_PIN_PULL_UP>; 83 nvidia,pull = <TEGRA_PIN_PULL_UP>;
93 nvidia,tristate = <TEGRA_PIN_DISABLE>; 84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -95,17 +86,17 @@
95 86
96 /* Colibri SSP */ 87 /* Colibri SSP */
97 ulpi_clk_py0 { 88 ulpi_clk_py0 {
98 nvidia,pins = "ulpi_clk_py0", 89 nvidia,pins = "ulpi_clk_py0",
99 "ulpi_dir_py1", 90 "ulpi_dir_py1",
100 "ulpi_nxt_py2", 91 "ulpi_nxt_py2",
101 "ulpi_stp_py3"; 92 "ulpi_stp_py3";
102 nvidia,function = "spi1"; 93 nvidia,function = "spi1";
103 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 94 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
104 nvidia,tristate = <TEGRA_PIN_DISABLE>; 95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
105 }; 96 };
106 sdmmc3_dat6_pd3 { 97 sdmmc3_dat6_pd3 {
107 nvidia,pins = "sdmmc3_dat6_pd3", 98 nvidia,pins = "sdmmc3_dat6_pd3",
108 "sdmmc3_dat7_pd4"; 99 "sdmmc3_dat7_pd4";
109 nvidia,function = "spdif"; 100 nvidia,function = "spdif";
110 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <TEGRA_PIN_ENABLE>; 102 nvidia,tristate = <TEGRA_PIN_ENABLE>;
@@ -113,14 +104,14 @@
113 104
114 /* Colibri UART_A */ 105 /* Colibri UART_A */
115 ulpi_data0 { 106 ulpi_data0 {
116 nvidia,pins = "ulpi_data0_po1", 107 nvidia,pins = "ulpi_data0_po1",
117 "ulpi_data1_po2", 108 "ulpi_data1_po2",
118 "ulpi_data2_po3", 109 "ulpi_data2_po3",
119 "ulpi_data3_po4", 110 "ulpi_data3_po4",
120 "ulpi_data4_po5", 111 "ulpi_data4_po5",
121 "ulpi_data5_po6", 112 "ulpi_data5_po6",
122 "ulpi_data6_po7", 113 "ulpi_data6_po7",
123 "ulpi_data7_po0"; 114 "ulpi_data7_po0";
124 nvidia,function = "uarta"; 115 nvidia,function = "uarta";
125 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 116 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126 nvidia,tristate = <TEGRA_PIN_DISABLE>; 117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -128,10 +119,10 @@
128 119
129 /* Colibri UART_B */ 120 /* Colibri UART_B */
130 gmi_a16_pj7 { 121 gmi_a16_pj7 {
131 nvidia,pins = "gmi_a16_pj7", 122 nvidia,pins = "gmi_a16_pj7",
132 "gmi_a17_pb0", 123 "gmi_a17_pb0",
133 "gmi_a18_pb1", 124 "gmi_a18_pb1",
134 "gmi_a19_pk7"; 125 "gmi_a19_pk7";
135 nvidia,function = "uartd"; 126 nvidia,function = "uartd";
136 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
137 nvidia,tristate = <TEGRA_PIN_DISABLE>; 128 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -139,8 +130,8 @@
139 130
140 /* Colibri UART_C */ 131 /* Colibri UART_C */
141 uart2_rxd { 132 uart2_rxd {
142 nvidia,pins = "uart2_rxd_pc3", 133 nvidia,pins = "uart2_rxd_pc3",
143 "uart2_txd_pc2"; 134 "uart2_txd_pc2";
144 nvidia,function = "uartb"; 135 nvidia,function = "uartb";
145 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 136 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
146 nvidia,tristate = <TEGRA_PIN_DISABLE>; 137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -148,25 +139,59 @@
148 139
149 /* eMMC */ 140 /* eMMC */
150 sdmmc4_clk_pcc4 { 141 sdmmc4_clk_pcc4 {
151 nvidia,pins = "sdmmc4_clk_pcc4", 142 nvidia,pins = "sdmmc4_clk_pcc4",
152 "sdmmc4_rst_n_pcc3"; 143 "sdmmc4_rst_n_pcc3";
153 nvidia,function = "sdmmc4"; 144 nvidia,function = "sdmmc4";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 145 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>; 146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 }; 147 };
157 sdmmc4_dat0_paa0 { 148 sdmmc4_dat0_paa0 {
158 nvidia,pins = "sdmmc4_dat0_paa0", 149 nvidia,pins = "sdmmc4_dat0_paa0",
159 "sdmmc4_dat1_paa1", 150 "sdmmc4_dat1_paa1",
160 "sdmmc4_dat2_paa2", 151 "sdmmc4_dat2_paa2",
161 "sdmmc4_dat3_paa3", 152 "sdmmc4_dat3_paa3",
162 "sdmmc4_dat4_paa4", 153 "sdmmc4_dat4_paa4",
163 "sdmmc4_dat5_paa5", 154 "sdmmc4_dat5_paa5",
164 "sdmmc4_dat6_paa6", 155 "sdmmc4_dat6_paa6",
165 "sdmmc4_dat7_paa7"; 156 "sdmmc4_dat7_paa7";
166 nvidia,function = "sdmmc4"; 157 nvidia,function = "sdmmc4";
167 nvidia,pull = <TEGRA_PIN_PULL_UP>; 158 nvidia,pull = <TEGRA_PIN_PULL_UP>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>; 159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 }; 160 };
161
162 /* Power I2C (On-module) */
163 pwr_i2c_scl_pz6 {
164 nvidia,pins = "pwr_i2c_scl_pz6",
165 "pwr_i2c_sda_pz7";
166 nvidia,function = "i2cpwr";
167 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
170 nvidia,lock = <TEGRA_PIN_DISABLE>;
171 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
172 };
173
174 /*
175 * THERMD_ALERT#, unlatched I2C address pin of LM95245
176 * temperature sensor therefore requires disabling for
177 * now
178 */
179 lcd_dc1_pd2 {
180 nvidia,pins = "lcd_dc1_pd2";
181 nvidia,function = "rsvd3";
182 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
183 nvidia,tristate = <TEGRA_PIN_DISABLE>;
184 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
185 };
186
187 /* TOUCH_PEN_INT# */
188 pv0 {
189 nvidia,pins = "pv0";
190 nvidia,function = "rsvd1";
191 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
192 nvidia,tristate = <TEGRA_PIN_DISABLE>;
193 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
194 };
170 }; 195 };
171 }; 196 };
172 197
@@ -236,7 +261,7 @@
236 /* 261 /*
237 * EN_+V3.3 switching via FET: 262 * EN_+V3.3 switching via FET:
238 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN 263 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
239 * see also v3_3 fixed supply 264 * see also 3v3 fixed supply
240 */ 265 */
241 ldo2_reg: ldo2 { 266 ldo2_reg: ldo2 {
242 regulator-name = "en_3v3"; 267 regulator-name = "en_3v3";
@@ -295,6 +320,46 @@
295 }; 320 };
296 }; 321 };
297 322
323 /* STMPE811 touch screen controller */
324 stmpe811@41 {
325 compatible = "st,stmpe811";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 reg = <0x41>;
329 interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
330 interrupt-parent = <&gpio>;
331 interrupt-controller;
332 id = <0>;
333 blocks = <0x5>;
334 irq-trigger = <0x1>;
335
336 stmpe_touchscreen {
337 compatible = "st,stmpe-ts";
338 reg = <0>;
339 /* 3.25 MHz ADC clock speed */
340 st,adc-freq = <1>;
341 /* 8 sample average control */
342 st,ave-ctrl = <3>;
343 /* 7 length fractional part in z */
344 st,fraction-z = <7>;
345 /*
346 * 50 mA typical 80 mA max touchscreen drivers
347 * current limit value
348 */
349 st,i-drive = <1>;
350 /* 12-bit ADC */
351 st,mod-12b = <1>;
352 /* internal ADC reference */
353 st,ref-sel = <0>;
354 /* ADC converstion time: 80 clocks */
355 st,sample-time = <4>;
356 /* 1 ms panel driver settling time */
357 st,settling = <3>;
358 /* 5 ms touch detect interrupt delay */
359 st,touch-det-delay = <5>;
360 };
361 };
362
298 /* 363 /*
299 * LM95245 temperature sensor 364 * LM95245 temperature sensor
300 * Note: OVERT_N directly connected to PMIC PWRDN 365 * Note: OVERT_N directly connected to PMIC PWRDN
@@ -331,7 +396,8 @@
331 nvidia,sys-clock-req-active-high; 396 nvidia,sys-clock-req-active-high;
332 }; 397 };
333 398
334 emmc: sdhci@78000600 { 399 /* eMMC */
400 sdhci@78000600 {
335 status = "okay"; 401 status = "okay";
336 bus-width = <8>; 402 bus-width = <8>;
337 non-removable; 403 non-removable;
@@ -365,18 +431,40 @@
365 #address-cells = <1>; 431 #address-cells = <1>;
366 #size-cells = <0>; 432 #size-cells = <0>;
367 433
368 sys_3v3_reg: regulator@100 { 434 avdd_hdmi_pll_1v8_reg: regulator@100 {
369 compatible = "regulator-fixed"; 435 compatible = "regulator-fixed";
370 reg = <100>; 436 reg = <100>;
437 regulator-name = "+V1.8_AVDD_HDMI_PLL";
438 regulator-min-microvolt = <1800000>;
439 regulator-max-microvolt = <1800000>;
440 enable-active-high;
441 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
442 vin-supply = <&vio_reg>;
443 };
444
445 sys_3v3_reg: regulator@101 {
446 compatible = "regulator-fixed";
447 reg = <101>;
371 regulator-name = "3v3"; 448 regulator-name = "3v3";
372 regulator-min-microvolt = <3300000>; 449 regulator-min-microvolt = <3300000>;
373 regulator-max-microvolt = <3300000>; 450 regulator-max-microvolt = <3300000>;
374 regulator-always-on; 451 regulator-always-on;
375 }; 452 };
376 453
377 charge_pump_5v0_reg: regulator@101 { 454 avdd_hdmi_3v3_reg: regulator@102 {
378 compatible = "regulator-fixed"; 455 compatible = "regulator-fixed";
379 reg = <101>; 456 reg = <102>;
457 regulator-name = "+V3.3_AVDD_HDMI";
458 regulator-min-microvolt = <3300000>;
459 regulator-max-microvolt = <3300000>;
460 enable-active-high;
461 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
462 vin-supply = <&sys_3v3_reg>;
463 };
464
465 charge_pump_5v0_reg: regulator@103 {
466 compatible = "regulator-fixed";
467 reg = <103>;
380 regulator-name = "5v0"; 468 regulator-name = "5v0";
381 regulator-min-microvolt = <5000000>; 469 regulator-min-microvolt = <5000000>;
382 regulator-max-microvolt = <5000000>; 470 regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index fe04fb5e155f..38e1e276bafc 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -42,8 +42,8 @@
42 <&tegra_car TEGRA30_CLK_CML0>; 42 <&tegra_car TEGRA30_CLK_CML0>;
43 clock-names = "pex", "afi", "pll_e", "cml"; 43 clock-names = "pex", "afi", "pll_e", "cml";
44 resets = <&tegra_car 70>, 44 resets = <&tegra_car 70>,
45 <&tegra_car 72>, 45 <&tegra_car 72>,
46 <&tegra_car 74>; 46 <&tegra_car 74>;
47 reset-names = "pex", "afi", "pcie_x"; 47 reset-names = "pex", "afi", "pcie_x";
48 status = "disabled"; 48 status = "disabled";
49 49
@@ -153,7 +153,7 @@
153 &tegra_car TEGRA30_CLK_GR3D2>; 153 &tegra_car TEGRA30_CLK_GR3D2>;
154 clock-names = "3d", "3d2"; 154 clock-names = "3d", "3d2";
155 resets = <&tegra_car 24>, 155 resets = <&tegra_car 24>,
156 <&tegra_car 98>; 156 <&tegra_car 98>;
157 reset-names = "3d", "3d2"; 157 reset-names = "3d", "3d2";
158 }; 158 };
159 159
@@ -455,7 +455,7 @@
455 }; 455 };
456 456
457 i2c@7000c000 { 457 i2c@7000c000 {
458 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 458 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
459 reg = <0x7000c000 0x100>; 459 reg = <0x7000c000 0x100>;
460 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 460 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
461 #address-cells = <1>; 461 #address-cells = <1>;
@@ -660,7 +660,7 @@
660 reg = <0x70030000 0x10000>; 660 reg = <0x70030000 0x10000>;
661 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 661 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&tegra_car TEGRA30_CLK_HDA>, 662 clocks = <&tegra_car TEGRA30_CLK_HDA>,
663 <&tegra_car TEGRA30_CLK_HDA2HDMI>, 663 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
664 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; 664 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
665 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 665 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
666 resets = <&tegra_car 125>, /* hda */ 666 resets = <&tegra_car 125>, /* hda */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 10:02:08 -0400