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authorLinus Torvalds <torvalds@linux-foundation.org>2019-07-16 15:17:07 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2019-07-16 15:17:07 -0400
commit3e859477a1db52a0435d06a55fdb54f62d69c292 (patch)
tree057daeae3cc56a459ef5534b8c6cce8181c0c662
parent1ec4013bab89058dcc594dfe7b5a20f5d46bbc5f (diff)
parent775f1f7eacede583ec25ed56e58c4483f2b29265 (diff)
Merge tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa
Pull Xtensa updates from Max Filippov: - clean up PCI support code - add defconfig and DTS for the 'virt' board - abstract 'entry' and 'retw' uses in xtensa assembly in preparation for XEA3/NX pipeline support - random small cleanups * tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa: xtensa: virt: add defconfig and DTS xtensa: abstract 'entry' and 'retw' in assembly code xtensa: One function call less in bootmem_init() xtensa: remove arch/xtensa/include/asm/types.h xtensa: use generic pcibios_set_master and pcibios_enable_device xtensa: drop dead PCI support code xtensa/PCI: Remove unused variable
Diffstat
-rw-r--r--arch/xtensa/boot/dts/virt.dts72
-rw-r--r--arch/xtensa/configs/virt_defconfig113
-rw-r--r--arch/xtensa/include/asm/asmmacro.h46
-rw-r--r--arch/xtensa/include/asm/platform.h10
-rw-r--r--arch/xtensa/include/asm/types.h23
-rw-r--r--arch/xtensa/kernel/coprocessor.S7
-rw-r--r--arch/xtensa/kernel/entry.S11
-rw-r--r--arch/xtensa/kernel/mcount.S11
-rw-r--r--arch/xtensa/kernel/pci.c124
-rw-r--r--arch/xtensa/kernel/platform.c2
-rw-r--r--arch/xtensa/kernel/setup.c4
-rw-r--r--arch/xtensa/lib/checksum.S12
-rw-r--r--arch/xtensa/lib/memcopy.S38
-rw-r--r--arch/xtensa/lib/memset.S10
-rw-r--r--arch/xtensa/lib/strncpy_user.S16
-rw-r--r--arch/xtensa/lib/strnlen_user.S14
-rw-r--r--arch/xtensa/lib/usercopy.S12
-rw-r--r--arch/xtensa/mm/init.c5
-rw-r--r--arch/xtensa/mm/misc.S78
19 files changed, 339 insertions, 269 deletions
diff --git a/arch/xtensa/boot/dts/virt.dts b/arch/xtensa/boot/dts/virt.dts
new file mode 100644
index 000000000000..6aecbc0f3549
--- /dev/null
+++ b/arch/xtensa/boot/dts/virt.dts
@@ -0,0 +1,72 @@
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4/ {
5 compatible = "cdns,xtensa-iss";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&pic>;
9
10 chosen {
11 bootargs = "console=ttyS0,115200n8 debug";
12 };
13
14 memory@0 {
15 device_type = "memory";
16 reg = <0x00000000 0x80000000>;
17 };
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22 cpu@0 {
23 compatible = "cdns,xtensa-cpu";
24 reg = <0>;
25 clocks = <&osc>;
26 };
27 };
28
29 clocks {
30 osc: osc {
31 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-frequency = <40000000>;
34 };
35 };
36
37 pic: pic {
38 compatible = "cdns,xtensa-pic";
39 /* one cell: internal irq number,
40 * two cells: second cell == 0: internal irq number
41 * second cell == 1: external irq number
42 */
43 #address-cells = <0>;
44 #interrupt-cells = <2>;
45 interrupt-controller;
46 };
47
48 pci {
49 compatible = "pci-host-ecam-generic";
50 device_type = "pci";
51 #address-cells = <3>;
52 #size-cells = <2>;
53 #interrupt-cells = <0x1>;
54
55 bus-range = <0x0 0x3f>;
56 reg = <0xc0000000 0x04000000>;
57
58 // BUS_ADDRESS(3) CPU_PHYSICAL(1) SIZE(2)
59 ranges = <0x01000000 0x0 0xc4000000 0xc4000000 0x0 0x04000000>,
60 <0x02000000 0x0 0xc8000000 0xc8000000 0x0 0x18000000>;
61
62 // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(2)
63 interrupt-map = <
64 0x0000 0x0 0x0 0x1 &pic 0x0 0x1
65 0x0800 0x0 0x0 0x1 &pic 0x1 0x1
66 0x1000 0x0 0x0 0x1 &pic 0x2 0x1
67 0x1800 0x0 0x0 0x1 &pic 0x3 0x1
68 >;
69
70 interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
71 };
72};
diff --git a/arch/xtensa/configs/virt_defconfig b/arch/xtensa/configs/virt_defconfig
new file mode 100644
index 000000000000..bfc45a138e72
--- /dev/null
+++ b/arch/xtensa/configs/virt_defconfig
@@ -0,0 +1,113 @@
1CONFIG_SYSVIPC=y
2CONFIG_POSIX_MQUEUE=y
3CONFIG_NO_HZ_IDLE=y
4CONFIG_HIGH_RES_TIMERS=y
5CONFIG_PREEMPT=y
6CONFIG_IRQ_TIME_ACCOUNTING=y
7CONFIG_BSD_PROCESS_ACCT=y
8CONFIG_MEMCG=y
9CONFIG_CGROUP_FREEZER=y
10CONFIG_CGROUP_DEVICE=y
11CONFIG_CGROUP_CPUACCT=y
12CONFIG_CGROUP_DEBUG=y
13CONFIG_NAMESPACES=y
14CONFIG_SCHED_AUTOGROUP=y
15CONFIG_RELAY=y
16CONFIG_BLK_DEV_INITRD=y
17CONFIG_EXPERT=y
18CONFIG_SYSCTL_SYSCALL=y
19CONFIG_KALLSYMS_ALL=y
20CONFIG_PERF_EVENTS=y
21CONFIG_XTENSA_VARIANT_DC233C=y
22CONFIG_XTENSA_UNALIGNED_USER=y
23CONFIG_VECTORS_OFFSET=0x00002000
24CONFIG_XTENSA_KSEG_512M=y
25CONFIG_HIGHMEM=y
26CONFIG_CMDLINE_BOOL=y
27CONFIG_CMDLINE="console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x80000000@0"
28CONFIG_USE_OF=y
29CONFIG_BUILTIN_DTB_SOURCE="virt"
30# CONFIG_PARSE_BOOTPARAM is not set
31CONFIG_JUMP_LABEL=y
32CONFIG_MODULES=y
33CONFIG_MODULE_UNLOAD=y
34# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
35# CONFIG_COMPACTION is not set
36CONFIG_NET=y
37CONFIG_PACKET=y
38CONFIG_UNIX=y
39CONFIG_INET=y
40CONFIG_IP_MULTICAST=y
41CONFIG_IP_PNP=y
42CONFIG_IP_PNP_DHCP=y
43CONFIG_IP_PNP_BOOTP=y
44CONFIG_IP_PNP_RARP=y
45# CONFIG_IPV6 is not set
46CONFIG_NETFILTER=y
47# CONFIG_WIRELESS is not set
48CONFIG_PCI=y
49CONFIG_PCI_HOST_GENERIC=y
50CONFIG_UEVENT_HELPER=y
51CONFIG_DEVTMPFS=y
52CONFIG_DEVTMPFS_MOUNT=y
53# CONFIG_STANDALONE is not set
54CONFIG_BLK_DEV_LOOP=y
55CONFIG_BLK_DEV_RAM=y
56CONFIG_VIRTIO_BLK=y
57CONFIG_SCSI=y
58CONFIG_BLK_DEV_SD=y
59CONFIG_NETDEVICES=y
60CONFIG_VIRTIO_NET=y
61# CONFIG_ETHERNET is not set
62# CONFIG_WLAN is not set
63CONFIG_INPUT_MOUSEDEV=y
64CONFIG_INPUT_EVDEV=y
65# CONFIG_INPUT_KEYBOARD is not set
66# CONFIG_LEGACY_PTYS is not set
67CONFIG_HW_RANDOM=y
68CONFIG_HW_RANDOM_VIRTIO=y
69# CONFIG_HWMON is not set
70CONFIG_DRM=y
71CONFIG_DRM_VGEM=y
72CONFIG_DRM_VIRTIO_GPU=y
73CONFIG_FB_MODE_HELPERS=y
74# CONFIG_VGA_CONSOLE is not set
75CONFIG_FRAMEBUFFER_CONSOLE=y
76CONFIG_LOGO=y
77# CONFIG_USB_SUPPORT is not set
78CONFIG_VIRTIO_PCI=y
79CONFIG_VIRTIO_INPUT=y
80# CONFIG_IOMMU_SUPPORT is not set
81CONFIG_EXT3_FS=y
82CONFIG_FANOTIFY=y
83CONFIG_VFAT_FS=y
84CONFIG_PROC_KCORE=y
85CONFIG_TMPFS=y
86CONFIG_TMPFS_POSIX_ACL=y
87CONFIG_NFS_FS=y
88CONFIG_NFS_V4=y
89CONFIG_NFS_SWAP=y
90CONFIG_ROOT_NFS=y
91CONFIG_SUNRPC_DEBUG=y
92CONFIG_NLS_CODEPAGE_437=y
93CONFIG_NLS_ISO8859_1=y
94CONFIG_CRYPTO_ECHAINIV=y
95CONFIG_CRYPTO_DEFLATE=y
96CONFIG_CRYPTO_LZO=y
97CONFIG_CRYPTO_ANSI_CPRNG=y
98CONFIG_CRYPTO_DEV_VIRTIO=y
99CONFIG_FONTS=y
100CONFIG_PRINTK_TIME=y
101CONFIG_DYNAMIC_DEBUG=y
102CONFIG_DEBUG_INFO=y
103CONFIG_MAGIC_SYSRQ=y
104# CONFIG_SCHED_DEBUG is not set
105CONFIG_SCHEDSTATS=y
106CONFIG_DEBUG_RT_MUTEXES=y
107CONFIG_DEBUG_SPINLOCK=y
108CONFIG_DEBUG_MUTEXES=y
109CONFIG_DEBUG_ATOMIC_SLEEP=y
110CONFIG_STACKTRACE=y
111CONFIG_RCU_TRACE=y
112# CONFIG_FTRACE is not set
113# CONFIG_S32C1I_SELFTEST is not set
diff --git a/arch/xtensa/include/asm/asmmacro.h b/arch/xtensa/include/asm/asmmacro.h
index 8308a9c3abb2..71a7e846bc1f 100644
--- a/arch/xtensa/include/asm/asmmacro.h
+++ b/arch/xtensa/include/asm/asmmacro.h
@@ -191,4 +191,50 @@
191#endif 191#endif
192 .endm 192 .endm
193 193
194#define XTENSA_STACK_ALIGNMENT 16
195
196#if defined(__XTENSA_WINDOWED_ABI__)
197#define XTENSA_FRAME_SIZE_RESERVE 16
198#define XTENSA_SPILL_STACK_RESERVE 32
199
200#define abi_entry(frame_size) \
201 entry sp, (XTENSA_FRAME_SIZE_RESERVE + \
202 (((frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \
203 -XTENSA_STACK_ALIGNMENT))
204#define abi_entry_default abi_entry(0)
205
206#define abi_ret(frame_size) retw
207#define abi_ret_default retw
208
209#elif defined(__XTENSA_CALL0_ABI__)
210
211#define XTENSA_SPILL_STACK_RESERVE 0
212
213#define abi_entry(frame_size) __abi_entry (frame_size)
214
215 .macro __abi_entry frame_size
216 .ifgt \frame_size
217 addi sp, sp, -(((\frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \
218 -XTENSA_STACK_ALIGNMENT)
219 .endif
220 .endm
221
222#define abi_entry_default
223
224#define abi_ret(frame_size) __abi_ret (frame_size)
225
226 .macro __abi_ret frame_size
227 .ifgt \frame_size
228 addi sp, sp, (((\frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \
229 -XTENSA_STACK_ALIGNMENT)
230 .endif
231 ret
232 .endm
233
234#define abi_ret_default ret
235
236#else
237#error Unsupported Xtensa ABI
238#endif
239
194#endif /* _XTENSA_ASMMACRO_H */ 240#endif /* _XTENSA_ASMMACRO_H */
diff --git a/arch/xtensa/include/asm/platform.h b/arch/xtensa/include/asm/platform.h
index 560483356a06..913826dfa838 100644
--- a/arch/xtensa/include/asm/platform.h
+++ b/arch/xtensa/include/asm/platform.h
@@ -55,16 +55,6 @@ extern void platform_idle (void);
55extern void platform_heartbeat (void); 55extern void platform_heartbeat (void);
56 56
57/* 57/*
58 * platform_pcibios_init is called to allow the platform to setup the pci bus.
59 */
60extern void platform_pcibios_init (void);
61
62/*
63 * platform_pcibios_fixup allows to modify the PCI configuration.
64 */
65extern int platform_pcibios_fixup (void);
66
67/*
68 * platform_calibrate_ccount calibrates cpu clock freq (CONFIG_XTENSA_CALIBRATE) 58 * platform_calibrate_ccount calibrates cpu clock freq (CONFIG_XTENSA_CALIBRATE)
69 */ 59 */
70extern void platform_calibrate_ccount (void); 60extern void platform_calibrate_ccount (void);
diff --git a/arch/xtensa/include/asm/types.h b/arch/xtensa/include/asm/types.h
deleted file mode 100644
index 2b410b8c7f79..000000000000
--- a/arch/xtensa/include/asm/types.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * include/asm-xtensa/types.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10#ifndef _XTENSA_TYPES_H
11#define _XTENSA_TYPES_H
12
13#include <uapi/asm/types.h>
14
15#ifndef __ASSEMBLY__
16/*
17 * These aren't exported outside the kernel to avoid name space clashes
18 */
19
20#define BITS_PER_LONG 32
21
22#endif
23#endif /* _XTENSA_TYPES_H */
diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coprocessor.S
index 92bf24a9da92..60c220020054 100644
--- a/arch/xtensa/kernel/coprocessor.S
+++ b/arch/xtensa/kernel/coprocessor.S
@@ -121,7 +121,9 @@
121 121
122ENTRY(coprocessor_flush) 122ENTRY(coprocessor_flush)
123 123
124 entry a1, 32 124 /* reserve 4 bytes on stack to save a0 */
125 abi_entry(4)
126
125 s32i a0, a1, 0 127 s32i a0, a1, 0
126 movi a0, .Lsave_cp_regs_jump_table 128 movi a0, .Lsave_cp_regs_jump_table
127 addx8 a3, a3, a0 129 addx8 a3, a3, a0
@@ -131,7 +133,8 @@ ENTRY(coprocessor_flush)
131 beqz a3, 1f 133 beqz a3, 1f
132 callx0 a3 134 callx0 a3
1331: l32i a0, a1, 0 1351: l32i a0, a1, 0
134 retw 136
137 abi_ret(4)
135 138
136ENDPROC(coprocessor_flush) 139ENDPROC(coprocessor_flush)
137 140
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index e54af8b7e0f8..183fa8e0bb5b 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -1842,7 +1842,8 @@ ENDPROC(fast_store_prohibited)
1842 1842
1843ENTRY(system_call) 1843ENTRY(system_call)
1844 1844
1845 entry a1, 32 1845 /* reserve 4 bytes on stack for function parameter */
1846 abi_entry(4)
1846 1847
1847 /* regs->syscall = regs->areg[2] */ 1848 /* regs->syscall = regs->areg[2] */
1848 1849
@@ -1892,7 +1893,7 @@ ENTRY(system_call)
1892 1893
1893 s32i a6, a2, PT_AREG2 1894 s32i a6, a2, PT_AREG2
1894 bnez a3, 1f 1895 bnez a3, 1f
1895 retw 1896 abi_ret(4)
1896 1897
18971: 18981:
1898 l32i a4, a1, 4 1899 l32i a4, a1, 4
@@ -1901,7 +1902,7 @@ ENTRY(system_call)
1901 mov a6, a2 1902 mov a6, a2
1902 call4 do_syscall_trace_leave 1903 call4 do_syscall_trace_leave
1903 s32i a3, a2, PT_SYSCALL 1904 s32i a3, a2, PT_SYSCALL
1904 retw 1905 abi_ret(4)
1905 1906
1906ENDPROC(system_call) 1907ENDPROC(system_call)
1907 1908
@@ -1952,7 +1953,7 @@ ENDPROC(system_call)
1952 1953
1953ENTRY(_switch_to) 1954ENTRY(_switch_to)
1954 1955
1955 entry a1, 48 1956 abi_entry(XTENSA_SPILL_STACK_RESERVE)
1956 1957
1957 mov a11, a3 # and 'next' (a3) 1958 mov a11, a3 # and 'next' (a3)
1958 1959
@@ -2013,7 +2014,7 @@ ENTRY(_switch_to)
2013 wsr a14, ps 2014 wsr a14, ps
2014 rsync 2015 rsync
2015 2016
2016 retw 2017 abi_ret(XTENSA_SPILL_STACK_RESERVE)
2017 2018
2018ENDPROC(_switch_to) 2019ENDPROC(_switch_to)
2019 2020
diff --git a/arch/xtensa/kernel/mcount.S b/arch/xtensa/kernel/mcount.S
index 0eeda2e4a25e..5e4619f52858 100644
--- a/arch/xtensa/kernel/mcount.S
+++ b/arch/xtensa/kernel/mcount.S
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <asm/asmmacro.h>
14#include <asm/ftrace.h> 15#include <asm/ftrace.h>
15 16
16/* 17/*
@@ -21,13 +22,13 @@
21 22
22ENTRY(_mcount) 23ENTRY(_mcount)
23 24
24 entry a1, 16 25 abi_entry_default
25 26
26 movi a4, ftrace_trace_function 27 movi a4, ftrace_trace_function
27 l32i a4, a4, 0 28 l32i a4, a4, 0
28 movi a3, ftrace_stub 29 movi a3, ftrace_stub
29 bne a3, a4, 1f 30 bne a3, a4, 1f
30 retw 31 abi_ret_default
31 32
321: xor a7, a2, a1 331: xor a7, a2, a1
33 movi a3, 0x3fffffff 34 movi a3, 0x3fffffff
@@ -40,11 +41,11 @@ ENTRY(_mcount)
40 addi a6, a6, -MCOUNT_INSN_SIZE 41 addi a6, a6, -MCOUNT_INSN_SIZE
41 callx4 a4 42 callx4 a4
42 43
43 retw 44 abi_ret_default
44 45
45ENDPROC(_mcount) 46ENDPROC(_mcount)
46 47
47ENTRY(ftrace_stub) 48ENTRY(ftrace_stub)
48 entry a1, 16 49 abi_entry_default
49 retw 50 abi_ret_default
50ENDPROC(ftrace_stub) 51ENDPROC(ftrace_stub)
diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c
index 8b823f94e568..3f32e275997a 100644
--- a/arch/xtensa/kernel/pci.c
+++ b/arch/xtensa/kernel/pci.c
@@ -24,23 +24,6 @@
24#include <asm/pci-bridge.h> 24#include <asm/pci-bridge.h>
25#include <asm/platform.h> 25#include <asm/platform.h>
26 26
27/* PCI Controller */
28
29
30/*
31 * pcibios_alloc_controller
32 * pcibios_enable_device
33 * pcibios_fixups
34 * pcibios_align_resource
35 * pcibios_fixup_bus
36 * pci_bus_add_device
37 */
38
39static struct pci_controller *pci_ctrl_head;
40static struct pci_controller **pci_ctrl_tail = &pci_ctrl_head;
41
42static int pci_bus_count;
43
44/* 27/*
45 * We need to avoid collisions with `mirrored' VGA ports 28 * We need to avoid collisions with `mirrored' VGA ports
46 * and other strange ISA hardware, so we always want the 29 * and other strange ISA hardware, so we always want the
@@ -75,81 +58,6 @@ pcibios_align_resource(void *data, const struct resource *res,
75 return start; 58 return start;
76} 59}
77 60
78static void __init pci_controller_apertures(struct pci_controller *pci_ctrl,
79 struct list_head *resources)
80{
81 struct resource *res;
82 unsigned long io_offset;
83 int i;
84
85 io_offset = (unsigned long)pci_ctrl->io_space.base;
86 res = &pci_ctrl->io_resource;
87 if (!res->flags) {
88 if (io_offset)
89 pr_err("I/O resource not set for host bridge %d\n",
90 pci_ctrl->index);
91 res->start = 0;
92 res->end = IO_SPACE_LIMIT;
93 res->flags = IORESOURCE_IO;
94 }
95 res->start += io_offset;
96 res->end += io_offset;
97 pci_add_resource_offset(resources, res, io_offset);
98
99 for (i = 0; i < 3; i++) {
100 res = &pci_ctrl->mem_resources[i];
101 if (!res->flags) {
102 if (i > 0)
103 continue;
104 pr_err("Memory resource not set for host bridge %d\n",
105 pci_ctrl->index);
106 res->start = 0;
107 res->end = ~0U;
108 res->flags = IORESOURCE_MEM;
109 }
110 pci_add_resource(resources, res);
111 }
112}
113
114static int __init pcibios_init(void)
115{
116 struct pci_controller *pci_ctrl;
117 struct list_head resources;
118 struct pci_bus *bus;
119 int next_busno = 0, ret;
120
121 pr_info("PCI: Probing PCI hardware\n");
122
123 /* Scan all of the recorded PCI controllers. */
124 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
125 pci_ctrl->last_busno = 0xff;
126 INIT_LIST_HEAD(&resources);
127 pci_controller_apertures(pci_ctrl, &resources);
128 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
129 pci_ctrl->ops, pci_ctrl, &resources);
130 if (!bus)
131 continue;
132
133 pci_ctrl->bus = bus;
134 pci_ctrl->last_busno = bus->busn_res.end;
135 if (next_busno <= pci_ctrl->last_busno)
136 next_busno = pci_ctrl->last_busno+1;
137 }
138 pci_bus_count = next_busno;
139 ret = platform_pcibios_fixup();
140 if (ret)
141 return ret;
142
143 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
144 if (pci_ctrl->bus)
145 pci_bus_add_devices(pci_ctrl->bus);
146 }
147
148 return 0;
149}
150
151subsys_initcall(pcibios_init);
152
153void pcibios_fixup_bus(struct pci_bus *bus) 61void pcibios_fixup_bus(struct pci_bus *bus)
154{ 62{
155 if (bus->parent) { 63 if (bus->parent) {
@@ -158,38 +66,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
158 } 66 }
159} 67}
160 68
161void pcibios_set_master(struct pci_dev *dev)
162{
163 /* No special bus mastering setup handling */
164}
165
166int pcibios_enable_device(struct pci_dev *dev, int mask)
167{
168 u16 cmd, old_cmd;
169 int idx;
170 struct resource *r;
171
172 pci_read_config_word(dev, PCI_COMMAND, &cmd);
173 old_cmd = cmd;
174 for (idx=0; idx<6; idx++) {
175 r = &dev->resource[idx];
176 if (!r->start && r->end) {
177 pci_err(dev, "can't enable device: resource collisions\n");
178 return -EINVAL;
179 }
180 if (r->flags & IORESOURCE_IO)
181 cmd |= PCI_COMMAND_IO;
182 if (r->flags & IORESOURCE_MEM)
183 cmd |= PCI_COMMAND_MEMORY;
184 }
185 if (cmd != old_cmd) {
186 pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
187 pci_write_config_word(dev, PCI_COMMAND, cmd);
188 }
189
190 return 0;
191}
192
193/* 69/*
194 * Platform support for /proc/bus/pci/X/Y mmap()s. 70 * Platform support for /proc/bus/pci/X/Y mmap()s.
195 * -- paulus. 71 * -- paulus.
diff --git a/arch/xtensa/kernel/platform.c b/arch/xtensa/kernel/platform.c
index 1cf008284dd2..a95ba05b0abe 100644
--- a/arch/xtensa/kernel/platform.c
+++ b/arch/xtensa/kernel/platform.c
@@ -34,8 +34,6 @@ _F(void, halt, (void), { while(1); });
34_F(void, power_off, (void), { while(1); }); 34_F(void, power_off, (void), { while(1); });
35_F(void, idle, (void), { __asm__ __volatile__ ("waiti 0" ::: "memory"); }); 35_F(void, idle, (void), { __asm__ __volatile__ ("waiti 0" ::: "memory"); });
36_F(void, heartbeat, (void), { }); 36_F(void, heartbeat, (void), { });
37_F(int, pcibios_fixup, (void), { return 0; });
38_F(void, pcibios_init, (void), { });
39 37
40#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT 38#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
41_F(void, calibrate_ccount, (void), 39_F(void, calibrate_ccount, (void),
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 176cb46bcf12..5cb8a62e091c 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -405,10 +405,6 @@ void __init setup_arch(char **cmdline_p)
405 conswitchp = &dummy_con; 405 conswitchp = &dummy_con;
406# endif 406# endif
407#endif 407#endif
408
409#ifdef CONFIG_PCI
410 platform_pcibios_init();
411#endif
412} 408}
413 409
414static DEFINE_PER_CPU(struct cpu, cpu_data); 410static DEFINE_PER_CPU(struct cpu, cpu_data);
diff --git a/arch/xtensa/lib/checksum.S b/arch/xtensa/lib/checksum.S
index c6e73b12e519..4cb9ca58d9ad 100644
--- a/arch/xtensa/lib/checksum.S
+++ b/arch/xtensa/lib/checksum.S
@@ -43,7 +43,7 @@ ENTRY(csum_partial)
43 * Experiments with Ethernet and SLIP connections show that buf 43 * Experiments with Ethernet and SLIP connections show that buf
44 * is aligned on either a 2-byte or 4-byte boundary. 44 * is aligned on either a 2-byte or 4-byte boundary.
45 */ 45 */
46 entry sp, 32 46 abi_entry_default
47 extui a5, a2, 0, 2 47 extui a5, a2, 0, 2
48 bnez a5, 8f /* branch if 2-byte aligned */ 48 bnez a5, 8f /* branch if 2-byte aligned */
49 /* Fall-through on common case, 4-byte alignment */ 49 /* Fall-through on common case, 4-byte alignment */
@@ -107,7 +107,7 @@ ENTRY(csum_partial)
107 ONES_ADD(a4, a6) 107 ONES_ADD(a4, a6)
1087: 1087:
109 mov a2, a4 109 mov a2, a4
110 retw 110 abi_ret_default
111 111
112 /* uncommon case, buf is 2-byte aligned */ 112 /* uncommon case, buf is 2-byte aligned */
1138: 1138:
@@ -195,7 +195,7 @@ unsigned int csum_partial_copy_generic (const char *src, char *dst, int len,
195 195
196ENTRY(csum_partial_copy_generic) 196ENTRY(csum_partial_copy_generic)
197 197
198 entry sp, 32 198 abi_entry_default
199 mov a12, a3 199 mov a12, a3
200 mov a11, a4 200 mov a11, a4
201 or a10, a2, a3 201 or a10, a2, a3
@@ -316,7 +316,7 @@ EX(11f) s8i a9, a3, 0
316 ONES_ADD(a5, a9) 316 ONES_ADD(a5, a9)
3178: 3178:
318 mov a2, a5 318 mov a2, a5
319 retw 319 abi_ret_default
320 320
3215: 3215:
322 /* Control branch to here when either src or dst is odd. We 322 /* Control branch to here when either src or dst is odd. We
@@ -383,12 +383,12 @@ ENDPROC(csum_partial_copy_generic)
383 blt a12, a11, .Leloop 383 blt a12, a11, .Leloop
384#endif 384#endif
3852: 3852:
386 retw 386 abi_ret_default
387 387
38811: 38811:
389 movi a2, -EFAULT 389 movi a2, -EFAULT
390 s32i a2, a7, 0 /* dst_err_ptr */ 390 s32i a2, a7, 0 /* dst_err_ptr */
391 movi a2, 0 391 movi a2, 0
392 retw 392 abi_ret_default
393 393
394.previous 394.previous
diff --git a/arch/xtensa/lib/memcopy.S b/arch/xtensa/lib/memcopy.S
index efecfd7ed8cc..582d817979ed 100644
--- a/arch/xtensa/lib/memcopy.S
+++ b/arch/xtensa/lib/memcopy.S
@@ -79,7 +79,7 @@
79 bne a3, a7, .Lnextbyte # continue loop if $a3:src != $a7:src_end 79 bne a3, a7, .Lnextbyte # continue loop if $a3:src != $a7:src_end
80#endif /* !XCHAL_HAVE_LOOPS */ 80#endif /* !XCHAL_HAVE_LOOPS */
81.Lbytecopydone: 81.Lbytecopydone:
82 retw 82 abi_ret_default
83 83
84/* 84/*
85 * Destination is unaligned 85 * Destination is unaligned
@@ -112,7 +112,7 @@
112ENTRY(__memcpy) 112ENTRY(__memcpy)
113WEAK(memcpy) 113WEAK(memcpy)
114 114
115 entry sp, 16 # minimal stack frame 115 abi_entry_default
116 # a2/ dst, a3/ src, a4/ len 116 # a2/ dst, a3/ src, a4/ len
117 mov a5, a2 # copy dst so that a2 is return value 117 mov a5, a2 # copy dst so that a2 is return value
118.Lcommon: 118.Lcommon:
@@ -161,7 +161,7 @@ WEAK(memcpy)
161 bbsi.l a4, 2, .L3 161 bbsi.l a4, 2, .L3
162 bbsi.l a4, 1, .L4 162 bbsi.l a4, 1, .L4
163 bbsi.l a4, 0, .L5 163 bbsi.l a4, 0, .L5
164 retw 164 abi_ret_default
165.L3: 165.L3:
166 # copy 4 bytes 166 # copy 4 bytes
167 l32i a6, a3, 0 167 l32i a6, a3, 0
@@ -170,7 +170,7 @@ WEAK(memcpy)
170 addi a5, a5, 4 170 addi a5, a5, 4
171 bbsi.l a4, 1, .L4 171 bbsi.l a4, 1, .L4
172 bbsi.l a4, 0, .L5 172 bbsi.l a4, 0, .L5
173 retw 173 abi_ret_default
174.L4: 174.L4:
175 # copy 2 bytes 175 # copy 2 bytes
176 l16ui a6, a3, 0 176 l16ui a6, a3, 0
@@ -178,12 +178,12 @@ WEAK(memcpy)
178 s16i a6, a5, 0 178 s16i a6, a5, 0
179 addi a5, a5, 2 179 addi a5, a5, 2
180 bbsi.l a4, 0, .L5 180 bbsi.l a4, 0, .L5
181 retw 181 abi_ret_default
182.L5: 182.L5:
183 # copy 1 byte 183 # copy 1 byte
184 l8ui a6, a3, 0 184 l8ui a6, a3, 0
185 s8i a6, a5, 0 185 s8i a6, a5, 0
186 retw 186 abi_ret_default
187 187
188/* 188/*
189 * Destination is aligned, Source is unaligned 189 * Destination is aligned, Source is unaligned
@@ -255,7 +255,7 @@ WEAK(memcpy)
255#endif 255#endif
256 bbsi.l a4, 1, .L14 256 bbsi.l a4, 1, .L14
257 bbsi.l a4, 0, .L15 257 bbsi.l a4, 0, .L15
258.Ldone: retw 258.Ldone: abi_ret_default
259.L14: 259.L14:
260 # copy 2 bytes 260 # copy 2 bytes
261 l8ui a6, a3, 0 261 l8ui a6, a3, 0
@@ -265,12 +265,12 @@ WEAK(memcpy)
265 s8i a7, a5, 1 265 s8i a7, a5, 1
266 addi a5, a5, 2 266 addi a5, a5, 2
267 bbsi.l a4, 0, .L15 267 bbsi.l a4, 0, .L15
268 retw 268 abi_ret_default
269.L15: 269.L15:
270 # copy 1 byte 270 # copy 1 byte
271 l8ui a6, a3, 0 271 l8ui a6, a3, 0
272 s8i a6, a5, 0 272 s8i a6, a5, 0
273 retw 273 abi_ret_default
274 274
275ENDPROC(__memcpy) 275ENDPROC(__memcpy)
276 276
@@ -280,7 +280,7 @@ ENDPROC(__memcpy)
280 280
281ENTRY(bcopy) 281ENTRY(bcopy)
282 282
283 entry sp, 16 # minimal stack frame 283 abi_entry_default
284 # a2=src, a3=dst, a4=len 284 # a2=src, a3=dst, a4=len
285 mov a5, a3 285 mov a5, a3
286 mov a3, a2 286 mov a3, a2
@@ -346,7 +346,7 @@ ENDPROC(bcopy)
346 # $a3:src != $a7:src_start 346 # $a3:src != $a7:src_start
347#endif /* !XCHAL_HAVE_LOOPS */ 347#endif /* !XCHAL_HAVE_LOOPS */
348.Lbackbytecopydone: 348.Lbackbytecopydone:
349 retw 349 abi_ret_default
350 350
351/* 351/*
352 * Destination is unaligned 352 * Destination is unaligned
@@ -380,7 +380,7 @@ ENDPROC(bcopy)
380ENTRY(__memmove) 380ENTRY(__memmove)
381WEAK(memmove) 381WEAK(memmove)
382 382
383 entry sp, 16 # minimal stack frame 383 abi_entry_default
384 # a2/ dst, a3/ src, a4/ len 384 # a2/ dst, a3/ src, a4/ len
385 mov a5, a2 # copy dst so that a2 is return value 385 mov a5, a2 # copy dst so that a2 is return value
386.Lmovecommon: 386.Lmovecommon:
@@ -435,7 +435,7 @@ WEAK(memmove)
435 bbsi.l a4, 2, .Lback3 435 bbsi.l a4, 2, .Lback3
436 bbsi.l a4, 1, .Lback4 436 bbsi.l a4, 1, .Lback4
437 bbsi.l a4, 0, .Lback5 437 bbsi.l a4, 0, .Lback5
438 retw 438 abi_ret_default
439.Lback3: 439.Lback3:
440 # copy 4 bytes 440 # copy 4 bytes
441 addi a3, a3, -4 441 addi a3, a3, -4
@@ -444,7 +444,7 @@ WEAK(memmove)
444 s32i a6, a5, 0 444 s32i a6, a5, 0
445 bbsi.l a4, 1, .Lback4 445 bbsi.l a4, 1, .Lback4
446 bbsi.l a4, 0, .Lback5 446 bbsi.l a4, 0, .Lback5
447 retw 447 abi_ret_default
448.Lback4: 448.Lback4:
449 # copy 2 bytes 449 # copy 2 bytes
450 addi a3, a3, -2 450 addi a3, a3, -2
@@ -452,14 +452,14 @@ WEAK(memmove)
452 addi a5, a5, -2 452 addi a5, a5, -2
453 s16i a6, a5, 0 453 s16i a6, a5, 0
454 bbsi.l a4, 0, .Lback5 454 bbsi.l a4, 0, .Lback5
455 retw 455 abi_ret_default
456.Lback5: 456.Lback5:
457 # copy 1 byte 457 # copy 1 byte
458 addi a3, a3, -1 458 addi a3, a3, -1
459 l8ui a6, a3, 0 459 l8ui a6, a3, 0
460 addi a5, a5, -1 460 addi a5, a5, -1
461 s8i a6, a5, 0 461 s8i a6, a5, 0
462 retw 462 abi_ret_default
463 463
464/* 464/*
465 * Destination is aligned, Source is unaligned 465 * Destination is aligned, Source is unaligned
@@ -531,7 +531,7 @@ WEAK(memmove)
531 bbsi.l a4, 1, .Lback14 531 bbsi.l a4, 1, .Lback14
532 bbsi.l a4, 0, .Lback15 532 bbsi.l a4, 0, .Lback15
533.Lbackdone: 533.Lbackdone:
534 retw 534 abi_ret_default
535.Lback14: 535.Lback14:
536 # copy 2 bytes 536 # copy 2 bytes
537 addi a3, a3, -2 537 addi a3, a3, -2
@@ -541,13 +541,13 @@ WEAK(memmove)
541 s8i a6, a5, 0 541 s8i a6, a5, 0
542 s8i a7, a5, 1 542 s8i a7, a5, 1
543 bbsi.l a4, 0, .Lback15 543 bbsi.l a4, 0, .Lback15
544 retw 544 abi_ret_default
545.Lback15: 545.Lback15:
546 # copy 1 byte 546 # copy 1 byte
547 addi a3, a3, -1 547 addi a3, a3, -1
548 addi a5, a5, -1 548 addi a5, a5, -1
549 l8ui a6, a3, 0 549 l8ui a6, a3, 0
550 s8i a6, a5, 0 550 s8i a6, a5, 0
551 retw 551 abi_ret_default
552 552
553ENDPROC(__memmove) 553ENDPROC(__memmove)
diff --git a/arch/xtensa/lib/memset.S b/arch/xtensa/lib/memset.S
index 8632eacbdc80..59b1524fd601 100644
--- a/arch/xtensa/lib/memset.S
+++ b/arch/xtensa/lib/memset.S
@@ -34,7 +34,7 @@
34ENTRY(__memset) 34ENTRY(__memset)
35WEAK(memset) 35WEAK(memset)
36 36
37 entry sp, 16 # minimal stack frame 37 abi_entry_default
38 # a2/ dst, a3/ c, a4/ length 38 # a2/ dst, a3/ c, a4/ length
39 extui a3, a3, 0, 8 # mask to just 8 bits 39 extui a3, a3, 0, 8 # mask to just 8 bits
40 slli a7, a3, 8 # duplicate character in all bytes of word 40 slli a7, a3, 8 # duplicate character in all bytes of word
@@ -48,7 +48,7 @@ WEAK(memset)
48 srli a7, a4, 4 # number of loop iterations with 16B 48 srli a7, a4, 4 # number of loop iterations with 16B
49 # per iteration 49 # per iteration
50 bnez a4, .Laligned 50 bnez a4, .Laligned
51 retw 51 abi_ret_default
52 52
53/* 53/*
54 * Destination is word-aligned. 54 * Destination is word-aligned.
@@ -95,7 +95,7 @@ EX(10f) s16i a3, a5, 0
95EX(10f) s8i a3, a5, 0 95EX(10f) s8i a3, a5, 0
96.L5: 96.L5:
97.Lret1: 97.Lret1:
98 retw 98 abi_ret_default
99 99
100/* 100/*
101 * Destination is unaligned 101 * Destination is unaligned
@@ -139,7 +139,7 @@ EX(10f) s8i a3, a5, 0
139 blt a5, a6, .Lbyteloop 139 blt a5, a6, .Lbyteloop
140#endif /* !XCHAL_HAVE_LOOPS */ 140#endif /* !XCHAL_HAVE_LOOPS */
141.Lbytesetdone: 141.Lbytesetdone:
142 retw 142 abi_ret_default
143 143
144ENDPROC(__memset) 144ENDPROC(__memset)
145 145
@@ -150,4 +150,4 @@ ENDPROC(__memset)
150 150
15110: 15110:
152 movi a2, 0 152 movi a2, 0
153 retw 153 abi_ret_default
diff --git a/arch/xtensa/lib/strncpy_user.S b/arch/xtensa/lib/strncpy_user.S
index c4c6c8578d59..4faf46fe3f38 100644
--- a/arch/xtensa/lib/strncpy_user.S
+++ b/arch/xtensa/lib/strncpy_user.S
@@ -50,7 +50,7 @@
50.text 50.text
51ENTRY(__strncpy_user) 51ENTRY(__strncpy_user)
52 52
53 entry sp, 16 # minimal stack frame 53 abi_entry_default
54 # a2/ dst, a3/ src, a4/ len 54 # a2/ dst, a3/ src, a4/ len
55 mov a11, a2 # leave dst in return value register 55 mov a11, a2 # leave dst in return value register
56 beqz a4, .Lret # if len is zero 56 beqz a4, .Lret # if len is zero
@@ -93,7 +93,7 @@ EX(10f) s8i a9, a11, 0 # store byte 0
93 bnez a4, .Lsrcaligned # if len is nonzero 93 bnez a4, .Lsrcaligned # if len is nonzero
94.Lret: 94.Lret:
95 sub a2, a11, a2 # compute strlen 95 sub a2, a11, a2 # compute strlen
96 retw 96 abi_ret_default
97 97
98/* 98/*
99 * dst is word-aligned, src is word-aligned 99 * dst is word-aligned, src is word-aligned
@@ -148,14 +148,14 @@ EX(10f) s8i a9, a11, 0
148.Lz3: # byte 3 is zero 148.Lz3: # byte 3 is zero
149 addi a11, a11, 3 # advance dst pointer 149 addi a11, a11, 3 # advance dst pointer
150 sub a2, a11, a2 # compute strlen 150 sub a2, a11, a2 # compute strlen
151 retw 151 abi_ret_default
152.Lz0: # byte 0 is zero 152.Lz0: # byte 0 is zero
153#ifdef __XTENSA_EB__ 153#ifdef __XTENSA_EB__
154 movi a9, 0 154 movi a9, 0
155#endif /* __XTENSA_EB__ */ 155#endif /* __XTENSA_EB__ */
156EX(10f) s8i a9, a11, 0 156EX(10f) s8i a9, a11, 0
157 sub a2, a11, a2 # compute strlen 157 sub a2, a11, a2 # compute strlen
158 retw 158 abi_ret_default
159.Lz1: # byte 1 is zero 159.Lz1: # byte 1 is zero
160#ifdef __XTENSA_EB__ 160#ifdef __XTENSA_EB__
161 extui a9, a9, 16, 16 161 extui a9, a9, 16, 16
@@ -163,7 +163,7 @@ EX(10f) s8i a9, a11, 0
163EX(10f) s16i a9, a11, 0 163EX(10f) s16i a9, a11, 0
164 addi a11, a11, 1 # advance dst pointer 164 addi a11, a11, 1 # advance dst pointer
165 sub a2, a11, a2 # compute strlen 165 sub a2, a11, a2 # compute strlen
166 retw 166 abi_ret_default
167.Lz2: # byte 2 is zero 167.Lz2: # byte 2 is zero
168#ifdef __XTENSA_EB__ 168#ifdef __XTENSA_EB__
169 extui a9, a9, 16, 16 169 extui a9, a9, 16, 16
@@ -173,7 +173,7 @@ EX(10f) s16i a9, a11, 0
173EX(10f) s8i a9, a11, 2 173EX(10f) s8i a9, a11, 2
174 addi a11, a11, 2 # advance dst pointer 174 addi a11, a11, 2 # advance dst pointer
175 sub a2, a11, a2 # compute strlen 175 sub a2, a11, a2 # compute strlen
176 retw 176 abi_ret_default
177 177
178 .align 4 # 1 mod 4 alignment for LOOPNEZ 178 .align 4 # 1 mod 4 alignment for LOOPNEZ
179 .byte 0 # (0 mod 4 alignment for LBEG) 179 .byte 0 # (0 mod 4 alignment for LBEG)
@@ -199,7 +199,7 @@ EX(10f) s8i a9, a11, 0
199 199
200.Lunalignedend: 200.Lunalignedend:
201 sub a2, a11, a2 # compute strlen 201 sub a2, a11, a2 # compute strlen
202 retw 202 abi_ret_default
203 203
204ENDPROC(__strncpy_user) 204ENDPROC(__strncpy_user)
205 205
@@ -214,4 +214,4 @@ ENDPROC(__strncpy_user)
21410: 21410:
21511: 21511:
216 movi a2, -EFAULT 216 movi a2, -EFAULT
217 retw 217 abi_ret_default
diff --git a/arch/xtensa/lib/strnlen_user.S b/arch/xtensa/lib/strnlen_user.S
index 1f2ca2bb2ab3..3d391dca3efb 100644
--- a/arch/xtensa/lib/strnlen_user.S
+++ b/arch/xtensa/lib/strnlen_user.S
@@ -45,7 +45,7 @@
45.text 45.text
46ENTRY(__strnlen_user) 46ENTRY(__strnlen_user)
47 47
48 entry sp, 16 # minimal stack frame 48 abi_entry_default
49 # a2/ s, a3/ len 49 # a2/ s, a3/ len
50 addi a4, a2, -4 # because we overincrement at the end; 50 addi a4, a2, -4 # because we overincrement at the end;
51 # we compensate with load offsets of 4 51 # we compensate with load offsets of 4
@@ -96,7 +96,7 @@ EX(10f) l32i a9, a4, 4 # load 4 bytes for remaining checks
96 addi a4, a4, 1 # advance string pointer 96 addi a4, a4, 1 # advance string pointer
97.L101: 97.L101:
98 sub a2, a4, a2 # compute length 98 sub a2, a4, a2 # compute length
99 retw 99 abi_ret_default
100 100
101# NOTE that in several places below, we point to the byte just after 101# NOTE that in several places below, we point to the byte just after
102# the zero byte in order to include the NULL terminator in the count. 102# the zero byte in order to include the NULL terminator in the count.
@@ -106,15 +106,15 @@ EX(10f) l32i a9, a4, 4 # load 4 bytes for remaining checks
106.Lz0: # byte 0 is zero 106.Lz0: # byte 0 is zero
107 addi a4, a4, 1 # point just beyond zero byte 107 addi a4, a4, 1 # point just beyond zero byte
108 sub a2, a4, a2 # subtract to get length 108 sub a2, a4, a2 # subtract to get length
109 retw 109 abi_ret_default
110.Lz1: # byte 1 is zero 110.Lz1: # byte 1 is zero
111 addi a4, a4, 1+1 # point just beyond zero byte 111 addi a4, a4, 1+1 # point just beyond zero byte
112 sub a2, a4, a2 # subtract to get length 112 sub a2, a4, a2 # subtract to get length
113 retw 113 abi_ret_default
114.Lz2: # byte 2 is zero 114.Lz2: # byte 2 is zero
115 addi a4, a4, 2+1 # point just beyond zero byte 115 addi a4, a4, 2+1 # point just beyond zero byte
116 sub a2, a4, a2 # subtract to get length 116 sub a2, a4, a2 # subtract to get length
117 retw 117 abi_ret_default
118 118
119.L1mod2: # address is odd 119.L1mod2: # address is odd
120EX(10f) l8ui a9, a4, 4 # get byte 0 120EX(10f) l8ui a9, a4, 4 # get byte 0
@@ -130,7 +130,7 @@ EX(10f) l32i a9, a4, 0 # get word with first two bytes of string
130 # byte 3 is zero 130 # byte 3 is zero
131 addi a4, a4, 3+1 # point just beyond zero byte 131 addi a4, a4, 3+1 # point just beyond zero byte
132 sub a2, a4, a2 # subtract to get length 132 sub a2, a4, a2 # subtract to get length
133 retw 133 abi_ret_default
134 134
135ENDPROC(__strnlen_user) 135ENDPROC(__strnlen_user)
136 136
@@ -138,4 +138,4 @@ ENDPROC(__strnlen_user)
138 .align 4 138 .align 4
13910: 13910:
140 movi a2, 0 140 movi a2, 0
141 retw 141 abi_ret_default
diff --git a/arch/xtensa/lib/usercopy.S b/arch/xtensa/lib/usercopy.S
index 228607e30bc2..a0aa4047f94a 100644
--- a/arch/xtensa/lib/usercopy.S
+++ b/arch/xtensa/lib/usercopy.S
@@ -60,7 +60,7 @@
60 .text 60 .text
61ENTRY(__xtensa_copy_user) 61ENTRY(__xtensa_copy_user)
62 62
63 entry sp, 16 # minimal stack frame 63 abi_entry_default
64 # a2/ dst, a3/ src, a4/ len 64 # a2/ dst, a3/ src, a4/ len
65 mov a5, a2 # copy dst so that a2 is return value 65 mov a5, a2 # copy dst so that a2 is return value
66 mov a11, a4 # preserve original len for error case 66 mov a11, a4 # preserve original len for error case
@@ -75,7 +75,7 @@ ENTRY(__xtensa_copy_user)
75 __ssa8 a3 # set shift amount from byte offset 75 __ssa8 a3 # set shift amount from byte offset
76 bnez a4, .Lsrcunaligned 76 bnez a4, .Lsrcunaligned
77 movi a2, 0 # return success for len==0 77 movi a2, 0 # return success for len==0
78 retw 78 abi_ret_default
79 79
80/* 80/*
81 * Destination is unaligned 81 * Destination is unaligned
@@ -127,7 +127,7 @@ EX(10f) s8i a6, a5, 0
127#endif /* !XCHAL_HAVE_LOOPS */ 127#endif /* !XCHAL_HAVE_LOOPS */
128.Lbytecopydone: 128.Lbytecopydone:
129 movi a2, 0 # return success for len bytes copied 129 movi a2, 0 # return success for len bytes copied
130 retw 130 abi_ret_default
131 131
132/* 132/*
133 * Destination and source are word-aligned. 133 * Destination and source are word-aligned.
@@ -187,7 +187,7 @@ EX(10f) l8ui a6, a3, 0
187EX(10f) s8i a6, a5, 0 187EX(10f) s8i a6, a5, 0
188.L5: 188.L5:
189 movi a2, 0 # return success for len bytes copied 189 movi a2, 0 # return success for len bytes copied
190 retw 190 abi_ret_default
191 191
192/* 192/*
193 * Destination is aligned, Source is unaligned 193 * Destination is aligned, Source is unaligned
@@ -264,7 +264,7 @@ EX(10f) l8ui a6, a3, 0
264EX(10f) s8i a6, a5, 0 264EX(10f) s8i a6, a5, 0
265.L15: 265.L15:
266 movi a2, 0 # return success for len bytes copied 266 movi a2, 0 # return success for len bytes copied
267 retw 267 abi_ret_default
268 268
269ENDPROC(__xtensa_copy_user) 269ENDPROC(__xtensa_copy_user)
270 270
@@ -281,4 +281,4 @@ ENDPROC(__xtensa_copy_user)
28110: 28110:
282 sub a2, a5, a2 /* a2 <-- bytes copied */ 282 sub a2, a5, a2 /* a2 <-- bytes copied */
283 sub a2, a11, a2 /* a2 <-- bytes not copied */ 283 sub a2, a11, a2 /* a2 <-- bytes not copied */
284 retw 284 abi_ret_default
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index b51746f2b80b..79467c749416 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -45,10 +45,7 @@ void __init bootmem_init(void)
45 * If PHYS_OFFSET is zero reserve page at address 0: 45 * If PHYS_OFFSET is zero reserve page at address 0:
46 * successfull allocations should never return NULL. 46 * successfull allocations should never return NULL.
47 */ 47 */
48 if (PHYS_OFFSET) 48 memblock_reserve(0, PHYS_OFFSET ? PHYS_OFFSET : 1);
49 memblock_reserve(0, PHYS_OFFSET);
50 else
51 memblock_reserve(0, 1);
52 49
53 early_init_fdt_scan_reserved_mem(); 50 early_init_fdt_scan_reserved_mem();
54 51
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S
index 11a01c3e9cea..6aa036c427c3 100644
--- a/arch/xtensa/mm/misc.S
+++ b/arch/xtensa/mm/misc.S
@@ -30,7 +30,7 @@
30 30
31ENTRY(clear_page) 31ENTRY(clear_page)
32 32
33 entry a1, 16 33 abi_entry_default
34 34
35 movi a3, 0 35 movi a3, 0
36 __loopi a2, a7, PAGE_SIZE, 32 36 __loopi a2, a7, PAGE_SIZE, 32
@@ -44,7 +44,7 @@ ENTRY(clear_page)
44 s32i a3, a2, 28 44 s32i a3, a2, 28
45 __endla a2, a7, 32 45 __endla a2, a7, 32
46 46
47 retw 47 abi_ret_default
48 48
49ENDPROC(clear_page) 49ENDPROC(clear_page)
50 50
@@ -57,7 +57,7 @@ ENDPROC(clear_page)
57 57
58ENTRY(copy_page) 58ENTRY(copy_page)
59 59
60 entry a1, 16 60 abi_entry_default
61 61
62 __loopi a2, a4, PAGE_SIZE, 32 62 __loopi a2, a4, PAGE_SIZE, 32
63 63
@@ -86,7 +86,7 @@ ENTRY(copy_page)
86 86
87 __endl a2, a4 87 __endl a2, a4
88 88
89 retw 89 abi_ret_default
90 90
91ENDPROC(copy_page) 91ENDPROC(copy_page)
92 92
@@ -116,7 +116,7 @@ ENTRY(__tlbtemp_mapping_start)
116 116
117ENTRY(clear_page_alias) 117ENTRY(clear_page_alias)
118 118
119 entry a1, 32 119 abi_entry_default
120 120
121 /* Skip setting up a temporary DTLB if not aliased low page. */ 121 /* Skip setting up a temporary DTLB if not aliased low page. */
122 122
@@ -144,14 +144,14 @@ ENTRY(clear_page_alias)
144 __endla a2, a7, 32 144 __endla a2, a7, 32
145 145
146 bnez a6, 1f 146 bnez a6, 1f
147 retw 147 abi_ret_default
148 148
149 /* We need to invalidate the temporary idtlb entry, if any. */ 149 /* We need to invalidate the temporary idtlb entry, if any. */
150 150
1511: idtlb a4 1511: idtlb a4
152 dsync 152 dsync
153 153
154 retw 154 abi_ret_default
155 155
156ENDPROC(clear_page_alias) 156ENDPROC(clear_page_alias)
157 157
@@ -164,7 +164,7 @@ ENDPROC(clear_page_alias)
164 164
165ENTRY(copy_page_alias) 165ENTRY(copy_page_alias)
166 166
167 entry a1, 32 167 abi_entry_default
168 168
169 /* Skip setting up a temporary DTLB for destination if not aliased. */ 169 /* Skip setting up a temporary DTLB for destination if not aliased. */
170 170
@@ -221,19 +221,19 @@ ENTRY(copy_page_alias)
221 221
222 bnez a6, 1f 222 bnez a6, 1f
223 bnez a7, 2f 223 bnez a7, 2f
224 retw 224 abi_ret_default
225 225
2261: addi a2, a2, -PAGE_SIZE 2261: addi a2, a2, -PAGE_SIZE
227 idtlb a2 227 idtlb a2
228 dsync 228 dsync
229 bnez a7, 2f 229 bnez a7, 2f
230 retw 230 abi_ret_default
231 231
2322: addi a3, a3, -PAGE_SIZE+1 2322: addi a3, a3, -PAGE_SIZE+1
233 idtlb a3 233 idtlb a3
234 dsync 234 dsync
235 235
236 retw 236 abi_ret_default
237 237
238ENDPROC(copy_page_alias) 238ENDPROC(copy_page_alias)
239 239
@@ -248,7 +248,7 @@ ENDPROC(copy_page_alias)
248 248
249ENTRY(__flush_invalidate_dcache_page_alias) 249ENTRY(__flush_invalidate_dcache_page_alias)
250 250
251 entry sp, 16 251 abi_entry_default
252 252
253 movi a7, 0 # required for exception handler 253 movi a7, 0 # required for exception handler
254 addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) 254 addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
@@ -261,7 +261,7 @@ ENTRY(__flush_invalidate_dcache_page_alias)
261 idtlb a4 261 idtlb a4
262 dsync 262 dsync
263 263
264 retw 264 abi_ret_default
265 265
266ENDPROC(__flush_invalidate_dcache_page_alias) 266ENDPROC(__flush_invalidate_dcache_page_alias)
267 267
@@ -272,7 +272,7 @@ ENDPROC(__flush_invalidate_dcache_page_alias)
272 272
273ENTRY(__invalidate_dcache_page_alias) 273ENTRY(__invalidate_dcache_page_alias)
274 274
275 entry sp, 16 275 abi_entry_default
276 276
277 movi a7, 0 # required for exception handler 277 movi a7, 0 # required for exception handler
278 addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) 278 addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
@@ -285,7 +285,7 @@ ENTRY(__invalidate_dcache_page_alias)
285 idtlb a4 285 idtlb a4
286 dsync 286 dsync
287 287
288 retw 288 abi_ret_default
289 289
290ENDPROC(__invalidate_dcache_page_alias) 290ENDPROC(__invalidate_dcache_page_alias)
291#endif 291#endif
@@ -296,7 +296,7 @@ ENTRY(__tlbtemp_mapping_itlb)
296 296
297ENTRY(__invalidate_icache_page_alias) 297ENTRY(__invalidate_icache_page_alias)
298 298
299 entry sp, 16 299 abi_entry_default
300 300
301 addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE) 301 addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE)
302 mov a4, a2 302 mov a4, a2
@@ -307,7 +307,7 @@ ENTRY(__invalidate_icache_page_alias)
307 307
308 iitlb a4 308 iitlb a4
309 isync 309 isync
310 retw 310 abi_ret_default
311 311
312ENDPROC(__invalidate_icache_page_alias) 312ENDPROC(__invalidate_icache_page_alias)
313 313
@@ -325,12 +325,12 @@ ENTRY(__tlbtemp_mapping_end)
325 325
326ENTRY(__invalidate_icache_page) 326ENTRY(__invalidate_icache_page)
327 327
328 entry sp, 16 328 abi_entry_default
329 329
330 ___invalidate_icache_page a2 a3 330 ___invalidate_icache_page a2 a3
331 isync 331 isync
332 332
333 retw 333 abi_ret_default
334 334
335ENDPROC(__invalidate_icache_page) 335ENDPROC(__invalidate_icache_page)
336 336
@@ -340,12 +340,12 @@ ENDPROC(__invalidate_icache_page)
340 340
341ENTRY(__invalidate_dcache_page) 341ENTRY(__invalidate_dcache_page)
342 342
343 entry sp, 16 343 abi_entry_default
344 344
345 ___invalidate_dcache_page a2 a3 345 ___invalidate_dcache_page a2 a3
346 dsync 346 dsync
347 347
348 retw 348 abi_ret_default
349 349
350ENDPROC(__invalidate_dcache_page) 350ENDPROC(__invalidate_dcache_page)
351 351
@@ -355,12 +355,12 @@ ENDPROC(__invalidate_dcache_page)
355 355
356ENTRY(__flush_invalidate_dcache_page) 356ENTRY(__flush_invalidate_dcache_page)
357 357
358 entry sp, 16 358 abi_entry_default
359 359
360 ___flush_invalidate_dcache_page a2 a3 360 ___flush_invalidate_dcache_page a2 a3
361 361
362 dsync 362 dsync
363 retw 363 abi_ret_default
364 364
365ENDPROC(__flush_invalidate_dcache_page) 365ENDPROC(__flush_invalidate_dcache_page)
366 366
@@ -370,12 +370,12 @@ ENDPROC(__flush_invalidate_dcache_page)
370 370
371ENTRY(__flush_dcache_page) 371ENTRY(__flush_dcache_page)
372 372
373 entry sp, 16 373 abi_entry_default
374 374
375 ___flush_dcache_page a2 a3 375 ___flush_dcache_page a2 a3
376 376
377 dsync 377 dsync
378 retw 378 abi_ret_default
379 379
380ENDPROC(__flush_dcache_page) 380ENDPROC(__flush_dcache_page)
381 381
@@ -385,12 +385,12 @@ ENDPROC(__flush_dcache_page)
385 385
386ENTRY(__invalidate_icache_range) 386ENTRY(__invalidate_icache_range)
387 387
388 entry sp, 16 388 abi_entry_default
389 389
390 ___invalidate_icache_range a2 a3 a4 390 ___invalidate_icache_range a2 a3 a4
391 isync 391 isync
392 392
393 retw 393 abi_ret_default
394 394
395ENDPROC(__invalidate_icache_range) 395ENDPROC(__invalidate_icache_range)
396 396
@@ -400,12 +400,12 @@ ENDPROC(__invalidate_icache_range)
400 400
401ENTRY(__flush_invalidate_dcache_range) 401ENTRY(__flush_invalidate_dcache_range)
402 402
403 entry sp, 16 403 abi_entry_default
404 404
405 ___flush_invalidate_dcache_range a2 a3 a4 405 ___flush_invalidate_dcache_range a2 a3 a4
406 dsync 406 dsync
407 407
408 retw 408 abi_ret_default
409 409
410ENDPROC(__flush_invalidate_dcache_range) 410ENDPROC(__flush_invalidate_dcache_range)
411 411
@@ -415,12 +415,12 @@ ENDPROC(__flush_invalidate_dcache_range)
415 415
416ENTRY(__flush_dcache_range) 416ENTRY(__flush_dcache_range)
417 417
418 entry sp, 16 418 abi_entry_default
419 419
420 ___flush_dcache_range a2 a3 a4 420 ___flush_dcache_range a2 a3 a4
421 dsync 421 dsync
422 422
423 retw 423 abi_ret_default
424 424
425ENDPROC(__flush_dcache_range) 425ENDPROC(__flush_dcache_range)
426 426
@@ -430,11 +430,11 @@ ENDPROC(__flush_dcache_range)
430 430
431ENTRY(__invalidate_dcache_range) 431ENTRY(__invalidate_dcache_range)
432 432
433 entry sp, 16 433 abi_entry_default
434 434
435 ___invalidate_dcache_range a2 a3 a4 435 ___invalidate_dcache_range a2 a3 a4
436 436
437 retw 437 abi_ret_default
438 438
439ENDPROC(__invalidate_dcache_range) 439ENDPROC(__invalidate_dcache_range)
440 440
@@ -444,12 +444,12 @@ ENDPROC(__invalidate_dcache_range)
444 444
445ENTRY(__invalidate_icache_all) 445ENTRY(__invalidate_icache_all)
446 446
447 entry sp, 16 447 abi_entry_default
448 448
449 ___invalidate_icache_all a2 a3 449 ___invalidate_icache_all a2 a3
450 isync 450 isync
451 451
452 retw 452 abi_ret_default
453 453
454ENDPROC(__invalidate_icache_all) 454ENDPROC(__invalidate_icache_all)
455 455
@@ -459,12 +459,12 @@ ENDPROC(__invalidate_icache_all)
459 459
460ENTRY(__flush_invalidate_dcache_all) 460ENTRY(__flush_invalidate_dcache_all)
461 461
462 entry sp, 16 462 abi_entry_default
463 463
464 ___flush_invalidate_dcache_all a2 a3 464 ___flush_invalidate_dcache_all a2 a3
465 dsync 465 dsync
466 466
467 retw 467 abi_ret_default
468 468
469ENDPROC(__flush_invalidate_dcache_all) 469ENDPROC(__flush_invalidate_dcache_all)
470 470
@@ -474,11 +474,11 @@ ENDPROC(__flush_invalidate_dcache_all)
474 474
475ENTRY(__invalidate_dcache_all) 475ENTRY(__invalidate_dcache_all)
476 476
477 entry sp, 16 477 abi_entry_default
478 478
479 ___invalidate_dcache_all a2 a3 479 ___invalidate_dcache_all a2 a3
480 dsync 480 dsync
481 481
482 retw 482 abi_ret_default
483 483
484ENDPROC(__invalidate_dcache_all) 484ENDPROC(__invalidate_dcache_all)
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 11:17:42 -0400