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authorOlof Johansson <olof@lixom.net>2017-04-19 09:32:35 -0400
committerOlof Johansson <olof@lixom.net>2017-04-19 09:32:35 -0400
commit3d3949df4e16e8dc501e66b3cf078984fd1b23b6 (patch)
tree0e727216938124777a1c2693440bdcc39fd83515
parent2149ed8d6fcd43cf99a10c3304f84286d64f6eed (diff)
parent18236a14883b718ce973e4c090db6ecb49b38287 (diff)
Merge tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
arm64: tegra: Device tree changes for v4.12-rc1 This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C, SDHCI and GPIO. It also enables various features on the P2771 devkit. A small fix is made to the compatible string list for the flow controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210. * tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Update the Tegra132 flowctrl compatible string arm64: tegra: Add GPU node for Tegra186 arm64: tegra: Enable IOMMU for host1x on Tegra210 arm64: tegra: Enable VIC on Tegra210 arm64: tegra: Add GPIO expanders on P2771 arm64: tegra: Add power monitors on P2771 arm64: tegra: Add GPIO keys on P2771 arm64: tegra: Enable current monitors on P3310 arm64: tegra: Enable SD/MMC slot on P2771 arm64: tegra: Enable SDHCI controllers on P3110 arm64: tegra: Add initial power tree for P3310 arm64: tegra: Enable ethernet on P3310 arm64: tegra: Enable I2C controllers on P3310 arm64: tegra: Invert the PMC interrupt on P3310 arm64: tegra: Add ethernet support for Tegra186 arm64: tegra: Add PMC controller on Tegra186 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra132.dtsi2
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts91
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi319
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi59
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi19
5 files changed, 487 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 3f3a46a4bd01..2b17936ac5be 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -224,7 +224,7 @@
224 }; 224 };
225 225
226 flow-controller@60007000 { 226 flow-controller@60007000 {
227 compatible = "nvidia,tegra124-flowctrl"; 227 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
228 reg = <0x0 0x60007000 0x0 0x1000>; 228 reg = <0x0 0x60007000 0x0 0x1000>;
229 }; 229 };
230 230
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 0d3c0996d832..8daadadec63a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -1,8 +1,99 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/linux-event-codes.h>
4
3#include "tegra186-p3310.dtsi" 5#include "tegra186-p3310.dtsi"
4 6
5/ { 7/ {
6 model = "NVIDIA Tegra186 P2771-0000 Development Board"; 8 model = "NVIDIA Tegra186 P2771-0000 Development Board";
7 compatible = "nvidia,p2771-0000", "nvidia,tegra186"; 9 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
10
11 i2c@3160000 {
12 power-monitor@42 {
13 compatible = "ti,ina3221";
14 reg = <0x42>;
15 };
16
17 power-monitor@43 {
18 compatible = "ti,ina3221";
19 reg = <0x43>;
20 };
21
22 exp1: gpio@74 {
23 compatible = "ti,tca9539";
24 reg = <0x74>;
25
26 interrupt-parent = <&gpio>;
27 interrupts = <TEGRA_MAIN_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
28
29 #gpio-cells = <2>;
30 gpio-controller;
31 };
32
33 exp2: gpio@77 {
34 compatible = "ti,tca9539";
35 reg = <0x77>;
36
37 interrupt-parent = <&gpio>;
38 interrupts = <TEGRA_MAIN_GPIO(Y, 6) GPIO_ACTIVE_LOW>;
39
40 #gpio-cells = <2>;
41 gpio-controller;
42 };
43 };
44
45 /* SDMMC1 (SD/MMC) */
46 sdhci@3400000 {
47 status = "okay";
48
49 vmmc-supply = <&vdd_sd>;
50 };
51
52 gpio-keys {
53 compatible = "gpio-keys";
54
55 power {
56 label = "Power";
57 gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0)
58 GPIO_ACTIVE_LOW>;
59 linux,input-type = <EV_KEY>;
60 linux,code = <KEY_POWER>;
61 debounce-interval = <10>;
62 wakeup-source;
63 };
64
65 volume-up {
66 label = "Volume Up";
67 gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1)
68 GPIO_ACTIVE_LOW>;
69 linux,input-type = <EV_KEY>;
70 linux,code = <KEY_VOLUMEUP>;
71 debounce-interval = <10>;
72 };
73
74 volume-down {
75 label = "Volume Down";
76 gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2)
77 GPIO_ACTIVE_LOW>;
78 linux,input-type = <EV_KEY>;
79 linux,code = <KEY_VOLUMEDOWN>;
80 debounce-interval = <10>;
81 };
82 };
83
84 regulators {
85 vdd_sd: regulator@100 {
86 compatible = "regulator-fixed";
87 reg = <100>;
88
89 regulator-name = "SD_CARD_SW_PWR";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92
93 gpio = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
94 enable-active-high;
95
96 vin-supply = <&vdd_3v3_sys>;
97 };
98 };
8}; 99};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 1abe2eceb3d1..cf84d7046ad5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -1,11 +1,23 @@
1#include "tegra186.dtsi" 1#include "tegra186.dtsi"
2 2
3#include <dt-bindings/mfd/max77620.h>
4
3/ { 5/ {
4 model = "NVIDIA Tegra186 P3310 Processor Module"; 6 model = "NVIDIA Tegra186 P3310 Processor Module";
5 compatible = "nvidia,p3310", "nvidia,tegra186"; 7 compatible = "nvidia,p3310", "nvidia,tegra186";
6 8
7 aliases { 9 aliases {
10 sdhci0 = "/sdhci@3460000";
11 sdhci1 = "/sdhci@3400000";
8 serial0 = &uarta; 12 serial0 = &uarta;
13 i2c0 = "/bpmp/i2c";
14 i2c1 = "/i2c@3160000";
15 i2c2 = "/i2c@c240000";
16 i2c3 = "/i2c@3180000";
17 i2c4 = "/i2c@3190000";
18 i2c5 = "/i2c@31c0000";
19 i2c6 = "/i2c@c250000";
20 i2c7 = "/i2c@31e0000";
9 }; 21 };
10 22
11 chosen { 23 chosen {
@@ -18,14 +30,99 @@
18 reg = <0x0 0x80000000 0x2 0x00000000>; 30 reg = <0x0 0x80000000 0x2 0x00000000>;
19 }; 31 };
20 32
33 ethernet@2490000 {
34 status = "okay";
35
36 phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
37 phy-handle = <&phy>;
38 phy-mode = "rgmii";
39
40 mdio {
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 phy: phy@0 {
45 compatible = "ethernet-phy-ieee802.3-c22";
46 reg = <0x0>;
47 interrupt-parent = <&gpio>;
48 interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_HIGH>;
49 };
50 };
51 };
52
21 serial@3100000 { 53 serial@3100000 {
22 status = "okay"; 54 status = "okay";
23 }; 55 };
24 56
57 i2c@3160000 {
58 status = "okay";
59
60 power-monitor@40 {
61 compatible = "ti,ina3221";
62 reg = <0x40>;
63 };
64
65 power-monitor@41 {
66 compatible = "ti,ina3221";
67 reg = <0x41>;
68 };
69 };
70
71 i2c@3180000 {
72 status = "okay";
73 };
74
75 i2c@3190000 {
76 status = "okay";
77 };
78
79 i2c@31c0000 {
80 status = "okay";
81 };
82
83 i2c@31e0000 {
84 status = "okay";
85 };
86
87 /* SDMMC1 (SD/MMC) */
88 sdhci@3400000 {
89 cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
90 wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;
91
92 vqmmc-supply = <&vddio_sdmmc1>;
93 };
94
95 /* SDMMC3 (SDIO) */
96 sdhci@3440000 {
97 status = "okay";
98 };
99
100 /* SDMMC4 (eMMC) */
101 sdhci@3460000 {
102 status = "okay";
103 bus-width = <8>;
104 non-removable;
105
106 vqmmc-supply = <&vdd_1v8_ap>;
107 vmmc-supply = <&vdd_3v3_sys>;
108 };
109
25 hsp@3c00000 { 110 hsp@3c00000 {
26 status = "okay"; 111 status = "okay";
27 }; 112 };
28 113
114 i2c@c240000 {
115 status = "okay";
116 };
117
118 i2c@c250000 {
119 status = "okay";
120 };
121
122 pmc@c360000 {
123 nvidia,invert-interrupt;
124 };
125
29 cpus { 126 cpus {
30 cpu@0 { 127 cpu@0 {
31 enable-method = "psci"; 128 enable-method = "psci";
@@ -53,7 +150,192 @@
53 }; 150 };
54 151
55 bpmp { 152 bpmp {
56 status = "okay"; 153 i2c {
154 status = "okay";
155
156 pmic: pmic@3c {
157 compatible = "maxim,max77620";
158 reg = <0x3c>;
159
160 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
161 #interrupt-cells = <2>;
162 interrupt-controller;
163
164 #gpio-cells = <2>;
165 gpio-controller;
166
167 pinctrl-names = "default";
168 pinctrl-0 = <&max77620_default>;
169
170 max77620_default: pinmux {
171 gpio0 {
172 pins = "gpio0";
173 function = "gpio";
174 };
175
176 gpio1 {
177 pins = "gpio1";
178 function = "fps-out";
179 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
180 };
181
182 gpio2 {
183 pins = "gpio2";
184 function = "fps-out";
185 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
186 };
187
188 gpio3 {
189 pins = "gpio3";
190 function = "fps-out";
191 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
192 };
193
194 gpio4 {
195 pins = "gpio4";
196 function = "32k-out1";
197 drive-push-pull = <1>;
198 };
199
200 gpio5 {
201 pins = "gpio5";
202 function = "gpio";
203 drive-push-pull = <0>;
204 };
205
206 gpio6 {
207 pins = "gpio6";
208 function = "gpio";
209 drive-push-pull = <1>;
210 };
211
212 gpio7 {
213 pins = "gpio7";
214 function = "gpio";
215 drive-push-pull = <0>;
216 };
217 };
218
219 fps {
220 fps0 {
221 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
222 maxim,shutdown-fps-time-period-us = <640>;
223 };
224
225 fps1 {
226 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
227 maxim,shutdown-fps-time-period-us = <640>;
228 };
229
230 fps2 {
231 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
232 maxim,shutdown-fps-time-period-us = <640>;
233 };
234 };
235
236 regulators {
237 in-sd0-supply = <&vdd_5v0_sys>;
238 in-sd1-supply = <&vdd_5v0_sys>;
239 in-sd2-supply = <&vdd_5v0_sys>;
240 in-sd3-supply = <&vdd_5v0_sys>;
241
242 in-ldo0-1-supply = <&vdd_5v0_sys>;
243 in-ldo2-supply = <&vdd_5v0_sys>;
244 in-ldo3-5-supply = <&vdd_5v0_sys>;
245 in-ldo4-6-supply = <&vdd_1v8>;
246 in-ldo7-8-supply = <&avdd_dsi_csi>;
247
248 sd0 {
249 regulator-name = "VDD_DDR_1V1_PMIC";
250 regulator-min-microvolt = <1100000>;
251 regulator-max-microvolt = <1100000>;
252 regulator-always-on;
253 regulator-boot-on;
254 };
255
256 avdd_dsi_csi: sd1 {
257 regulator-name = "AVDD_DSI_CSI_1V2";
258 regulator-min-microvolt = <1200000>;
259 regulator-max-microvolt = <1200000>;
260 /* XXX */
261 regulator-always-on;
262 regulator-boot-on;
263 };
264
265 vdd_1v8: sd2 {
266 regulator-name = "VDD_1V8";
267 regulator-min-microvolt = <1800000>;
268 regulator-max-microvolt = <1800000>;
269 /* XXX */
270 regulator-always-on;
271 regulator-boot-on;
272 };
273
274 vdd_3v3_sys: sd3 {
275 regulator-name = "VDD_3V3_SYS";
276 regulator-min-microvolt = <3300000>;
277 regulator-max-microvolt = <3300000>;
278 /* XXX */
279 regulator-always-on;
280 regulator-boot-on;
281 };
282
283 ldo0 {
284 regulator-name = "VDD_1V8_AP_PLL";
285 regulator-min-microvolt = <1800000>;
286 regulator-max-microvolt = <1800000>;
287 /* XXX */
288 regulator-always-on;
289 regulator-boot-on;
290 };
291
292 ldo2 {
293 regulator-name = "VDDIO_3V3_AOHV";
294 regulator-min-microvolt = <3300000>;
295 regulator-max-microvolt = <3300000>;
296 /* XXX */
297 regulator-always-on;
298 regulator-boot-on;
299 };
300
301 vddio_sdmmc1: ldo3 {
302 regulator-name = "VDDIO_SDMMC1_AP";
303 regulator-min-microvolt = <1800000>;
304 regulator-max-microvolt = <3300000>;
305 };
306
307 ldo4 {
308 regulator-name = "VDD_RTC";
309 regulator-min-microvolt = <1000000>;
310 regulator-max-microvolt = <1000000>;
311 };
312
313 vddio_sdmmc3: ldo5 {
314 regulator-name = "VDDIO_SDMMC3_AP";
315 regulator-min-microvolt = <2800000>;
316 regulator-max-microvolt = <2800000>;
317 };
318
319 avdd_1v05: ldo7 {
320 regulator-name = "VDD_HDMI_1V05";
321 regulator-min-microvolt = <1050000>;
322 regulator-max-microvolt = <1050000>;
323 /* XXX */
324 regulator-always-on;
325 regulator-boot-on;
326 };
327
328 vdd_pex: ldo8 {
329 regulator-name = "VDD_PEX_1V05";
330 regulator-min-microvolt = <1050000>;
331 regulator-max-microvolt = <1050000>;
332 /* XXX */
333 regulator-always-on;
334 regulator-boot-on;
335 };
336 };
337 };
338 };
57 }; 339 };
58 340
59 psci { 341 psci {
@@ -61,4 +343,39 @@
61 status = "okay"; 343 status = "okay";
62 method = "smc"; 344 method = "smc";
63 }; 345 };
346
347 regulators {
348 compatible = "simple-bus";
349 #address-cells = <1>;
350 #size-cells = <0>;
351
352 vdd_5v0_sys: regulator@0 {
353 compatible = "regulator-fixed";
354 reg = <0>;
355
356 regulator-name = "VDD_5V0_SYS";
357 regulator-min-microvolt = <5000000>;
358 regulator-max-microvolt = <5000000>;
359 regulator-always-on;
360 regulator-boot-on;
361 };
362
363 vdd_1v8_ap: regulator@1 {
364 compatible = "regulator-fixed";
365 reg = <1>;
366
367 regulator-name = "VDD_1V8_AP";
368 regulator-min-microvolt = <1800000>;
369 regulator-max-microvolt = <1800000>;
370
371 /* XXX */
372 regulator-always-on;
373 regulator-boot-on;
374
375 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
376 enable-active-high;
377
378 vin-supply = <&vdd_1v8>;
379 };
380 };
64}; 381};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 62fa85ae0271..5e62e68ac053 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -2,6 +2,7 @@
2#include <dt-bindings/gpio/tegra186-gpio.h> 2#include <dt-bindings/gpio/tegra186-gpio.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h>
4#include <dt-bindings/mailbox/tegra186-hsp.h> 4#include <dt-bindings/mailbox/tegra186-hsp.h>
5#include <dt-bindings/power/tegra186-powergate.h>
5#include <dt-bindings/reset/tegra186-reset.h> 6#include <dt-bindings/reset/tegra186-reset.h>
6 7
7/ { 8/ {
@@ -27,6 +28,37 @@
27 gpio-controller; 28 gpio-controller;
28 }; 29 };
29 30
31 ethernet@2490000 {
32 compatible = "nvidia,tegra186-eqos",
33 "snps,dwc-qos-ethernet-4.10";
34 reg = <0x0 0x02490000 0x0 0x10000>;
35 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
36 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
37 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
38 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
39 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
40 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
41 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
42 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
43 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
44 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
45 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
46 <&bpmp TEGRA186_CLK_EQOS_AXI>,
47 <&bpmp TEGRA186_CLK_EQOS_RX>,
48 <&bpmp TEGRA186_CLK_EQOS_TX>,
49 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
51 resets = <&bpmp TEGRA186_RESET_EQOS>;
52 reset-names = "eqos";
53 status = "disabled";
54
55 snps,write-requests = <1>;
56 snps,read-requests = <3>;
57 snps,burst-map = <0x7>;
58 snps,txpbl = <32>;
59 snps,rxpbl = <8>;
60 };
61
30 uarta: serial@3100000 { 62 uarta: serial@3100000 {
31 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 63 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
32 reg = <0x0 0x03100000 0x0 0x40>; 64 reg = <0x0 0x03100000 0x0 0x40>;
@@ -307,6 +339,33 @@
307 #interrupt-cells = <2>; 339 #interrupt-cells = <2>;
308 }; 340 };
309 341
342 pmc@c360000 {
343 compatible = "nvidia,tegra186-pmc";
344 reg = <0 0x0c360000 0 0x10000>,
345 <0 0x0c370000 0 0x10000>,
346 <0 0x0c380000 0 0x10000>,
347 <0 0x0c390000 0 0x10000>;
348 reg-names = "pmc", "wake", "aotag", "scratch";
349 };
350
351 gpu@17000000 {
352 compatible = "nvidia,gp10b";
353 reg = <0x0 0x17000000 0x0 0x1000000>,
354 <0x0 0x18000000 0x0 0x1000000>;
355 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
357 interrupt-names = "stall", "nonstall";
358
359 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
360 <&bpmp TEGRA186_CLK_GPU>;
361 clock-names = "gpu", "pwr";
362 resets = <&bpmp TEGRA186_RESET_GPU>;
363 reset-names = "gpu";
364 status = "disabled";
365
366 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
367 };
368
310 sysram@30000000 { 369 sysram@30000000 {
311 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 370 compatible = "nvidia,tegra186-sysram", "mmio-sram";
312 reg = <0x0 0x30000000 0x0 0x50000>; 371 reg = <0x0 0x30000000 0x0 0x50000>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 2f832df29da8..8f26c4d4409a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -89,6 +89,8 @@
89 89
90 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 90 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
91 91
92 iommus = <&mc TEGRA_SWGROUP_HC>;
93
92 dpaux1: dpaux@54040000 { 94 dpaux1: dpaux@54040000 {
93 compatible = "nvidia,tegra210-dpaux"; 95 compatible = "nvidia,tegra210-dpaux";
94 reg = <0x0 0x54040000 0x0 0x00040000>; 96 reg = <0x0 0x54040000 0x0 0x00040000>;
@@ -185,7 +187,14 @@
185 vic@54340000 { 187 vic@54340000 {
186 compatible = "nvidia,tegra210-vic"; 188 compatible = "nvidia,tegra210-vic";
187 reg = <0x0 0x54340000 0x0 0x00040000>; 189 reg = <0x0 0x54340000 0x0 0x00040000>;
188 status = "disabled"; 190 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
192 clock-names = "vic";
193 resets = <&tegra_car 178>;
194 reset-names = "vic";
195
196 iommus = <&mc TEGRA_SWGROUP_VIC>;
197 power-domains = <&pd_vic>;
189 }; 198 };
190 199
191 nvjpg@54380000 { 200 nvjpg@54380000 {
@@ -755,6 +764,14 @@
755 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 764 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
756 #power-domain-cells = <0>; 765 #power-domain-cells = <0>;
757 }; 766 };
767
768 pd_vic: vic {
769 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
770 clock-names = "vic";
771 resets = <&tegra_car 178>;
772 reset-names = "vic";
773 #power-domain-cells = <0>;
774 };
758 }; 775 };
759 }; 776 };
760 777
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 08:12:23 -0400