diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-07-27 13:03:08 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-07-27 13:03:08 -0400 |
commit | 3c9fdefe516f350469ac105943fb1bc22e3e8196 (patch) | |
tree | 08284f4236031329c7d339cc4333248d8b22fa3b | |
parent | 49b1622bdb0be9b1cb20d36c64a635bcc5981c4b (diff) | |
parent | 050d2a5533af362932553cb47fd5db9a3476074e (diff) |
Merge tag 'drm-fixes-2018-07-27' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Not much happening this week which is good: two imx display fixes and
one i915 quirk addition"
* tag 'drm-fixes-2018-07-27' of git://anongit.freedesktop.org/drm/drm:
drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.
gpu: ipu-csi: Check for field type alternate
drm/imx: imx-ldb: check if channel is enabled before printing warning
drm/imx: imx-ldb: disable LDB on driver bind
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 21 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/imx/imx-ldb.c | 9 | ||||
-rw-r--r-- | drivers/gpu/ipu-v3/ipu-csi.c | 3 |
6 files changed, 41 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 52f3b91d14fd..71e1aa54f774 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -652,6 +652,7 @@ enum intel_sbi_destination { | |||
652 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) | 652 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
653 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) | 653 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
654 | #define QUIRK_INCREASE_T12_DELAY (1<<6) | 654 | #define QUIRK_INCREASE_T12_DELAY (1<<6) |
655 | #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) | ||
655 | 656 | ||
656 | struct intel_fbdev; | 657 | struct intel_fbdev; |
657 | struct intel_fbc_work; | 658 | struct intel_fbc_work; |
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f4a8598a2d39..fed26d6e4e27 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c | |||
@@ -1782,15 +1782,24 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) | |||
1782 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | 1782 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
1783 | } | 1783 | } |
1784 | 1784 | ||
1785 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | 1785 | void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) |
1786 | enum transcoder cpu_transcoder) | ||
1787 | { | 1786 | { |
1787 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | ||
1788 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | ||
1789 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | ||
1788 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); | 1790 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
1789 | uint32_t val = I915_READ(reg); | 1791 | uint32_t val = I915_READ(reg); |
1790 | 1792 | ||
1791 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); | 1793 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
1792 | val |= TRANS_DDI_PORT_NONE; | 1794 | val |= TRANS_DDI_PORT_NONE; |
1793 | I915_WRITE(reg, val); | 1795 | I915_WRITE(reg, val); |
1796 | |||
1797 | if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && | ||
1798 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { | ||
1799 | DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n"); | ||
1800 | /* Quirk time at 100ms for reliable operation */ | ||
1801 | msleep(100); | ||
1802 | } | ||
1794 | } | 1803 | } |
1795 | 1804 | ||
1796 | int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, | 1805 | int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2cc6faa1daa8..dec0d60921bf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -5809,7 +5809,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, | |||
5809 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); | 5809 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
5810 | 5810 | ||
5811 | if (!transcoder_is_dsi(cpu_transcoder)) | 5811 | if (!transcoder_is_dsi(cpu_transcoder)) |
5812 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); | 5812 | intel_ddi_disable_transcoder_func(old_crtc_state); |
5813 | 5813 | ||
5814 | if (INTEL_GEN(dev_priv) >= 9) | 5814 | if (INTEL_GEN(dev_priv) >= 9) |
5815 | skylake_scaler_disable(intel_crtc); | 5815 | skylake_scaler_disable(intel_crtc); |
@@ -14646,6 +14646,18 @@ static void quirk_increase_t12_delay(struct drm_device *dev) | |||
14646 | DRM_INFO("Applying T12 delay quirk\n"); | 14646 | DRM_INFO("Applying T12 delay quirk\n"); |
14647 | } | 14647 | } |
14648 | 14648 | ||
14649 | /* | ||
14650 | * GeminiLake NUC HDMI outputs require additional off time | ||
14651 | * this allows the onboard retimer to correctly sync to signal | ||
14652 | */ | ||
14653 | static void quirk_increase_ddi_disabled_time(struct drm_device *dev) | ||
14654 | { | ||
14655 | struct drm_i915_private *dev_priv = to_i915(dev); | ||
14656 | |||
14657 | dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME; | ||
14658 | DRM_INFO("Applying Increase DDI Disabled quirk\n"); | ||
14659 | } | ||
14660 | |||
14649 | struct intel_quirk { | 14661 | struct intel_quirk { |
14650 | int device; | 14662 | int device; |
14651 | int subsystem_vendor; | 14663 | int subsystem_vendor; |
@@ -14732,6 +14744,13 @@ static struct intel_quirk intel_quirks[] = { | |||
14732 | 14744 | ||
14733 | /* Toshiba Satellite P50-C-18C */ | 14745 | /* Toshiba Satellite P50-C-18C */ |
14734 | { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay }, | 14746 | { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay }, |
14747 | |||
14748 | /* GeminiLake NUC */ | ||
14749 | { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time }, | ||
14750 | { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time }, | ||
14751 | /* ASRock ITX*/ | ||
14752 | { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time }, | ||
14753 | { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time }, | ||
14735 | }; | 14754 | }; |
14736 | 14755 | ||
14737 | static void intel_init_quirks(struct drm_device *dev) | 14756 | static void intel_init_quirks(struct drm_device *dev) |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 0361130500a6..b8eefbffc77d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
@@ -1388,8 +1388,7 @@ void hsw_fdi_link_train(struct intel_crtc *crtc, | |||
1388 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); | 1388 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); |
1389 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | 1389 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
1390 | void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); | 1390 | void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); |
1391 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | 1391 | void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); |
1392 | enum transcoder cpu_transcoder); | ||
1393 | void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state); | 1392 | void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state); |
1394 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); | 1393 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); |
1395 | struct intel_encoder * | 1394 | struct intel_encoder * |
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c index 56dd7a9a8e25..dd5312b02a8d 100644 --- a/drivers/gpu/drm/imx/imx-ldb.c +++ b/drivers/gpu/drm/imx/imx-ldb.c | |||
@@ -612,6 +612,9 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data) | |||
612 | return PTR_ERR(imx_ldb->regmap); | 612 | return PTR_ERR(imx_ldb->regmap); |
613 | } | 613 | } |
614 | 614 | ||
615 | /* disable LDB by resetting the control register to POR default */ | ||
616 | regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0); | ||
617 | |||
615 | imx_ldb->dev = dev; | 618 | imx_ldb->dev = dev; |
616 | 619 | ||
617 | if (of_id) | 620 | if (of_id) |
@@ -652,14 +655,14 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data) | |||
652 | if (ret || i < 0 || i > 1) | 655 | if (ret || i < 0 || i > 1) |
653 | return -EINVAL; | 656 | return -EINVAL; |
654 | 657 | ||
658 | if (!of_device_is_available(child)) | ||
659 | continue; | ||
660 | |||
655 | if (dual && i > 0) { | 661 | if (dual && i > 0) { |
656 | dev_warn(dev, "dual-channel mode, ignoring second output\n"); | 662 | dev_warn(dev, "dual-channel mode, ignoring second output\n"); |
657 | continue; | 663 | continue; |
658 | } | 664 | } |
659 | 665 | ||
660 | if (!of_device_is_available(child)) | ||
661 | continue; | ||
662 | |||
663 | channel = &imx_ldb->channel[i]; | 666 | channel = &imx_ldb->channel[i]; |
664 | channel->ldb = imx_ldb; | 667 | channel->ldb = imx_ldb; |
665 | channel->chno = i; | 668 | channel->chno = i; |
diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c index caa05b0702e1..5450a2db1219 100644 --- a/drivers/gpu/ipu-v3/ipu-csi.c +++ b/drivers/gpu/ipu-v3/ipu-csi.c | |||
@@ -339,7 +339,8 @@ static void fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg, | |||
339 | break; | 339 | break; |
340 | case V4L2_MBUS_BT656: | 340 | case V4L2_MBUS_BT656: |
341 | csicfg->ext_vsync = 0; | 341 | csicfg->ext_vsync = 0; |
342 | if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field)) | 342 | if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field) || |
343 | mbus_fmt->field == V4L2_FIELD_ALTERNATE) | ||
343 | csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED; | 344 | csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED; |
344 | else | 345 | else |
345 | csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE; | 346 | csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE; |