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authorMichael Turquette <mturquette@baylibre.com>2016-07-11 17:39:47 -0400
committerMichael Turquette <mturquette@baylibre.com>2016-07-11 17:39:47 -0400
commit3c67d1162aaf51b028784c249bf213f9b14df66b (patch)
treeb6b88f0a9571cef7c7aa85ae88c2153ffcadd078
parent7adb76956189d10fd77f00b41b4d413480e94715 (diff)
parentf38f51992347f80f982e50160596fd5388a43797 (diff)
Merge branch 'clk-sunxi-ng' into clk-next
Diffstat
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi312
-rw-r--r--drivers/clk/sunxi-ng/Kconfig2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.c4
3 files changed, 63 insertions, 255 deletions
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 4a4926b0b0ed..9871bad34742 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -42,8 +42,10 @@
42 42
43#include "skeleton.dtsi" 43#include "skeleton.dtsi"
44 44
45#include <dt-bindings/clock/sun8i-h3-ccu.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/pinctrl/sun4i-a10.h> 47#include <dt-bindings/pinctrl/sun4i-a10.h>
48#include <dt-bindings/reset/sun8i-h3-ccu.h>
47 49
48/ { 50/ {
49 interrupt-parent = <&gic>; 51 interrupt-parent = <&gic>;
@@ -104,191 +106,6 @@
104 clock-output-names = "osc32k"; 106 clock-output-names = "osc32k";
105 }; 107 };
106 108
107 pll1: clk@01c20000 {
108 #clock-cells = <0>;
109 compatible = "allwinner,sun8i-a23-pll1-clk";
110 reg = <0x01c20000 0x4>;
111 clocks = <&osc24M>;
112 clock-output-names = "pll1";
113 };
114
115 /* dummy clock until actually implemented */
116 pll5: pll5_clk {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 clock-frequency = <0>;
120 clock-output-names = "pll5";
121 };
122
123 pll6: clk@01c20028 {
124 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-pll6-clk";
126 reg = <0x01c20028 0x4>;
127 clocks = <&osc24M>;
128 clock-output-names = "pll6", "pll6x2";
129 };
130
131 pll6d2: pll6d2_clk {
132 #clock-cells = <0>;
133 compatible = "fixed-factor-clock";
134 clock-div = <2>;
135 clock-mult = <1>;
136 clocks = <&pll6 0>;
137 clock-output-names = "pll6d2";
138 };
139
140 /* dummy clock until pll6 can be reused */
141 pll8: pll8_clk {
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 clock-frequency = <1>;
145 clock-output-names = "pll8";
146 };
147
148 cpu: cpu_clk@01c20050 {
149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-a10-cpu-clk";
151 reg = <0x01c20050 0x4>;
152 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
153 clock-output-names = "cpu";
154 };
155
156 axi: axi_clk@01c20050 {
157 #clock-cells = <0>;
158 compatible = "allwinner,sun4i-a10-axi-clk";
159 reg = <0x01c20050 0x4>;
160 clocks = <&cpu>;
161 clock-output-names = "axi";
162 };
163
164 ahb1: ahb1_clk@01c20054 {
165 #clock-cells = <0>;
166 compatible = "allwinner,sun6i-a31-ahb1-clk";
167 reg = <0x01c20054 0x4>;
168 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
169 clock-output-names = "ahb1";
170 };
171
172 ahb2: ahb2_clk@01c2005c {
173 #clock-cells = <0>;
174 compatible = "allwinner,sun8i-h3-ahb2-clk";
175 reg = <0x01c2005c 0x4>;
176 clocks = <&ahb1>, <&pll6d2>;
177 clock-output-names = "ahb2";
178 };
179
180 apb1: apb1_clk@01c20054 {
181 #clock-cells = <0>;
182 compatible = "allwinner,sun4i-a10-apb0-clk";
183 reg = <0x01c20054 0x4>;
184 clocks = <&ahb1>;
185 clock-output-names = "apb1";
186 };
187
188 apb2: apb2_clk@01c20058 {
189 #clock-cells = <0>;
190 compatible = "allwinner,sun4i-a10-apb1-clk";
191 reg = <0x01c20058 0x4>;
192 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
193 clock-output-names = "apb2";
194 };
195
196 bus_gates: clk@01c20060 {
197 #clock-cells = <1>;
198 compatible = "allwinner,sun8i-h3-bus-gates-clk";
199 reg = <0x01c20060 0x14>;
200 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
201 clock-names = "ahb1", "ahb2", "apb1", "apb2";
202 clock-indices = <5>, <6>, <8>,
203 <9>, <10>, <13>,
204 <14>, <17>, <18>,
205 <19>, <20>,
206 <21>, <23>,
207 <24>, <25>,
208 <26>, <27>,
209 <28>, <29>,
210 <30>, <31>, <32>,
211 <35>, <36>, <37>,
212 <40>, <41>, <43>,
213 <44>, <52>, <53>,
214 <54>, <64>,
215 <65>, <69>, <72>,
216 <76>, <77>, <78>,
217 <96>, <97>, <98>,
218 <112>, <113>,
219 <114>, <115>,
220 <116>, <128>, <135>;
221 clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
222 "bus_mmc1", "bus_mmc2", "bus_nand",
223 "bus_sdram", "bus_gmac", "bus_ts",
224 "bus_hstimer", "bus_spi0",
225 "bus_spi1", "bus_otg",
226 "bus_otg_ehci0", "bus_ehci1",
227 "bus_ehci2", "bus_ehci3",
228 "bus_otg_ohci0", "bus_ohci1",
229 "bus_ohci2", "bus_ohci3", "bus_ve",
230 "bus_lcd0", "bus_lcd1", "bus_deint",
231 "bus_csi", "bus_tve", "bus_hdmi",
232 "bus_de", "bus_gpu", "bus_msgbox",
233 "bus_spinlock", "bus_codec",
234 "bus_spdif", "bus_pio", "bus_ths",
235 "bus_i2s0", "bus_i2s1", "bus_i2s2",
236 "bus_i2c0", "bus_i2c1", "bus_i2c2",
237 "bus_uart0", "bus_uart1",
238 "bus_uart2", "bus_uart3",
239 "bus_scr", "bus_ephy", "bus_dbg";
240 };
241
242 mmc0_clk: clk@01c20088 {
243 #clock-cells = <1>;
244 compatible = "allwinner,sun4i-a10-mmc-clk";
245 reg = <0x01c20088 0x4>;
246 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
247 clock-output-names = "mmc0",
248 "mmc0_output",
249 "mmc0_sample";
250 };
251
252 mmc1_clk: clk@01c2008c {
253 #clock-cells = <1>;
254 compatible = "allwinner,sun4i-a10-mmc-clk";
255 reg = <0x01c2008c 0x4>;
256 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
257 clock-output-names = "mmc1",
258 "mmc1_output",
259 "mmc1_sample";
260 };
261
262 mmc2_clk: clk@01c20090 {
263 #clock-cells = <1>;
264 compatible = "allwinner,sun4i-a10-mmc-clk";
265 reg = <0x01c20090 0x4>;
266 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
267 clock-output-names = "mmc2",
268 "mmc2_output",
269 "mmc2_sample";
270 };
271
272 usb_clk: clk@01c200cc {
273 #clock-cells = <1>;
274 #reset-cells = <1>;
275 compatible = "allwinner,sun8i-h3-usb-clk";
276 reg = <0x01c200cc 0x4>;
277 clocks = <&osc24M>;
278 clock-output-names = "usb_phy0", "usb_phy1",
279 "usb_phy2", "usb_phy3",
280 "usb_ohci0", "usb_ohci1",
281 "usb_ohci2", "usb_ohci3";
282 };
283
284 mbus_clk: clk@01c2015c {
285 #clock-cells = <0>;
286 compatible = "allwinner,sun8i-a23-mbus-clk";
287 reg = <0x01c2015c 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
289 clock-output-names = "mbus";
290 };
291
292 apb0: apb0_clk { 109 apb0: apb0_clk {
293 compatible = "fixed-factor-clock"; 110 compatible = "fixed-factor-clock";
294 #clock-cells = <0>; 111 #clock-cells = <0>;
@@ -327,23 +144,23 @@
327 compatible = "allwinner,sun8i-h3-dma"; 144 compatible = "allwinner,sun8i-h3-dma";
328 reg = <0x01c02000 0x1000>; 145 reg = <0x01c02000 0x1000>;
329 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 146 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&bus_gates 6>; 147 clocks = <&ccu CLK_BUS_DMA>;
331 resets = <&ahb_rst 6>; 148 resets = <&ccu RST_BUS_DMA>;
332 #dma-cells = <1>; 149 #dma-cells = <1>;
333 }; 150 };
334 151
335 mmc0: mmc@01c0f000 { 152 mmc0: mmc@01c0f000 {
336 compatible = "allwinner,sun5i-a13-mmc"; 153 compatible = "allwinner,sun5i-a13-mmc";
337 reg = <0x01c0f000 0x1000>; 154 reg = <0x01c0f000 0x1000>;
338 clocks = <&bus_gates 8>, 155 clocks = <&ccu CLK_BUS_MMC0>,
339 <&mmc0_clk 0>, 156 <&ccu CLK_MMC0>,
340 <&mmc0_clk 1>, 157 <&ccu CLK_MMC0_OUTPUT>,
341 <&mmc0_clk 2>; 158 <&ccu CLK_MMC0_SAMPLE>;
342 clock-names = "ahb", 159 clock-names = "ahb",
343 "mmc", 160 "mmc",
344 "output", 161 "output",
345 "sample"; 162 "sample";
346 resets = <&ahb_rst 8>; 163 resets = <&ccu RST_BUS_MMC0>;
347 reset-names = "ahb"; 164 reset-names = "ahb";
348 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 165 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
349 status = "disabled"; 166 status = "disabled";
@@ -354,15 +171,15 @@
354 mmc1: mmc@01c10000 { 171 mmc1: mmc@01c10000 {
355 compatible = "allwinner,sun5i-a13-mmc"; 172 compatible = "allwinner,sun5i-a13-mmc";
356 reg = <0x01c10000 0x1000>; 173 reg = <0x01c10000 0x1000>;
357 clocks = <&bus_gates 9>, 174 clocks = <&ccu CLK_BUS_MMC1>,
358 <&mmc1_clk 0>, 175 <&ccu CLK_MMC1>,
359 <&mmc1_clk 1>, 176 <&ccu CLK_MMC1_OUTPUT>,
360 <&mmc1_clk 2>; 177 <&ccu CLK_MMC1_SAMPLE>;
361 clock-names = "ahb", 178 clock-names = "ahb",
362 "mmc", 179 "mmc",
363 "output", 180 "output",
364 "sample"; 181 "sample";
365 resets = <&ahb_rst 9>; 182 resets = <&ccu RST_BUS_MMC1>;
366 reset-names = "ahb"; 183 reset-names = "ahb";
367 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 184 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
368 status = "disabled"; 185 status = "disabled";
@@ -373,15 +190,15 @@
373 mmc2: mmc@01c11000 { 190 mmc2: mmc@01c11000 {
374 compatible = "allwinner,sun5i-a13-mmc"; 191 compatible = "allwinner,sun5i-a13-mmc";
375 reg = <0x01c11000 0x1000>; 192 reg = <0x01c11000 0x1000>;
376 clocks = <&bus_gates 10>, 193 clocks = <&ccu CLK_BUS_MMC2>,
377 <&mmc2_clk 0>, 194 <&ccu CLK_MMC2>,
378 <&mmc2_clk 1>, 195 <&ccu CLK_MMC2_OUTPUT>,
379 <&mmc2_clk 2>; 196 <&ccu CLK_MMC2_SAMPLE>;
380 clock-names = "ahb", 197 clock-names = "ahb",
381 "mmc", 198 "mmc",
382 "output", 199 "output",
383 "sample"; 200 "sample";
384 resets = <&ahb_rst 10>; 201 resets = <&ccu RST_BUS_MMC2>;
385 reset-names = "ahb"; 202 reset-names = "ahb";
386 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 203 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
387 status = "disabled"; 204 status = "disabled";
@@ -401,18 +218,18 @@
401 "pmu1", 218 "pmu1",
402 "pmu2", 219 "pmu2",
403 "pmu3"; 220 "pmu3";
404 clocks = <&usb_clk 8>, 221 clocks = <&ccu CLK_USB_PHY0>,
405 <&usb_clk 9>, 222 <&ccu CLK_USB_PHY1>,
406 <&usb_clk 10>, 223 <&ccu CLK_USB_PHY2>,
407 <&usb_clk 11>; 224 <&ccu CLK_USB_PHY3>;
408 clock-names = "usb0_phy", 225 clock-names = "usb0_phy",
409 "usb1_phy", 226 "usb1_phy",
410 "usb2_phy", 227 "usb2_phy",
411 "usb3_phy"; 228 "usb3_phy";
412 resets = <&usb_clk 0>, 229 resets = <&ccu RST_USB_PHY0>,
413 <&usb_clk 1>, 230 <&ccu RST_USB_PHY1>,
414 <&usb_clk 2>, 231 <&ccu RST_USB_PHY2>,
415 <&usb_clk 3>; 232 <&ccu RST_USB_PHY3>;
416 reset-names = "usb0_reset", 233 reset-names = "usb0_reset",
417 "usb1_reset", 234 "usb1_reset",
418 "usb2_reset", 235 "usb2_reset",
@@ -425,8 +242,8 @@
425 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 242 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
426 reg = <0x01c1b000 0x100>; 243 reg = <0x01c1b000 0x100>;
427 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 244 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&bus_gates 25>, <&bus_gates 29>; 245 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
429 resets = <&ahb_rst 25>, <&ahb_rst 29>; 246 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
430 phys = <&usbphy 1>; 247 phys = <&usbphy 1>;
431 phy-names = "usb"; 248 phy-names = "usb";
432 status = "disabled"; 249 status = "disabled";
@@ -436,9 +253,9 @@
436 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 253 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
437 reg = <0x01c1b400 0x100>; 254 reg = <0x01c1b400 0x100>;
438 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 255 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&bus_gates 29>, <&bus_gates 25>, 256 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
440 <&usb_clk 17>; 257 <&ccu CLK_USB_OHCI1>;
441 resets = <&ahb_rst 29>, <&ahb_rst 25>; 258 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
442 phys = <&usbphy 1>; 259 phys = <&usbphy 1>;
443 phy-names = "usb"; 260 phy-names = "usb";
444 status = "disabled"; 261 status = "disabled";
@@ -448,8 +265,8 @@
448 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 265 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
449 reg = <0x01c1c000 0x100>; 266 reg = <0x01c1c000 0x100>;
450 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 267 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&bus_gates 26>, <&bus_gates 30>; 268 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
452 resets = <&ahb_rst 26>, <&ahb_rst 30>; 269 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
453 phys = <&usbphy 2>; 270 phys = <&usbphy 2>;
454 phy-names = "usb"; 271 phy-names = "usb";
455 status = "disabled"; 272 status = "disabled";
@@ -459,9 +276,9 @@
459 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 276 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
460 reg = <0x01c1c400 0x100>; 277 reg = <0x01c1c400 0x100>;
461 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 278 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&bus_gates 30>, <&bus_gates 26>, 279 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
463 <&usb_clk 18>; 280 <&ccu CLK_USB_OHCI2>;
464 resets = <&ahb_rst 30>, <&ahb_rst 26>; 281 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
465 phys = <&usbphy 2>; 282 phys = <&usbphy 2>;
466 phy-names = "usb"; 283 phy-names = "usb";
467 status = "disabled"; 284 status = "disabled";
@@ -471,8 +288,8 @@
471 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 288 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
472 reg = <0x01c1d000 0x100>; 289 reg = <0x01c1d000 0x100>;
473 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 290 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&bus_gates 27>, <&bus_gates 31>; 291 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
475 resets = <&ahb_rst 27>, <&ahb_rst 31>; 292 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
476 phys = <&usbphy 3>; 293 phys = <&usbphy 3>;
477 phy-names = "usb"; 294 phy-names = "usb";
478 status = "disabled"; 295 status = "disabled";
@@ -482,20 +299,29 @@
482 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 299 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
483 reg = <0x01c1d400 0x100>; 300 reg = <0x01c1d400 0x100>;
484 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 301 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&bus_gates 31>, <&bus_gates 27>, 302 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
486 <&usb_clk 19>; 303 <&ccu CLK_USB_OHCI3>;
487 resets = <&ahb_rst 31>, <&ahb_rst 27>; 304 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
488 phys = <&usbphy 3>; 305 phys = <&usbphy 3>;
489 phy-names = "usb"; 306 phy-names = "usb";
490 status = "disabled"; 307 status = "disabled";
491 }; 308 };
492 309
310 ccu: clock@01c20000 {
311 compatible = "allwinner,sun8i-h3-ccu";
312 reg = <0x01c20000 0x400>;
313 clocks = <&osc24M>, <&osc32k>;
314 clock-names = "hosc", "losc";
315 #clock-cells = <1>;
316 #reset-cells = <1>;
317 };
318
493 pio: pinctrl@01c20800 { 319 pio: pinctrl@01c20800 {
494 compatible = "allwinner,sun8i-h3-pinctrl"; 320 compatible = "allwinner,sun8i-h3-pinctrl";
495 reg = <0x01c20800 0x400>; 321 reg = <0x01c20800 0x400>;
496 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 323 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&bus_gates 69>; 324 clocks = <&ccu CLK_BUS_PIO>;
499 gpio-controller; 325 gpio-controller;
500 #gpio-cells = <3>; 326 #gpio-cells = <3>;
501 interrupt-controller; 327 interrupt-controller;
@@ -542,24 +368,6 @@
542 }; 368 };
543 }; 369 };
544 370
545 ahb_rst: reset@01c202c0 {
546 #reset-cells = <1>;
547 compatible = "allwinner,sun6i-a31-ahb1-reset";
548 reg = <0x01c202c0 0xc>;
549 };
550
551 apb1_rst: reset@01c202d0 {
552 #reset-cells = <1>;
553 compatible = "allwinner,sun6i-a31-clock-reset";
554 reg = <0x01c202d0 0x4>;
555 };
556
557 apb2_rst: reset@01c202d8 {
558 #reset-cells = <1>;
559 compatible = "allwinner,sun6i-a31-clock-reset";
560 reg = <0x01c202d8 0x4>;
561 };
562
563 timer@01c20c00 { 371 timer@01c20c00 {
564 compatible = "allwinner,sun4i-a10-timer"; 372 compatible = "allwinner,sun4i-a10-timer";
565 reg = <0x01c20c00 0xa0>; 373 reg = <0x01c20c00 0xa0>;
@@ -580,8 +388,8 @@
580 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 388 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
581 reg-shift = <2>; 389 reg-shift = <2>;
582 reg-io-width = <4>; 390 reg-io-width = <4>;
583 clocks = <&bus_gates 112>; 391 clocks = <&ccu CLK_BUS_UART0>;
584 resets = <&apb2_rst 16>; 392 resets = <&ccu RST_BUS_UART0>;
585 dmas = <&dma 6>, <&dma 6>; 393 dmas = <&dma 6>, <&dma 6>;
586 dma-names = "rx", "tx"; 394 dma-names = "rx", "tx";
587 status = "disabled"; 395 status = "disabled";
@@ -593,8 +401,8 @@
593 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 401 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
594 reg-shift = <2>; 402 reg-shift = <2>;
595 reg-io-width = <4>; 403 reg-io-width = <4>;
596 clocks = <&bus_gates 113>; 404 clocks = <&ccu CLK_BUS_UART1>;
597 resets = <&apb2_rst 17>; 405 resets = <&ccu RST_BUS_UART1>;
598 dmas = <&dma 7>, <&dma 7>; 406 dmas = <&dma 7>, <&dma 7>;
599 dma-names = "rx", "tx"; 407 dma-names = "rx", "tx";
600 status = "disabled"; 408 status = "disabled";
@@ -606,8 +414,8 @@
606 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 414 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
607 reg-shift = <2>; 415 reg-shift = <2>;
608 reg-io-width = <4>; 416 reg-io-width = <4>;
609 clocks = <&bus_gates 114>; 417 clocks = <&ccu CLK_BUS_UART2>;
610 resets = <&apb2_rst 18>; 418 resets = <&ccu RST_BUS_UART2>;
611 dmas = <&dma 8>, <&dma 8>; 419 dmas = <&dma 8>, <&dma 8>;
612 dma-names = "rx", "tx"; 420 dma-names = "rx", "tx";
613 status = "disabled"; 421 status = "disabled";
@@ -619,8 +427,8 @@
619 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 427 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
620 reg-shift = <2>; 428 reg-shift = <2>;
621 reg-io-width = <4>; 429 reg-io-width = <4>;
622 clocks = <&bus_gates 115>; 430 clocks = <&ccu CLK_BUS_UART3>;
623 resets = <&apb2_rst 19>; 431 resets = <&ccu RST_BUS_UART3>;
624 dmas = <&dma 9>, <&dma 9>; 432 dmas = <&dma 9>, <&dma 9>;
625 dma-names = "rx", "tx"; 433 dma-names = "rx", "tx";
626 status = "disabled"; 434 status = "disabled";
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 41e53e8d4d41..2afcbd39e41e 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -60,6 +60,6 @@ config SUN8I_H3_CCU
60 select SUNXI_CCU_NM 60 select SUNXI_CCU_NM
61 select SUNXI_CCU_MP 61 select SUNXI_CCU_MP
62 select SUNXI_CCU_PHASE 62 select SUNXI_CCU_PHASE
63 default ARCH_SUN8I 63 default MACH_SUN8I
64 64
65endif 65endif
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index bcc0a95549d3..9af359544110 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -817,8 +817,8 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
817 817
818 /* Force the PLL-Audio-1x divider to 4 */ 818 /* Force the PLL-Audio-1x divider to 4 */
819 val = readl(reg + SUN8I_H3_PLL_AUDIO_REG); 819 val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
820 val &= ~GENMASK(4, 0); 820 val &= ~GENMASK(19, 16);
821 writel(val | 3, reg + SUN8I_H3_PLL_AUDIO_REG); 821 writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
822 822
823 sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc); 823 sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
824} 824}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 01:27:03 -0400