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authorDinh Nguyen <dinguyen@kernel.org>2017-05-09 10:21:08 -0400
committerDinh Nguyen <dinguyen@kernel.org>2017-06-23 10:29:13 -0400
commit3c56909ec2672d74d30f32f1c0ed8cfd7d6e2b14 (patch)
tree6e5224858597a4b493e2f41bc130f3cc8be27a30
parent5b5ada57e4df56940d4855069754460b31666806 (diff)
ARM: dts: socfpga: set the i2c frequency
Use 'clock-frequency' binding for the i2c node that will put the I2C driver into the standard operating mode. 'speed-mode' was not a valid binding for the I2C driver, remove it. Signed-off-by: Alan Tull <atull@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
-rw-r--r--arch/arm/boot/dts/socfpga_arria10_socdk.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts2
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 94e088473823..3a32de9ded3b 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -130,13 +130,13 @@
130}; 130};
131 131
132&i2c1 { 132&i2c1 {
133 speed-mode = <0>;
134 status = "okay"; 133 status = "okay";
135 134
136 /* 135 /*
137 * adjust the falling times to decrease the i2c frequency to 50Khz 136 * adjust the falling times to decrease the i2c frequency to 50Khz
138 * because the LCD module does not work at the standard 100Khz 137 * because the LCD module does not work at the standard 100Khz
139 */ 138 */
139 clock-frequency = <100000>;
140 i2c-sda-falling-time-ns = <6000>; 140 i2c-sda-falling-time-ns = <6000>;
141 i2c-scl-falling-time-ns = <6000>; 141 i2c-scl-falling-time-ns = <6000>;
142 142
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
index 7b49395452b6..b280e6494193 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
@@ -86,7 +86,7 @@
86 86
87&i2c0 { 87&i2c0 {
88 status = "okay"; 88 status = "okay";
89 speed-mode = <0>; 89 clock-frequency = <100000>;
90 90
91 adxl345: adxl345@0 { 91 adxl345: adxl345@0 {
92 compatible = "adi,adxl345"; 92 compatible = "adi,adxl345";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
index 21e397287e29..c2eb88aab8b3 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
@@ -58,7 +58,7 @@
58 58
59&i2c0 { 59&i2c0 {
60 status = "okay"; 60 status = "okay";
61 speed-mode = <0>; 61 clock-frequency = <100000>;
62 62
63 stmpe1: stmpe811@41 { 63 stmpe1: stmpe811@41 {
64 compatible = "st,stmpe811"; 64 compatible = "st,stmpe811";