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authorTej Parkash <tej.parkash@qlogic.com>2014-02-24 22:07:00 -0500
committerChristoph Hellwig <hch@lst.de>2014-05-19 13:12:14 -0400
commit3c3cab172700bbd03fc24deb7eb56e656c271f5b (patch)
tree631673669e742f372f5fb0754785f8799e7decef
parentb18297894584ec9ae0fdfe55c9cc18f424435799 (diff)
qla4xxx: Added PEX DMA Support for ISP8022 Adapter
Signed-off-by: Tej Parkash <tej.parkash@qlogic.com> Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com> Reviewed-by: Mike Christie <michaelc@cs.wisc.edu> Signed-off-by: Christoph Hellwig <hch@lst.de>
Diffstat
-rw-r--r--drivers/scsi/qla4xxx/ql4_83xx.c44
-rw-r--r--drivers/scsi/qla4xxx/ql4_glbl.h2
-rw-r--r--drivers/scsi/qla4xxx/ql4_nx.c15
3 files changed, 28 insertions, 33 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_83xx.c b/drivers/scsi/qla4xxx/ql4_83xx.c
index 2eba35365920..ffce0163cb5d 100644
--- a/drivers/scsi/qla4xxx/ql4_83xx.c
+++ b/drivers/scsi/qla4xxx/ql4_83xx.c
@@ -250,7 +250,7 @@ void qla4_83xx_rom_lock_recovery(struct scsi_qla_host *ha)
250} 250}
251 251
252/** 252/**
253 * qla4_83xx_ms_mem_write_128b - Writes data to MS/off-chip memory 253 * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory
254 * @ha: Pointer to adapter structure 254 * @ha: Pointer to adapter structure
255 * @addr: Flash address to write to 255 * @addr: Flash address to write to
256 * @data: Data to be written 256 * @data: Data to be written
@@ -259,7 +259,7 @@ void qla4_83xx_rom_lock_recovery(struct scsi_qla_host *ha)
259 * Return: On success return QLA_SUCCESS 259 * Return: On success return QLA_SUCCESS
260 * On error return QLA_ERROR 260 * On error return QLA_ERROR
261 **/ 261 **/
262int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr, 262int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
263 uint32_t *data, uint32_t count) 263 uint32_t *data, uint32_t count)
264{ 264{
265 int i, j; 265 int i, j;
@@ -276,7 +276,7 @@ int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
276 write_lock_irqsave(&ha->hw_lock, flags); 276 write_lock_irqsave(&ha->hw_lock, flags);
277 277
278 /* Write address */ 278 /* Write address */
279 ret_val = qla4_83xx_wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0); 279 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
280 if (ret_val == QLA_ERROR) { 280 if (ret_val == QLA_ERROR) {
281 ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n", 281 ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
282 __func__); 282 __func__);
@@ -292,19 +292,20 @@ int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
292 goto exit_ms_mem_write_unlock; 292 goto exit_ms_mem_write_unlock;
293 } 293 }
294 294
295 ret_val = qla4_83xx_wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO, 295 ret_val = ha->isp_ops->wr_reg_indirect(ha,
296 addr); 296 MD_MIU_TEST_AGT_ADDR_LO,
297 addr);
297 /* Write data */ 298 /* Write data */
298 ret_val |= qla4_83xx_wr_reg_indirect(ha, 299 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
299 MD_MIU_TEST_AGT_WRDATA_LO, 300 MD_MIU_TEST_AGT_WRDATA_LO,
300 *data++); 301 *data++);
301 ret_val |= qla4_83xx_wr_reg_indirect(ha, 302 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
302 MD_MIU_TEST_AGT_WRDATA_HI, 303 MD_MIU_TEST_AGT_WRDATA_HI,
303 *data++); 304 *data++);
304 ret_val |= qla4_83xx_wr_reg_indirect(ha, 305 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
305 MD_MIU_TEST_AGT_WRDATA_ULO, 306 MD_MIU_TEST_AGT_WRDATA_ULO,
306 *data++); 307 *data++);
307 ret_val |= qla4_83xx_wr_reg_indirect(ha, 308 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
308 MD_MIU_TEST_AGT_WRDATA_UHI, 309 MD_MIU_TEST_AGT_WRDATA_UHI,
309 *data++); 310 *data++);
310 if (ret_val == QLA_ERROR) { 311 if (ret_val == QLA_ERROR) {
@@ -314,10 +315,11 @@ int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
314 } 315 }
315 316
316 /* Check write status */ 317 /* Check write status */
317 ret_val = qla4_83xx_wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, 318 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
318 MIU_TA_CTL_WRITE_ENABLE); 319 MIU_TA_CTL_WRITE_ENABLE);
319 ret_val |= qla4_83xx_wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, 320 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
320 MIU_TA_CTL_WRITE_START); 321 MD_MIU_TEST_AGT_CTRL,
322 MIU_TA_CTL_WRITE_START);
321 if (ret_val == QLA_ERROR) { 323 if (ret_val == QLA_ERROR) {
322 ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n", 324 ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
323 __func__); 325 __func__);
@@ -325,9 +327,9 @@ int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
325 } 327 }
326 328
327 for (j = 0; j < MAX_CTL_CHECK; j++) { 329 for (j = 0; j < MAX_CTL_CHECK; j++) {
328 ret_val = qla4_83xx_rd_reg_indirect(ha, 330 ret_val = ha->isp_ops->rd_reg_indirect(ha,
329 MD_MIU_TEST_AGT_CTRL, 331 MD_MIU_TEST_AGT_CTRL,
330 &agt_ctrl); 332 &agt_ctrl);
331 if (ret_val == QLA_ERROR) { 333 if (ret_val == QLA_ERROR) {
332 ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n", 334 ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
333 __func__); 335 __func__);
@@ -760,7 +762,7 @@ static int qla4_83xx_copy_bootloader(struct scsi_qla_host *ha)
760 __func__)); 762 __func__));
761 763
762 /* 128 bit/16 byte write to MS memory */ 764 /* 128 bit/16 byte write to MS memory */
763 ret_val = qla4_83xx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache, 765 ret_val = qla4_8xxx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache,
764 count); 766 count);
765 if (ret_val == QLA_ERROR) { 767 if (ret_val == QLA_ERROR) {
766 ql4_printk(KERN_ERR, ha, "%s: Error writing firmware to MS\n", 768 ql4_printk(KERN_ERR, ha, "%s: Error writing firmware to MS\n",
diff --git a/drivers/scsi/qla4xxx/ql4_glbl.h b/drivers/scsi/qla4xxx/ql4_glbl.h
index b1a19cd8d5b2..20354754faa2 100644
--- a/drivers/scsi/qla4xxx/ql4_glbl.h
+++ b/drivers/scsi/qla4xxx/ql4_glbl.h
@@ -274,7 +274,7 @@ int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
274int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma, 274int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
275 uint32_t acb_type, uint32_t len); 275 uint32_t acb_type, uint32_t len);
276int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config); 276int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config);
277int qla4_83xx_ms_mem_write_128b(struct scsi_qla_host *ha, 277int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha,
278 uint64_t addr, uint32_t *data, uint32_t count); 278 uint64_t addr, uint32_t *data, uint32_t count);
279uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state); 279uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state);
280int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config); 280int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config);
diff --git a/drivers/scsi/qla4xxx/ql4_nx.c b/drivers/scsi/qla4xxx/ql4_nx.c
index bdc3b9563688..6032bf601e6e 100644
--- a/drivers/scsi/qla4xxx/ql4_nx.c
+++ b/drivers/scsi/qla4xxx/ql4_nx.c
@@ -1918,7 +1918,7 @@ error_exit:
1918 return rval; 1918 return rval;
1919} 1919}
1920 1920
1921static int qla4_83xx_minidump_pex_dma_read(struct scsi_qla_host *ha, 1921static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha,
1922 struct qla8xxx_minidump_entry_hdr *entry_hdr, 1922 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1923 uint32_t **d_ptr) 1923 uint32_t **d_ptr)
1924{ 1924{
@@ -1995,7 +1995,7 @@ static int qla4_83xx_minidump_pex_dma_read(struct scsi_qla_host *ha,
1995 dma_desc.cmd.read_data_size = size; 1995 dma_desc.cmd.read_data_size = size;
1996 1996
1997 /* Prepare: Write pex-dma descriptor to MS memory. */ 1997 /* Prepare: Write pex-dma descriptor to MS memory. */
1998 rval = qla4_83xx_ms_mem_write_128b(ha, 1998 rval = qla4_8xxx_ms_mem_write_128b(ha,
1999 (uint64_t)m_hdr->desc_card_addr, 1999 (uint64_t)m_hdr->desc_card_addr,
2000 (uint32_t *)&dma_desc, 2000 (uint32_t *)&dma_desc,
2001 (sizeof(struct qla4_83xx_pex_dma_descriptor)/16)); 2001 (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
@@ -2455,17 +2455,10 @@ static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2455 uint32_t *data_ptr = *d_ptr; 2455 uint32_t *data_ptr = *d_ptr;
2456 int rval = QLA_SUCCESS; 2456 int rval = QLA_SUCCESS;
2457 2457
2458 if (is_qla8032(ha) || is_qla8042(ha)) { 2458 rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr);
2459 rval = qla4_83xx_minidump_pex_dma_read(ha, entry_hdr, 2459 if (rval != QLA_SUCCESS)
2460 &data_ptr);
2461 if (rval != QLA_SUCCESS) {
2462 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2463 &data_ptr);
2464 }
2465 } else {
2466 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 2460 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2467 &data_ptr); 2461 &data_ptr);
2468 }
2469 *d_ptr = data_ptr; 2462 *d_ptr = data_ptr;
2470 return rval; 2463 return rval;
2471} 2464}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-28 11:50:05 -0400