diff options
author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2016-09-22 07:06:56 -0400 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-11-02 04:48:18 -0400 |
commit | 3b592939b7c02db19a50545834d2eeaa7eff6df6 (patch) | |
tree | 14672d1a7e1acd64b5bfcc32f2c088c28d8d435d | |
parent | 530582998acef0a6f9aafed7c82a2bb11b4405f6 (diff) |
drm/omap: dispc: Simplify _dispc_mgr_set_lcd_timings() parameters
Instead of passing the omap_video_timings structure's members individually,
use the pointer to the struct.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dispc.c | 38 |
1 files changed, 14 insertions, 24 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index f11bfe5378d1..6a0c13d97cc1 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c | |||
@@ -3141,29 +3141,23 @@ bool dispc_mgr_timings_ok(enum omap_channel channel, | |||
3141 | return true; | 3141 | return true; |
3142 | } | 3142 | } |
3143 | 3143 | ||
3144 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, | 3144 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, |
3145 | int hfp, int hbp, int vsw, int vfp, int vbp, | 3145 | const struct omap_video_timings *ovt) |
3146 | enum omap_dss_signal_level vsync_level, | ||
3147 | enum omap_dss_signal_level hsync_level, | ||
3148 | enum omap_dss_signal_edge data_pclk_edge, | ||
3149 | enum omap_dss_signal_level de_level, | ||
3150 | enum omap_dss_signal_edge sync_pclk_edge) | ||
3151 | |||
3152 | { | 3146 | { |
3153 | u32 timing_h, timing_v, l; | 3147 | u32 timing_h, timing_v, l; |
3154 | bool onoff, rf, ipc, vs, hs, de; | 3148 | bool onoff, rf, ipc, vs, hs, de; |
3155 | 3149 | ||
3156 | timing_h = FLD_VAL(hsync_len-1, dispc.feat->sw_start, 0) | | 3150 | timing_h = FLD_VAL(ovt->hsync_len - 1, dispc.feat->sw_start, 0) | |
3157 | FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | | 3151 | FLD_VAL(ovt->hfront_porch - 1, dispc.feat->fp_start, 8) | |
3158 | FLD_VAL(hbp-1, dispc.feat->bp_start, 20); | 3152 | FLD_VAL(ovt->hback_porch - 1, dispc.feat->bp_start, 20); |
3159 | timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | | 3153 | timing_v = FLD_VAL(ovt->vsync_len - 1, dispc.feat->sw_start, 0) | |
3160 | FLD_VAL(vfp, dispc.feat->fp_start, 8) | | 3154 | FLD_VAL(ovt->vfront_porch, dispc.feat->fp_start, 8) | |
3161 | FLD_VAL(vbp, dispc.feat->bp_start, 20); | 3155 | FLD_VAL(ovt->vback_porch, dispc.feat->bp_start, 20); |
3162 | 3156 | ||
3163 | dispc_write_reg(DISPC_TIMING_H(channel), timing_h); | 3157 | dispc_write_reg(DISPC_TIMING_H(channel), timing_h); |
3164 | dispc_write_reg(DISPC_TIMING_V(channel), timing_v); | 3158 | dispc_write_reg(DISPC_TIMING_V(channel), timing_v); |
3165 | 3159 | ||
3166 | switch (vsync_level) { | 3160 | switch (ovt->vsync_level) { |
3167 | case OMAPDSS_SIG_ACTIVE_LOW: | 3161 | case OMAPDSS_SIG_ACTIVE_LOW: |
3168 | vs = true; | 3162 | vs = true; |
3169 | break; | 3163 | break; |
@@ -3174,7 +3168,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, | |||
3174 | BUG(); | 3168 | BUG(); |
3175 | } | 3169 | } |
3176 | 3170 | ||
3177 | switch (hsync_level) { | 3171 | switch (ovt->hsync_level) { |
3178 | case OMAPDSS_SIG_ACTIVE_LOW: | 3172 | case OMAPDSS_SIG_ACTIVE_LOW: |
3179 | hs = true; | 3173 | hs = true; |
3180 | break; | 3174 | break; |
@@ -3185,7 +3179,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, | |||
3185 | BUG(); | 3179 | BUG(); |
3186 | } | 3180 | } |
3187 | 3181 | ||
3188 | switch (de_level) { | 3182 | switch (ovt->de_level) { |
3189 | case OMAPDSS_SIG_ACTIVE_LOW: | 3183 | case OMAPDSS_SIG_ACTIVE_LOW: |
3190 | de = true; | 3184 | de = true; |
3191 | break; | 3185 | break; |
@@ -3196,7 +3190,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, | |||
3196 | BUG(); | 3190 | BUG(); |
3197 | } | 3191 | } |
3198 | 3192 | ||
3199 | switch (data_pclk_edge) { | 3193 | switch (ovt->data_pclk_edge) { |
3200 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: | 3194 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: |
3201 | ipc = false; | 3195 | ipc = false; |
3202 | break; | 3196 | break; |
@@ -3210,7 +3204,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len, | |||
3210 | /* always use the 'rf' setting */ | 3204 | /* always use the 'rf' setting */ |
3211 | onoff = true; | 3205 | onoff = true; |
3212 | 3206 | ||
3213 | switch (sync_pclk_edge) { | 3207 | switch (ovt->sync_pclk_edge) { |
3214 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: | 3208 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: |
3215 | rf = false; | 3209 | rf = false; |
3216 | break; | 3210 | break; |
@@ -3270,11 +3264,7 @@ void dispc_mgr_set_timings(enum omap_channel channel, | |||
3270 | } | 3264 | } |
3271 | 3265 | ||
3272 | if (dss_mgr_is_lcd(channel)) { | 3266 | if (dss_mgr_is_lcd(channel)) { |
3273 | _dispc_mgr_set_lcd_timings(channel, | 3267 | _dispc_mgr_set_lcd_timings(channel, &t); |
3274 | t.hsync_len, t.hfront_porch, t.hback_porch, | ||
3275 | t.vsync_len, t.vfront_porch, t.vback_porch, | ||
3276 | t.vsync_level, t.hsync_level, t.data_pclk_edge, | ||
3277 | t.de_level, t.sync_pclk_edge); | ||
3278 | 3268 | ||
3279 | xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; | 3269 | xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; |
3280 | ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch; | 3270 | ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch; |