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authorDave Airlie <airlied@redhat.com>2017-08-21 03:37:33 -0400
committerDave Airlie <airlied@redhat.com>2017-08-21 03:37:33 -0400
commit3aadb888b1b62ba04798414cae431d3c3bd5f452 (patch)
tree3fac632c260090c711c766339eaa1fca31447f4c
parente5fa05b96b02f45a91a364d2121451a4da05cd84 (diff)
parentec73c4cfe7de6229e49989f7d7754a7039cd5c28 (diff)
Merge tag 'drm/tegra/for-4.14-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v4.14-rc1 This contains a couple of fixes and improvements for host1x, with some preparatory work for Tegra186 support. The remainder is cleanup and minor bugfixes for Tegra DRM along with enhancements to debuggability. There have also been some enhancements to the kernel interfaces for host1x job submissions and support for mmap'ing PRIME buffers directly, all of which get the interfaces very close to ready for serious work. * tag 'drm/tegra/for-4.14-rc1' of git://anongit.freedesktop.org/tegra/linux: (21 commits) drm/tegra: Prevent BOs from being freed during job submission drm/tegra: gem: Implement mmap() for PRIME buffers drm/tegra: Support render node drm/tegra: sor: Trace register accesses drm/tegra: dpaux: Trace register accesses drm/tegra: dsi: Trace register accesses drm/tegra: hdmi: Trace register accesses drm/tegra: dc: Trace register accesses drm/tegra: sor: Use unsigned int for register offsets drm/tegra: hdmi: Use unsigned int for register offsets drm/tegra: dsi: Use unsigned int for register offsets drm/tegra: dpaux: Use unsigned int for register offsets drm/tegra: dc: Use unsigned int for register offsets drm/tegra: Fix NULL deref in debugfs/iova drm/tegra: switch to drm_*_get(), drm_*_put() helpers drm/tegra: Set MODULE_FIRMWARE for the VIC drm/tegra: Add CONFIG_OF dependency gpu: host1x: Support sub-devices recursively gpu: host1x: fix error return code in host1x_probe() gpu: host1x: Fix bitshift/mask multipliers ...
-rw-r--r--drivers/gpu/drm/tegra/Kconfig1
-rw-r--r--drivers/gpu/drm/tegra/Makefile2
-rw-r--r--drivers/gpu/drm/tegra/dpaux.c12
-rw-r--r--drivers/gpu/drm/tegra/drm.c102
-rw-r--r--drivers/gpu/drm/tegra/drm.h12
-rw-r--r--drivers/gpu/drm/tegra/dsi.c14
-rw-r--r--drivers/gpu/drm/tegra/fb.c8
-rw-r--r--drivers/gpu/drm/tegra/gem.c57
-rw-r--r--drivers/gpu/drm/tegra/hdmi.c12
-rw-r--r--drivers/gpu/drm/tegra/sor.c12
-rw-r--r--drivers/gpu/drm/tegra/trace.c2
-rw-r--r--drivers/gpu/drm/tegra/trace.h68
-rw-r--r--drivers/gpu/drm/tegra/vic.c15
-rw-r--r--drivers/gpu/host1x/bus.c18
-rw-r--r--drivers/gpu/host1x/dev.c4
-rw-r--r--drivers/gpu/host1x/hw/intr_hw.c24
-rw-r--r--drivers/gpu/host1x/hw/syncpt_hw.c2
-rw-r--r--drivers/gpu/host1x/job.c8
18 files changed, 276 insertions, 97 deletions
diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig
index 2db29d67193d..dc58ab140151 100644
--- a/drivers/gpu/drm/tegra/Kconfig
+++ b/drivers/gpu/drm/tegra/Kconfig
@@ -3,6 +3,7 @@ config DRM_TEGRA
3 depends on ARCH_TEGRA || (ARM && COMPILE_TEST) 3 depends on ARCH_TEGRA || (ARM && COMPILE_TEST)
4 depends on COMMON_CLK 4 depends on COMMON_CLK
5 depends on DRM 5 depends on DRM
6 depends on OF
6 select DRM_KMS_HELPER 7 select DRM_KMS_HELPER
7 select DRM_MIPI_DSI 8 select DRM_MIPI_DSI
8 select DRM_PANEL 9 select DRM_PANEL
diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
index 6af3a9ad6565..8927784396e8 100644
--- a/drivers/gpu/drm/tegra/Makefile
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -17,4 +17,6 @@ tegra-drm-y := \
17 falcon.o \ 17 falcon.o \
18 vic.o 18 vic.o
19 19
20tegra-drm-y += trace.o
21
20obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o 22obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 2fde44c3a1b3..e4da041ba89b 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -25,6 +25,7 @@
25 25
26#include "dpaux.h" 26#include "dpaux.h"
27#include "drm.h" 27#include "drm.h"
28#include "trace.h"
28 29
29static DEFINE_MUTEX(dpaux_lock); 30static DEFINE_MUTEX(dpaux_lock);
30static LIST_HEAD(dpaux_list); 31static LIST_HEAD(dpaux_list);
@@ -65,14 +66,19 @@ static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
65} 66}
66 67
67static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, 68static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
68 unsigned long offset) 69 unsigned int offset)
69{ 70{
70 return readl(dpaux->regs + (offset << 2)); 71 u32 value = readl(dpaux->regs + (offset << 2));
72
73 trace_dpaux_readl(dpaux->dev, offset, value);
74
75 return value;
71} 76}
72 77
73static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, 78static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
74 u32 value, unsigned long offset) 79 u32 value, unsigned int offset)
75{ 80{
81 trace_dpaux_writel(dpaux->dev, offset, value);
76 writel(value, dpaux->regs + (offset << 2)); 82 writel(value, dpaux->regs + (offset << 2));
77} 83}
78 84
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 224ce1dbb1cb..597d563d636a 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -306,8 +306,6 @@ host1x_bo_lookup(struct drm_file *file, u32 handle)
306 if (!gem) 306 if (!gem)
307 return NULL; 307 return NULL;
308 308
309 drm_gem_object_unreference_unlocked(gem);
310
311 bo = to_tegra_bo(gem); 309 bo = to_tegra_bo(gem);
312 return &bo->base; 310 return &bo->base;
313} 311}
@@ -396,8 +394,10 @@ int tegra_drm_submit(struct tegra_drm_context *context,
396 (void __user *)(uintptr_t)args->waitchks; 394 (void __user *)(uintptr_t)args->waitchks;
397 struct drm_tegra_syncpt syncpt; 395 struct drm_tegra_syncpt syncpt;
398 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); 396 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
397 struct drm_gem_object **refs;
399 struct host1x_syncpt *sp; 398 struct host1x_syncpt *sp;
400 struct host1x_job *job; 399 struct host1x_job *job;
400 unsigned int num_refs;
401 int err; 401 int err;
402 402
403 /* We don't yet support other than one syncpt_incr struct per submit */ 403 /* We don't yet support other than one syncpt_incr struct per submit */
@@ -419,6 +419,21 @@ int tegra_drm_submit(struct tegra_drm_context *context,
419 job->class = context->client->base.class; 419 job->class = context->client->base.class;
420 job->serialize = true; 420 job->serialize = true;
421 421
422 /*
423 * Track referenced BOs so that they can be unreferenced after the
424 * submission is complete.
425 */
426 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
427
428 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
429 if (!refs) {
430 err = -ENOMEM;
431 goto put;
432 }
433
434 /* reuse as an iterator later */
435 num_refs = 0;
436
422 while (num_cmdbufs) { 437 while (num_cmdbufs) {
423 struct drm_tegra_cmdbuf cmdbuf; 438 struct drm_tegra_cmdbuf cmdbuf;
424 struct host1x_bo *bo; 439 struct host1x_bo *bo;
@@ -447,6 +462,7 @@ int tegra_drm_submit(struct tegra_drm_context *context,
447 462
448 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); 463 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
449 obj = host1x_to_tegra_bo(bo); 464 obj = host1x_to_tegra_bo(bo);
465 refs[num_refs++] = &obj->gem;
450 466
451 /* 467 /*
452 * Gather buffer base address must be 4-bytes aligned, 468 * Gather buffer base address must be 4-bytes aligned,
@@ -476,6 +492,7 @@ int tegra_drm_submit(struct tegra_drm_context *context,
476 492
477 reloc = &job->relocarray[num_relocs]; 493 reloc = &job->relocarray[num_relocs];
478 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); 494 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
495 refs[num_refs++] = &obj->gem;
479 496
480 /* 497 /*
481 * The unaligned cmdbuf offset will cause an unaligned write 498 * The unaligned cmdbuf offset will cause an unaligned write
@@ -489,6 +506,7 @@ int tegra_drm_submit(struct tegra_drm_context *context,
489 } 506 }
490 507
491 obj = host1x_to_tegra_bo(reloc->target.bo); 508 obj = host1x_to_tegra_bo(reloc->target.bo);
509 refs[num_refs++] = &obj->gem;
492 510
493 if (reloc->target.offset >= obj->gem.size) { 511 if (reloc->target.offset >= obj->gem.size) {
494 err = -EINVAL; 512 err = -EINVAL;
@@ -508,6 +526,7 @@ int tegra_drm_submit(struct tegra_drm_context *context,
508 goto fail; 526 goto fail;
509 527
510 obj = host1x_to_tegra_bo(wait->bo); 528 obj = host1x_to_tegra_bo(wait->bo);
529 refs[num_refs++] = &obj->gem;
511 530
512 /* 531 /*
513 * The unaligned offset will cause an unaligned write during 532 * The unaligned offset will cause an unaligned write during
@@ -547,17 +566,20 @@ int tegra_drm_submit(struct tegra_drm_context *context,
547 goto fail; 566 goto fail;
548 567
549 err = host1x_job_submit(job); 568 err = host1x_job_submit(job);
550 if (err) 569 if (err) {
551 goto fail_submit; 570 host1x_job_unpin(job);
571 goto fail;
572 }
552 573
553 args->fence = job->syncpt_end; 574 args->fence = job->syncpt_end;
554 575
555 host1x_job_put(job);
556 return 0;
557
558fail_submit:
559 host1x_job_unpin(job);
560fail: 576fail:
577 while (num_refs--)
578 drm_gem_object_put_unlocked(refs[num_refs]);
579
580 kfree(refs);
581
582put:
561 host1x_job_put(job); 583 host1x_job_put(job);
562 return err; 584 return err;
563} 585}
@@ -593,7 +615,7 @@ static int tegra_gem_mmap(struct drm_device *drm, void *data,
593 615
594 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); 616 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
595 617
596 drm_gem_object_unreference_unlocked(gem); 618 drm_gem_object_put_unlocked(gem);
597 619
598 return 0; 620 return 0;
599} 621}
@@ -860,7 +882,7 @@ static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
860 bo->tiling.mode = mode; 882 bo->tiling.mode = mode;
861 bo->tiling.value = value; 883 bo->tiling.value = value;
862 884
863 drm_gem_object_unreference_unlocked(gem); 885 drm_gem_object_put_unlocked(gem);
864 886
865 return 0; 887 return 0;
866} 888}
@@ -900,7 +922,7 @@ static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
900 break; 922 break;
901 } 923 }
902 924
903 drm_gem_object_unreference_unlocked(gem); 925 drm_gem_object_put_unlocked(gem);
904 926
905 return err; 927 return err;
906} 928}
@@ -925,7 +947,7 @@ static int tegra_gem_set_flags(struct drm_device *drm, void *data,
925 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) 947 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
926 bo->flags |= TEGRA_BO_BOTTOM_UP; 948 bo->flags |= TEGRA_BO_BOTTOM_UP;
927 949
928 drm_gem_object_unreference_unlocked(gem); 950 drm_gem_object_put_unlocked(gem);
929 951
930 return 0; 952 return 0;
931} 953}
@@ -947,7 +969,7 @@ static int tegra_gem_get_flags(struct drm_device *drm, void *data,
947 if (bo->flags & TEGRA_BO_BOTTOM_UP) 969 if (bo->flags & TEGRA_BO_BOTTOM_UP)
948 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; 970 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
949 971
950 drm_gem_object_unreference_unlocked(gem); 972 drm_gem_object_put_unlocked(gem);
951 973
952 return 0; 974 return 0;
953} 975}
@@ -955,20 +977,34 @@ static int tegra_gem_get_flags(struct drm_device *drm, void *data,
955 977
956static const struct drm_ioctl_desc tegra_drm_ioctls[] = { 978static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
957#ifdef CONFIG_DRM_TEGRA_STAGING 979#ifdef CONFIG_DRM_TEGRA_STAGING
958 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0), 980 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
959 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0), 981 DRM_UNLOCKED | DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0), 982 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
961 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0), 983 DRM_UNLOCKED | DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0), 984 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
963 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0), 985 DRM_UNLOCKED | DRM_RENDER_ALLOW),
964 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0), 986 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
965 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0), 987 DRM_UNLOCKED | DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0), 988 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
967 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0), 989 DRM_UNLOCKED | DRM_RENDER_ALLOW),
968 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0), 990 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
969 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0), 991 DRM_UNLOCKED | DRM_RENDER_ALLOW),
970 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0), 992 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
971 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0), 993 DRM_UNLOCKED | DRM_RENDER_ALLOW),
994 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
995 DRM_UNLOCKED | DRM_RENDER_ALLOW),
996 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
997 DRM_UNLOCKED | DRM_RENDER_ALLOW),
998 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
999 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1000 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
1001 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1002 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
1003 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1004 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
1005 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1006 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
1007 DRM_UNLOCKED | DRM_RENDER_ALLOW),
972#endif 1008#endif
973}; 1009};
974 1010
@@ -1035,9 +1071,11 @@ static int tegra_debugfs_iova(struct seq_file *s, void *data)
1035 struct tegra_drm *tegra = drm->dev_private; 1071 struct tegra_drm *tegra = drm->dev_private;
1036 struct drm_printer p = drm_seq_file_printer(s); 1072 struct drm_printer p = drm_seq_file_printer(s);
1037 1073
1038 mutex_lock(&tegra->mm_lock); 1074 if (tegra->domain) {
1039 drm_mm_print(&tegra->mm, &p); 1075 mutex_lock(&tegra->mm_lock);
1040 mutex_unlock(&tegra->mm_lock); 1076 drm_mm_print(&tegra->mm, &p);
1077 mutex_unlock(&tegra->mm_lock);
1078 }
1041 1079
1042 return 0; 1080 return 0;
1043} 1081}
@@ -1057,7 +1095,7 @@ static int tegra_debugfs_init(struct drm_minor *minor)
1057 1095
1058static struct drm_driver tegra_drm_driver = { 1096static struct drm_driver tegra_drm_driver = {
1059 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | 1097 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
1060 DRIVER_ATOMIC, 1098 DRIVER_ATOMIC | DRIVER_RENDER,
1061 .load = tegra_drm_load, 1099 .load = tegra_drm_load,
1062 .unload = tegra_drm_unload, 1100 .unload = tegra_drm_unload,
1063 .open = tegra_drm_open, 1101 .open = tegra_drm_open,
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 6d6da01282f3..063f5d397526 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -23,6 +23,7 @@
23#include <drm/drm_fixed.h> 23#include <drm/drm_fixed.h>
24 24
25#include "gem.h" 25#include "gem.h"
26#include "trace.h"
26 27
27struct reset_control; 28struct reset_control;
28 29
@@ -172,14 +173,19 @@ static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
172} 173}
173 174
174static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, 175static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
175 unsigned long offset) 176 unsigned int offset)
176{ 177{
178 trace_dc_writel(dc->dev, offset, value);
177 writel(value, dc->regs + (offset << 2)); 179 writel(value, dc->regs + (offset << 2));
178} 180}
179 181
180static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned long offset) 182static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)
181{ 183{
182 return readl(dc->regs + (offset << 2)); 184 u32 value = readl(dc->regs + (offset << 2));
185
186 trace_dc_readl(dc->dev, offset, value);
187
188 return value;
183} 189}
184 190
185struct tegra_dc_window { 191struct tegra_dc_window {
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index e4b5aedfdbd4..046649ec9441 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -28,6 +28,7 @@
28#include "drm.h" 28#include "drm.h"
29#include "dsi.h" 29#include "dsi.h"
30#include "mipi-phy.h" 30#include "mipi-phy.h"
31#include "trace.h"
31 32
32struct tegra_dsi_state { 33struct tegra_dsi_state {
33 struct drm_connector_state base; 34 struct drm_connector_state base;
@@ -105,15 +106,20 @@ static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
105 return to_dsi_state(dsi->output.connector.state); 106 return to_dsi_state(dsi->output.connector.state);
106} 107}
107 108
108static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg) 109static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
109{ 110{
110 return readl(dsi->regs + (reg << 2)); 111 u32 value = readl(dsi->regs + (offset << 2));
112
113 trace_dsi_readl(dsi->dev, offset, value);
114
115 return value;
111} 116}
112 117
113static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, 118static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
114 unsigned long reg) 119 unsigned int offset)
115{ 120{
116 writel(value, dsi->regs + (reg << 2)); 121 trace_dsi_writel(dsi->dev, offset, value);
122 writel(value, dsi->regs + (offset << 2));
117} 123}
118 124
119static int tegra_dsi_show_regs(struct seq_file *s, void *data) 125static int tegra_dsi_show_regs(struct seq_file *s, void *data)
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
index 25acb73ee728..80540c1c66dc 100644
--- a/drivers/gpu/drm/tegra/fb.c
+++ b/drivers/gpu/drm/tegra/fb.c
@@ -88,7 +88,7 @@ static void tegra_fb_destroy(struct drm_framebuffer *framebuffer)
88 if (bo->pages) 88 if (bo->pages)
89 vunmap(bo->vaddr); 89 vunmap(bo->vaddr);
90 90
91 drm_gem_object_unreference_unlocked(&bo->gem); 91 drm_gem_object_put_unlocked(&bo->gem);
92 } 92 }
93 } 93 }
94 94
@@ -195,7 +195,7 @@ struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
195 195
196unreference: 196unreference:
197 while (i--) 197 while (i--)
198 drm_gem_object_unreference_unlocked(&planes[i]->gem); 198 drm_gem_object_put_unlocked(&planes[i]->gem);
199 199
200 return ERR_PTR(err); 200 return ERR_PTR(err);
201} 201}
@@ -242,7 +242,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper,
242 info = drm_fb_helper_alloc_fbi(helper); 242 info = drm_fb_helper_alloc_fbi(helper);
243 if (IS_ERR(info)) { 243 if (IS_ERR(info)) {
244 dev_err(drm->dev, "failed to allocate framebuffer info\n"); 244 dev_err(drm->dev, "failed to allocate framebuffer info\n");
245 drm_gem_object_unreference_unlocked(&bo->gem); 245 drm_gem_object_put_unlocked(&bo->gem);
246 return PTR_ERR(info); 246 return PTR_ERR(info);
247 } 247 }
248 248
@@ -251,7 +251,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper,
251 err = PTR_ERR(fbdev->fb); 251 err = PTR_ERR(fbdev->fb);
252 dev_err(drm->dev, "failed to allocate DRM framebuffer: %d\n", 252 dev_err(drm->dev, "failed to allocate DRM framebuffer: %d\n",
253 err); 253 err);
254 drm_gem_object_unreference_unlocked(&bo->gem); 254 drm_gem_object_put_unlocked(&bo->gem);
255 return PTR_ERR(fbdev->fb); 255 return PTR_ERR(fbdev->fb);
256 } 256 }
257 257
diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index c6079affe642..ab1e53d434e8 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -24,7 +24,7 @@ static void tegra_bo_put(struct host1x_bo *bo)
24{ 24{
25 struct tegra_bo *obj = host1x_to_tegra_bo(bo); 25 struct tegra_bo *obj = host1x_to_tegra_bo(bo);
26 26
27 drm_gem_object_unreference_unlocked(&obj->gem); 27 drm_gem_object_put_unlocked(&obj->gem);
28} 28}
29 29
30static dma_addr_t tegra_bo_pin(struct host1x_bo *bo, struct sg_table **sgt) 30static dma_addr_t tegra_bo_pin(struct host1x_bo *bo, struct sg_table **sgt)
@@ -95,7 +95,7 @@ static struct host1x_bo *tegra_bo_get(struct host1x_bo *bo)
95{ 95{
96 struct tegra_bo *obj = host1x_to_tegra_bo(bo); 96 struct tegra_bo *obj = host1x_to_tegra_bo(bo);
97 97
98 drm_gem_object_reference(&obj->gem); 98 drm_gem_object_get(&obj->gem);
99 99
100 return bo; 100 return bo;
101} 101}
@@ -325,7 +325,7 @@ struct tegra_bo *tegra_bo_create_with_handle(struct drm_file *file,
325 return ERR_PTR(err); 325 return ERR_PTR(err);
326 } 326 }
327 327
328 drm_gem_object_unreference_unlocked(&bo->gem); 328 drm_gem_object_put_unlocked(&bo->gem);
329 329
330 return bo; 330 return bo;
331} 331}
@@ -460,30 +460,28 @@ const struct vm_operations_struct tegra_bo_vm_ops = {
460 .close = drm_gem_vm_close, 460 .close = drm_gem_vm_close,
461}; 461};
462 462
463int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma) 463static int tegra_gem_mmap(struct drm_gem_object *gem,
464 struct vm_area_struct *vma)
464{ 465{
465 struct drm_gem_object *gem; 466 struct tegra_bo *bo = to_tegra_bo(gem);
466 struct tegra_bo *bo;
467 int ret;
468
469 ret = drm_gem_mmap(file, vma);
470 if (ret)
471 return ret;
472
473 gem = vma->vm_private_data;
474 bo = to_tegra_bo(gem);
475 467
476 if (!bo->pages) { 468 if (!bo->pages) {
477 unsigned long vm_pgoff = vma->vm_pgoff; 469 unsigned long vm_pgoff = vma->vm_pgoff;
470 int err;
478 471
472 /*
473 * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(),
474 * and set the vm_pgoff (used as a fake buffer offset by DRM)
475 * to 0 as we want to map the whole buffer.
476 */
479 vma->vm_flags &= ~VM_PFNMAP; 477 vma->vm_flags &= ~VM_PFNMAP;
480 vma->vm_pgoff = 0; 478 vma->vm_pgoff = 0;
481 479
482 ret = dma_mmap_wc(gem->dev->dev, vma, bo->vaddr, bo->paddr, 480 err = dma_mmap_wc(gem->dev->dev, vma, bo->vaddr, bo->paddr,
483 gem->size); 481 gem->size);
484 if (ret) { 482 if (err < 0) {
485 drm_gem_vm_close(vma); 483 drm_gem_vm_close(vma);
486 return ret; 484 return err;
487 } 485 }
488 486
489 vma->vm_pgoff = vm_pgoff; 487 vma->vm_pgoff = vm_pgoff;
@@ -499,6 +497,20 @@ int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma)
499 return 0; 497 return 0;
500} 498}
501 499
500int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma)
501{
502 struct drm_gem_object *gem;
503 int err;
504
505 err = drm_gem_mmap(file, vma);
506 if (err < 0)
507 return err;
508
509 gem = vma->vm_private_data;
510
511 return tegra_gem_mmap(gem, vma);
512}
513
502static struct sg_table * 514static struct sg_table *
503tegra_gem_prime_map_dma_buf(struct dma_buf_attachment *attach, 515tegra_gem_prime_map_dma_buf(struct dma_buf_attachment *attach,
504 enum dma_data_direction dir) 516 enum dma_data_direction dir)
@@ -582,7 +594,14 @@ static void tegra_gem_prime_kunmap(struct dma_buf *buf, unsigned long page,
582 594
583static int tegra_gem_prime_mmap(struct dma_buf *buf, struct vm_area_struct *vma) 595static int tegra_gem_prime_mmap(struct dma_buf *buf, struct vm_area_struct *vma)
584{ 596{
585 return -EINVAL; 597 struct drm_gem_object *gem = buf->priv;
598 int err;
599
600 err = drm_gem_mmap_obj(gem, gem->size, vma);
601 if (err < 0)
602 return err;
603
604 return tegra_gem_mmap(gem, vma);
586} 605}
587 606
588static void *tegra_gem_prime_vmap(struct dma_buf *buf) 607static void *tegra_gem_prime_vmap(struct dma_buf *buf)
@@ -633,7 +652,7 @@ struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm,
633 struct drm_gem_object *gem = buf->priv; 652 struct drm_gem_object *gem = buf->priv;
634 653
635 if (gem->dev == drm) { 654 if (gem->dev == drm) {
636 drm_gem_object_reference(gem); 655 drm_gem_object_get(gem);
637 return gem; 656 return gem;
638 } 657 }
639 } 658 }
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index a621b0da4092..5b9d83b71943 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -24,6 +24,7 @@
24#include "hdmi.h" 24#include "hdmi.h"
25#include "drm.h" 25#include "drm.h"
26#include "dc.h" 26#include "dc.h"
27#include "trace.h"
27 28
28#define HDMI_ELD_BUFFER_SIZE 96 29#define HDMI_ELD_BUFFER_SIZE 96
29 30
@@ -100,14 +101,19 @@ enum {
100}; 101};
101 102
102static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi, 103static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
103 unsigned long offset) 104 unsigned int offset)
104{ 105{
105 return readl(hdmi->regs + (offset << 2)); 106 u32 value = readl(hdmi->regs + (offset << 2));
107
108 trace_hdmi_readl(hdmi->dev, offset, value);
109
110 return value;
106} 111}
107 112
108static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value, 113static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
109 unsigned long offset) 114 unsigned int offset)
110{ 115{
116 trace_hdmi_writel(hdmi->dev, offset, value);
111 writel(value, hdmi->regs + (offset << 2)); 117 writel(value, hdmi->regs + (offset << 2));
112} 118}
113 119
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index e0642d05a8d3..7ab1d1dc7cd7 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -26,6 +26,7 @@
26#include "dc.h" 26#include "dc.h"
27#include "drm.h" 27#include "drm.h"
28#include "sor.h" 28#include "sor.h"
29#include "trace.h"
29 30
30#define SOR_REKEY 0x38 31#define SOR_REKEY 0x38
31 32
@@ -232,14 +233,19 @@ static inline struct tegra_sor *to_sor(struct tegra_output *output)
232 return container_of(output, struct tegra_sor, output); 233 return container_of(output, struct tegra_sor, output);
233} 234}
234 235
235static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) 236static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
236{ 237{
237 return readl(sor->regs + (offset << 2)); 238 u32 value = readl(sor->regs + (offset << 2));
239
240 trace_sor_readl(sor->dev, offset, value);
241
242 return value;
238} 243}
239 244
240static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 245static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
241 unsigned long offset) 246 unsigned int offset)
242{ 247{
248 trace_sor_writel(sor->dev, offset, value);
243 writel(value, sor->regs + (offset << 2)); 249 writel(value, sor->regs + (offset << 2));
244} 250}
245 251
diff --git a/drivers/gpu/drm/tegra/trace.c b/drivers/gpu/drm/tegra/trace.c
new file mode 100644
index 000000000000..006f65c72a34
--- /dev/null
+++ b/drivers/gpu/drm/tegra/trace.c
@@ -0,0 +1,2 @@
1#define CREATE_TRACE_POINTS
2#include "trace.h"
diff --git a/drivers/gpu/drm/tegra/trace.h b/drivers/gpu/drm/tegra/trace.h
new file mode 100644
index 000000000000..e9b7cdad5c4c
--- /dev/null
+++ b/drivers/gpu/drm/tegra/trace.h
@@ -0,0 +1,68 @@
1#undef TRACE_SYSTEM
2#define TRACE_SYSTEM tegra
3
4#if !defined(DRM_TEGRA_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
5#define DRM_TEGRA_TRACE_H 1
6
7#include <linux/device.h>
8#include <linux/tracepoint.h>
9
10DECLARE_EVENT_CLASS(register_access,
11 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
12 TP_ARGS(dev, offset, value),
13 TP_STRUCT__entry(
14 __field(struct device *, dev)
15 __field(unsigned int, offset)
16 __field(u32, value)
17 ),
18 TP_fast_assign(
19 __entry->dev = dev;
20 __entry->offset = offset;
21 __entry->value = value;
22 ),
23 TP_printk("%s %04x %08x", dev_name(__entry->dev), __entry->offset,
24 __entry->value)
25);
26
27DEFINE_EVENT(register_access, dc_writel,
28 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
29 TP_ARGS(dev, offset, value));
30DEFINE_EVENT(register_access, dc_readl,
31 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
32 TP_ARGS(dev, offset, value));
33
34DEFINE_EVENT(register_access, hdmi_writel,
35 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
36 TP_ARGS(dev, offset, value));
37DEFINE_EVENT(register_access, hdmi_readl,
38 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
39 TP_ARGS(dev, offset, value));
40
41DEFINE_EVENT(register_access, dsi_writel,
42 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
43 TP_ARGS(dev, offset, value));
44DEFINE_EVENT(register_access, dsi_readl,
45 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
46 TP_ARGS(dev, offset, value));
47
48DEFINE_EVENT(register_access, dpaux_writel,
49 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
50 TP_ARGS(dev, offset, value));
51DEFINE_EVENT(register_access, dpaux_readl,
52 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
53 TP_ARGS(dev, offset, value));
54
55DEFINE_EVENT(register_access, sor_writel,
56 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
57 TP_ARGS(dev, offset, value));
58DEFINE_EVENT(register_access, sor_readl,
59 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
60 TP_ARGS(dev, offset, value));
61
62#endif /* DRM_TEGRA_TRACE_H */
63
64/* This part must be outside protection */
65#undef TRACE_INCLUDE_PATH
66#define TRACE_INCLUDE_PATH .
67#define TRACE_INCLUDE_FILE trace
68#include <trace/define_trace.h>
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index 47cb1aaa58b1..2448229fa653 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -258,12 +258,16 @@ static const struct tegra_drm_client_ops vic_ops = {
258 .submit = tegra_drm_submit, 258 .submit = tegra_drm_submit,
259}; 259};
260 260
261#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
262
261static const struct vic_config vic_t124_config = { 263static const struct vic_config vic_t124_config = {
262 .firmware = "nvidia/tegra124/vic03_ucode.bin", 264 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
263}; 265};
264 266
267#define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
268
265static const struct vic_config vic_t210_config = { 269static const struct vic_config vic_t210_config = {
266 .firmware = "nvidia/tegra210/vic04_ucode.bin", 270 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
267}; 271};
268 272
269static const struct of_device_id vic_match[] = { 273static const struct of_device_id vic_match[] = {
@@ -394,3 +398,10 @@ struct platform_driver tegra_vic_driver = {
394 .probe = vic_probe, 398 .probe = vic_probe,
395 .remove = vic_remove, 399 .remove = vic_remove,
396}; 400};
401
402#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
403MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
404#endif
405#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
406MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
407#endif
diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c
index 7ece0e9058c6..f9cde03030fd 100644
--- a/drivers/gpu/host1x/bus.c
+++ b/drivers/gpu/host1x/bus.c
@@ -44,9 +44,12 @@ struct host1x_subdev {
44 * @np: device node 44 * @np: device node
45 */ 45 */
46static int host1x_subdev_add(struct host1x_device *device, 46static int host1x_subdev_add(struct host1x_device *device,
47 struct host1x_driver *driver,
47 struct device_node *np) 48 struct device_node *np)
48{ 49{
49 struct host1x_subdev *subdev; 50 struct host1x_subdev *subdev;
51 struct device_node *child;
52 int err;
50 53
51 subdev = kzalloc(sizeof(*subdev), GFP_KERNEL); 54 subdev = kzalloc(sizeof(*subdev), GFP_KERNEL);
52 if (!subdev) 55 if (!subdev)
@@ -59,6 +62,19 @@ static int host1x_subdev_add(struct host1x_device *device,
59 list_add_tail(&subdev->list, &device->subdevs); 62 list_add_tail(&subdev->list, &device->subdevs);
60 mutex_unlock(&device->subdevs_lock); 63 mutex_unlock(&device->subdevs_lock);
61 64
65 /* recursively add children */
66 for_each_child_of_node(np, child) {
67 if (of_match_node(driver->subdevs, child) &&
68 of_device_is_available(child)) {
69 err = host1x_subdev_add(device, driver, child);
70 if (err < 0) {
71 /* XXX cleanup? */
72 of_node_put(child);
73 return err;
74 }
75 }
76 }
77
62 return 0; 78 return 0;
63} 79}
64 80
@@ -87,7 +103,7 @@ static int host1x_device_parse_dt(struct host1x_device *device,
87 for_each_child_of_node(device->dev.parent->of_node, np) { 103 for_each_child_of_node(device->dev.parent->of_node, np) {
88 if (of_match_node(driver->subdevs, np) && 104 if (of_match_node(driver->subdevs, np) &&
89 of_device_is_available(np)) { 105 of_device_is_available(np)) {
90 err = host1x_subdev_add(device, np); 106 err = host1x_subdev_add(device, driver, np);
91 if (err < 0) { 107 if (err < 0) {
92 of_node_put(np); 108 of_node_put(np);
93 return err; 109 return err;
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 778272514164..7f22c5c37660 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -134,8 +134,8 @@ static int host1x_probe(struct platform_device *pdev)
134 134
135 syncpt_irq = platform_get_irq(pdev, 0); 135 syncpt_irq = platform_get_irq(pdev, 0);
136 if (syncpt_irq < 0) { 136 if (syncpt_irq < 0) {
137 dev_err(&pdev->dev, "failed to get IRQ\n"); 137 dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq);
138 return -ENXIO; 138 return syncpt_irq;
139 } 139 }
140 140
141 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 141 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
diff --git a/drivers/gpu/host1x/hw/intr_hw.c b/drivers/gpu/host1x/hw/intr_hw.c
index dacb8009a605..37ebb51703fa 100644
--- a/drivers/gpu/host1x/hw/intr_hw.c
+++ b/drivers/gpu/host1x/hw/intr_hw.c
@@ -33,10 +33,10 @@ static void host1x_intr_syncpt_handle(struct host1x_syncpt *syncpt)
33 unsigned int id = syncpt->id; 33 unsigned int id = syncpt->id;
34 struct host1x *host = syncpt->host; 34 struct host1x *host = syncpt->host;
35 35
36 host1x_sync_writel(host, BIT_MASK(id), 36 host1x_sync_writel(host, BIT(id % 32),
37 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(BIT_WORD(id))); 37 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32));
38 host1x_sync_writel(host, BIT_MASK(id), 38 host1x_sync_writel(host, BIT(id % 32),
39 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(BIT_WORD(id))); 39 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32));
40 40
41 schedule_work(&syncpt->intr.work); 41 schedule_work(&syncpt->intr.work);
42} 42}
@@ -50,9 +50,9 @@ static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id)
50 for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) { 50 for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) {
51 reg = host1x_sync_readl(host, 51 reg = host1x_sync_readl(host,
52 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i)); 52 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
53 for_each_set_bit(id, &reg, BITS_PER_LONG) { 53 for_each_set_bit(id, &reg, 32) {
54 struct host1x_syncpt *syncpt = 54 struct host1x_syncpt *syncpt =
55 host->syncpt + (i * BITS_PER_LONG + id); 55 host->syncpt + (i * 32 + id);
56 host1x_intr_syncpt_handle(syncpt); 56 host1x_intr_syncpt_handle(syncpt);
57 } 57 }
58 } 58 }
@@ -117,17 +117,17 @@ static void _host1x_intr_set_syncpt_threshold(struct host1x *host,
117static void _host1x_intr_enable_syncpt_intr(struct host1x *host, 117static void _host1x_intr_enable_syncpt_intr(struct host1x *host,
118 unsigned int id) 118 unsigned int id)
119{ 119{
120 host1x_sync_writel(host, BIT_MASK(id), 120 host1x_sync_writel(host, BIT(id % 32),
121 HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(BIT_WORD(id))); 121 HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id / 32));
122} 122}
123 123
124static void _host1x_intr_disable_syncpt_intr(struct host1x *host, 124static void _host1x_intr_disable_syncpt_intr(struct host1x *host,
125 unsigned int id) 125 unsigned int id)
126{ 126{
127 host1x_sync_writel(host, BIT_MASK(id), 127 host1x_sync_writel(host, BIT(id % 32),
128 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(BIT_WORD(id))); 128 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32));
129 host1x_sync_writel(host, BIT_MASK(id), 129 host1x_sync_writel(host, BIT(id % 32),
130 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(BIT_WORD(id))); 130 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32));
131} 131}
132 132
133static int _host1x_free_syncpt_irq(struct host1x *host) 133static int _host1x_free_syncpt_irq(struct host1x *host)
diff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c
index c93f74fcce72..7b0270d60742 100644
--- a/drivers/gpu/host1x/hw/syncpt_hw.c
+++ b/drivers/gpu/host1x/hw/syncpt_hw.c
@@ -89,7 +89,7 @@ static int syncpt_cpu_incr(struct host1x_syncpt *sp)
89 host1x_syncpt_idle(sp)) 89 host1x_syncpt_idle(sp))
90 return -EINVAL; 90 return -EINVAL;
91 91
92 host1x_sync_writel(host, BIT_MASK(sp->id), 92 host1x_sync_writel(host, BIT(sp->id % 32),
93 HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset)); 93 HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset));
94 wmb(); 94 wmb();
95 95
diff --git a/drivers/gpu/host1x/job.c b/drivers/gpu/host1x/job.c
index bee504406cfc..db509ab8874e 100644
--- a/drivers/gpu/host1x/job.c
+++ b/drivers/gpu/host1x/job.c
@@ -197,10 +197,6 @@ static unsigned int pin_job(struct host1x *host, struct host1x_job *job)
197 } 197 }
198 198
199 phys_addr = host1x_bo_pin(reloc->target.bo, &sgt); 199 phys_addr = host1x_bo_pin(reloc->target.bo, &sgt);
200 if (!phys_addr) {
201 err = -EINVAL;
202 goto unpin;
203 }
204 200
205 job->addr_phys[job->num_unpins] = phys_addr; 201 job->addr_phys[job->num_unpins] = phys_addr;
206 job->unpins[job->num_unpins].bo = reloc->target.bo; 202 job->unpins[job->num_unpins].bo = reloc->target.bo;
@@ -225,10 +221,6 @@ static unsigned int pin_job(struct host1x *host, struct host1x_job *job)
225 } 221 }
226 222
227 phys_addr = host1x_bo_pin(g->bo, &sgt); 223 phys_addr = host1x_bo_pin(g->bo, &sgt);
228 if (!phys_addr) {
229 err = -EINVAL;
230 goto unpin;
231 }
232 224
233 if (!IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL) && host->domain) { 225 if (!IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL) && host->domain) {
234 for_each_sg(sgt->sgl, sg, sgt->nents, j) 226 for_each_sg(sgt->sgl, sg, sgt->nents, j)