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authorHarry Wentland <harry.wentland@amd.com>2018-01-24 11:23:28 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-02-19 14:20:05 -0500
commit3a97f3fff110d17ecc957ea99d16a8877890b4eb (patch)
tree53b24579ed9fac1df7be92a1becc3cf0e9958660
parentbbad2da8b1c6a4216addcd59ab2999b4467c0a41 (diff)
drm/amd/display: Make couple functions in DCE80 TG static
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c125
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h6
2 files changed, 63 insertions, 68 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
index 265894851493..2934650e0434 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
@@ -84,7 +84,7 @@ static const struct dce110_timing_generator_offsets reg_offsets[] = {
84#define DCP_REG(reg) (reg + tg110->offsets.dcp) 84#define DCP_REG(reg) (reg + tg110->offsets.dcp)
85#define DMIF_REG(reg) (reg + tg110->offsets.dmif) 85#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
86 86
87void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz) 87static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
88{ 88{
89 uint64_t pix_dur; 89 uint64_t pix_dur;
90 uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 90 uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
@@ -115,6 +115,68 @@ static void program_timing(struct timing_generator *tg,
115 dce110_tg_program_timing(tg, timing, use_vbios); 115 dce110_tg_program_timing(tg, timing, use_vbios);
116} 116}
117 117
118static void dce80_timing_generator_enable_advanced_request(
119 struct timing_generator *tg,
120 bool enable,
121 const struct dc_crtc_timing *timing)
122{
123 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
124 uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
125 uint32_t value = dm_read_reg(tg->ctx, addr);
126
127 if (enable) {
128 set_reg_field_value(
129 value,
130 0,
131 CRTC_START_LINE_CONTROL,
132 CRTC_LEGACY_REQUESTOR_EN);
133 } else {
134 set_reg_field_value(
135 value,
136 1,
137 CRTC_START_LINE_CONTROL,
138 CRTC_LEGACY_REQUESTOR_EN);
139 }
140
141 if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
142 set_reg_field_value(
143 value,
144 3,
145 CRTC_START_LINE_CONTROL,
146 CRTC_ADVANCED_START_LINE_POSITION);
147 set_reg_field_value(
148 value,
149 0,
150 CRTC_START_LINE_CONTROL,
151 CRTC_PREFETCH_EN);
152 } else {
153 set_reg_field_value(
154 value,
155 4,
156 CRTC_START_LINE_CONTROL,
157 CRTC_ADVANCED_START_LINE_POSITION);
158 set_reg_field_value(
159 value,
160 1,
161 CRTC_START_LINE_CONTROL,
162 CRTC_PREFETCH_EN);
163 }
164
165 set_reg_field_value(
166 value,
167 1,
168 CRTC_START_LINE_CONTROL,
169 CRTC_PROGRESSIVE_START_LINE_EARLY);
170
171 set_reg_field_value(
172 value,
173 1,
174 CRTC_START_LINE_CONTROL,
175 CRTC_INTERLACE_START_LINE_EARLY);
176
177 dm_write_reg(tg->ctx, addr, value);
178}
179
118static const struct timing_generator_funcs dce80_tg_funcs = { 180static const struct timing_generator_funcs dce80_tg_funcs = {
119 .validate_timing = dce110_tg_validate_timing, 181 .validate_timing = dce110_tg_validate_timing,
120 .program_timing = program_timing, 182 .program_timing = program_timing,
@@ -176,64 +238,3 @@ void dce80_timing_generator_construct(
176 tg110->min_h_back_porch = 4; 238 tg110->min_h_back_porch = 4;
177} 239}
178 240
179void dce80_timing_generator_enable_advanced_request(
180 struct timing_generator *tg,
181 bool enable,
182 const struct dc_crtc_timing *timing)
183{
184 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
185 uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
186 uint32_t value = dm_read_reg(tg->ctx, addr);
187
188 if (enable) {
189 set_reg_field_value(
190 value,
191 0,
192 CRTC_START_LINE_CONTROL,
193 CRTC_LEGACY_REQUESTOR_EN);
194 } else {
195 set_reg_field_value(
196 value,
197 1,
198 CRTC_START_LINE_CONTROL,
199 CRTC_LEGACY_REQUESTOR_EN);
200 }
201
202 if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
203 set_reg_field_value(
204 value,
205 3,
206 CRTC_START_LINE_CONTROL,
207 CRTC_ADVANCED_START_LINE_POSITION);
208 set_reg_field_value(
209 value,
210 0,
211 CRTC_START_LINE_CONTROL,
212 CRTC_PREFETCH_EN);
213 } else {
214 set_reg_field_value(
215 value,
216 4,
217 CRTC_START_LINE_CONTROL,
218 CRTC_ADVANCED_START_LINE_POSITION);
219 set_reg_field_value(
220 value,
221 1,
222 CRTC_START_LINE_CONTROL,
223 CRTC_PREFETCH_EN);
224 }
225
226 set_reg_field_value(
227 value,
228 1,
229 CRTC_START_LINE_CONTROL,
230 CRTC_PROGRESSIVE_START_LINE_EARLY);
231
232 set_reg_field_value(
233 value,
234 1,
235 CRTC_START_LINE_CONTROL,
236 CRTC_INTERLACE_START_LINE_EARLY);
237
238 dm_write_reg(tg->ctx, addr, value);
239}
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h
index 9cebb24c94c8..8ff1b06bcd8b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h
@@ -36,10 +36,4 @@ void dce80_timing_generator_construct(
36 uint32_t instance, 36 uint32_t instance,
37 const struct dce110_timing_generator_offsets *offsets); 37 const struct dce110_timing_generator_offsets *offsets);
38 38
39/******** HW programming ************/
40void dce80_timing_generator_enable_advanced_request(
41 struct timing_generator *tg,
42 bool enable,
43 const struct dc_crtc_timing *timing);
44
45#endif /* __DC_TIMING_GENERATOR_DCE80_H__ */ 39#endif /* __DC_TIMING_GENERATOR_DCE80_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 13:54:05 -0400