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authorJean-Francois Moine <moinejf@free.fr>2016-09-18 03:59:50 -0400
committerVinod Koul <vinod.koul@intel.com>2016-09-26 13:45:06 -0400
commit3a03ea763a675ecb2a8805c6db01af125daa56e4 (patch)
tree0d09437e6c8e3f94529a4f1ebea2cf65d16ba5a8
parent34681d84a0f7cc22ded1413dc79eef8a2f23d9c3 (diff)
dmaengine: sun6i: Add support for Allwinner A83T (sun8i) variant
The A83T SoC has the same dma engine as the A31 (sun6i), with a reduced amount of endpoints and physical channels. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--Documentation/devicetree/bindings/dma/sun6i-dma.txt1
-rw-r--r--drivers/dma/sun6i-dma.c7
2 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
index d13c136cef8c..6b267045f522 100644
--- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
+++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
@@ -7,6 +7,7 @@ Required properties:
7- compatible: Must be one of 7- compatible: Must be one of
8 "allwinner,sun6i-a31-dma" 8 "allwinner,sun6i-a31-dma"
9 "allwinner,sun8i-a23-dma" 9 "allwinner,sun8i-a23-dma"
10 "allwinner,sun8i-a83t-dma"
10 "allwinner,sun8i-h3-dma" 11 "allwinner,sun8i-h3-dma"
11- reg: Should contain the registers base address and length 12- reg: Should contain the registers base address and length
12- interrupts: Should contain a reference to the interrupt used by this device 13- interrupts: Should contain a reference to the interrupt used by this device
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 3835fcde3545..83461994e418 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -1011,6 +1011,12 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = {
1011 .nr_max_vchans = 37, 1011 .nr_max_vchans = 37,
1012}; 1012};
1013 1013
1014static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
1015 .nr_max_channels = 8,
1016 .nr_max_requests = 28,
1017 .nr_max_vchans = 39,
1018};
1019
1014/* 1020/*
1015 * The H3 has 12 physical channels, a maximum DRQ port id of 27, 1021 * The H3 has 12 physical channels, a maximum DRQ port id of 27,
1016 * and a total of 34 usable source and destination endpoints. 1022 * and a total of 34 usable source and destination endpoints.
@@ -1025,6 +1031,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
1025static const struct of_device_id sun6i_dma_match[] = { 1031static const struct of_device_id sun6i_dma_match[] = {
1026 { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg }, 1032 { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
1027 { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg }, 1033 { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
1034 { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
1028 { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, 1035 { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
1029 { /* sentinel */ } 1036 { /* sentinel */ }
1030}; 1037};