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authorKevin Hilman <khilman@baylibre.com>2016-09-15 18:35:35 -0400
committerKevin Hilman <khilman@baylibre.com>2016-09-15 18:35:35 -0400
commit39f0d9803f393f3d78fc815736d024a8adc149a8 (patch)
tree4fd238ba20b377e5f042579f42098a9bf54a2277
parent29b4817d4018df78086157ea3a55c1d9424a7cfc (diff)
parentdfdd7d4af6ebee027be7bf2636b2314937948da6 (diff)
Merge tag 'amlogic-drivers-2' into v4.8/dt64-2
Amlogic driver updates for v4.9, 2nd round - media: update IR support for newer SoCs - firmware: add secure monitor driver - net: new stmmac glue driver - usb: udd DWC2 support for meson-gxbb - clocks: expose more clock IDs for use by DT - DT binding updates
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt45
-rw-r--r--Documentation/devicetree/bindings/net/meson-dwmac.txt45
-rw-r--r--Documentation/devicetree/bindings/phy/meson-usb2-phy.txt27
-rw-r--r--Documentation/devicetree/bindings/usb/dwc2.txt2
-rw-r--r--drivers/clk/meson/Makefile4
-rw-r--r--drivers/clk/meson/clkc.h2
-rw-r--r--drivers/clk/meson/gxbb-aoclk.c191
-rw-r--r--drivers/clk/meson/gxbb.c171
-rw-r--r--drivers/clk/meson/gxbb.h31
-rw-r--r--drivers/clk/meson/meson8b.c (renamed from drivers/clk/meson/meson8b-clkc.c)293
-rw-r--r--drivers/clk/meson/meson8b.h151
-rw-r--r--drivers/firmware/Kconfig1
-rw-r--r--drivers/firmware/Makefile1
-rw-r--r--drivers/firmware/meson/Kconfig9
-rw-r--r--drivers/firmware/meson/Makefile1
-rw-r--r--drivers/firmware/meson/meson_sm.c248
-rw-r--r--drivers/media/rc/meson-ir.c29
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/Kconfig6
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/Makefile2
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c4
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c324
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h8
-rw-r--r--drivers/nvmem/Kconfig10
-rw-r--r--drivers/nvmem/Makefile2
-rw-r--r--drivers/nvmem/meson-efuse.c93
-rw-r--r--drivers/usb/dwc2/platform.c34
-rw-r--r--include/dt-bindings/clock/gxbb-aoclkc.h66
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h16
-rw-r--r--include/dt-bindings/clock/meson8b-clkc.h2
-rw-r--r--include/dt-bindings/reset/gxbb-aoclkc.h66
-rw-r--r--include/linux/firmware/meson/meson_sm.h31
31 files changed, 1766 insertions, 149 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
new file mode 100644
index 000000000000..a55d31b48d6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -0,0 +1,45 @@
1* Amlogic GXBB AO Clock and Reset Unit
2
3The Amlogic GXBB AO clock controller generates and supplies clock to various
4controllers within the Always-On part of the SoC.
5
6Required Properties:
7
8- compatible: should be "amlogic,gxbb-aoclkc"
9- reg: physical base address of the clock controller and length of memory
10 mapped region.
11
12- #clock-cells: should be 1.
13
14Each clock is assigned an identifier and client nodes can use this identifier
15to specify the clock which they consume. All available clocks are defined as
16preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
17used in device tree sources.
18
19- #reset-cells: should be 1.
20
21Each reset is assigned an identifier and client nodes can use this identifier
22to specify the reset which they consume. All available resets are defined as
23preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
24used in device tree sources.
25
26Example: AO Clock controller node:
27
28 clkc_AO: clock-controller@040 {
29 compatible = "amlogic,gxbb-aoclkc";
30 reg = <0x0 0x040 0x0 0x4>;
31 #clock-cells = <1>;
32 #reset-cells = <1>;
33 };
34
35Example: UART controller node that consumes the clock and reset generated
36 by the clock controller:
37
38 uart_AO: serial@4c0 {
39 compatible = "amlogic,meson-uart";
40 reg = <0x4c0 0x14>;
41 interrupts = <0 90 1>;
42 clocks = <&clkc_AO CLKID_AO_UART1>;
43 resets = <&clkc_AO RESET_AO_UART1>;
44 status = "disabled";
45 };
diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
index ec633d74a8a8..89e62ddc69ca 100644
--- a/Documentation/devicetree/bindings/net/meson-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -1,18 +1,32 @@
1* Amlogic Meson DWMAC Ethernet controller 1* Amlogic Meson DWMAC Ethernet controller
2 2
3The device inherits all the properties of the dwmac/stmmac devices 3The device inherits all the properties of the dwmac/stmmac devices
4described in the file net/stmmac.txt with the following changes. 4described in the file stmmac.txt in the current directory with the
5following changes.
5 6
6Required properties: 7Required properties on all platforms:
7 8
8- compatible: should be "amlogic,meson6-dwmac" along with "snps,dwmac" 9- compatible: Depending on the platform this should be one of:
9 and any applicable more detailed version number 10 - "amlogic,meson6-dwmac"
10 described in net/stmmac.txt 11 - "amlogic,meson8b-dwmac"
12 - "amlogic,meson-gxbb-dwmac"
13 Additionally "snps,dwmac" and any applicable more
14 detailed version number described in net/stmmac.txt
15 should be used.
11 16
12- reg: should contain a register range for the dwmac controller and 17- reg: The first register range should be the one of the DWMAC
13 another one for the Amlogic specific configuration 18 controller. The second range is is for the Amlogic specific
19 configuration (for example the PRG_ETHERNET register range
20 on Meson8b and newer)
14 21
15Example: 22Required properties on Meson8b and newer:
23- clock-names: Should contain the following:
24 - "stmmaceth" - see stmmac.txt
25 - "clkin0" - first parent clock of the internal mux
26 - "clkin1" - second parent clock of the internal mux
27
28
29Example for Meson6:
16 30
17 ethmac: ethernet@c9410000 { 31 ethmac: ethernet@c9410000 {
18 compatible = "amlogic,meson6-dwmac", "snps,dwmac"; 32 compatible = "amlogic,meson6-dwmac", "snps,dwmac";
@@ -23,3 +37,18 @@ Example:
23 clocks = <&clk81>; 37 clocks = <&clk81>;
24 clock-names = "stmmaceth"; 38 clock-names = "stmmaceth";
25 } 39 }
40
41Example for GXBB:
42 ethmac: ethernet@c9410000 {
43 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
44 reg = <0x0 0xc9410000 0x0 0x10000>,
45 <0x0 0xc8834540 0x0 0x8>;
46 interrupts = <0 8 1>;
47 interrupt-names = "macirq";
48 clocks = <&clkc CLKID_ETH>,
49 <&clkc CLKID_FCLK_DIV2>,
50 <&clkc CLKID_MPLL2>;
51 clock-names = "stmmaceth", "clkin0", "clkin1";
52 phy-mode = "rgmii";
53 status = "disabled";
54 };
diff --git a/Documentation/devicetree/bindings/phy/meson-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson-usb2-phy.txt
new file mode 100644
index 000000000000..9da5ea234154
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/meson-usb2-phy.txt
@@ -0,0 +1,27 @@
1* Amlogic USB2 PHY
2
3Required properties:
4- compatible: Depending on the platform this should be one of:
5 "amlogic,meson8b-usb2-phy"
6 "amlogic,meson-gxbb-usb2-phy"
7- reg: The base address and length of the registers
8- #phys-cells: should be 0 (see phy-bindings.txt in this directory)
9- clocks: phandle and clock identifier for the phy clocks
10- clock-names: "usb_general" and "usb"
11
12Optional properties:
13- resets: reference to the reset controller
14- phy-supply: see phy-bindings.txt in this directory
15
16
17Example:
18
19usb0_phy: usb_phy@0 {
20 compatible = "amlogic,meson-gxbb-usb2-phy";
21 #phy-cells = <0>;
22 reg = <0x0 0x0 0x0 0x20>;
23 resets = <&reset RESET_USB_OTG>;
24 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
25 clock-names = "usb_general", "usb";
26 phy-supply = <&usb_vbus>;
27};
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 20a68bf2b4e7..2c30a5479069 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -10,6 +10,8 @@ Required properties:
10 - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; 10 - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
11 - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; 11 - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
12 - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; 12 - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
13 - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
14 - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
13 - snps,dwc2: A generic DWC2 USB controller with default parameters. 15 - snps,dwc2: A generic DWC2 USB controller with default parameters.
14- reg : Should contain 1 register range (address and length) 16- reg : Should contain 1 register range (address and length)
15- interrupts : Should contain 1 interrupt 17- interrupts : Should contain 1 interrupt
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 197e40175166..349583405b7c 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,5 +3,5 @@
3# 3#
4 4
5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o 5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o 6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o 7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 53326c32e853..9bb70e7a7d6a 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -98,7 +98,7 @@ struct meson_clk_mpll {
98}; 98};
99 99
100#define MESON_GATE(_name, _reg, _bit) \ 100#define MESON_GATE(_name, _reg, _bit) \
101struct clk_gate gxbb_##_name = { \ 101struct clk_gate _name = { \
102 .reg = (void __iomem *) _reg, \ 102 .reg = (void __iomem *) _reg, \
103 .bit_idx = (_bit), \ 103 .bit_idx = (_bit), \
104 .lock = &clk_lock, \ 104 .lock = &clk_lock, \
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
new file mode 100644
index 000000000000..b45c5fba7e35
--- /dev/null
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -0,0 +1,191 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 BayLibre, SAS.
8 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 * The full GNU General Public License is included in this distribution
22 * in the file called COPYING.
23 *
24 * BSD LICENSE
25 *
26 * Copyright (c) 2016 BayLibre, SAS.
27 * Author: Neil Armstrong <narmstrong@baylibre.com>
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55#include <linux/clk-provider.h>
56#include <linux/of_address.h>
57#include <linux/platform_device.h>
58#include <linux/reset-controller.h>
59#include <linux/init.h>
60#include <dt-bindings/clock/gxbb-aoclkc.h>
61#include <dt-bindings/reset/gxbb-aoclkc.h>
62
63static DEFINE_SPINLOCK(gxbb_aoclk_lock);
64
65struct gxbb_aoclk_reset_controller {
66 struct reset_controller_dev reset;
67 unsigned int *data;
68 void __iomem *base;
69};
70
71static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
72 unsigned long id)
73{
74 struct gxbb_aoclk_reset_controller *reset =
75 container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
76
77 writel(BIT(reset->data[id]), reset->base);
78
79 return 0;
80}
81
82static const struct reset_control_ops gxbb_aoclk_reset_ops = {
83 .reset = gxbb_aoclk_do_reset,
84};
85
86#define GXBB_AO_GATE(_name, _bit) \
87static struct clk_gate _name##_ao = { \
88 .reg = (void __iomem *)0, \
89 .bit_idx = (_bit), \
90 .lock = &gxbb_aoclk_lock, \
91 .hw.init = &(struct clk_init_data) { \
92 .name = #_name "_ao", \
93 .ops = &clk_gate_ops, \
94 .parent_names = (const char *[]){ "clk81" }, \
95 .num_parents = 1, \
96 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
97 }, \
98}
99
100GXBB_AO_GATE(remote, 0);
101GXBB_AO_GATE(i2c_master, 1);
102GXBB_AO_GATE(i2c_slave, 2);
103GXBB_AO_GATE(uart1, 3);
104GXBB_AO_GATE(uart2, 5);
105GXBB_AO_GATE(ir_blaster, 6);
106
107static unsigned int gxbb_aoclk_reset[] = {
108 [RESET_AO_REMOTE] = 16,
109 [RESET_AO_I2C_MASTER] = 18,
110 [RESET_AO_I2C_SLAVE] = 19,
111 [RESET_AO_UART1] = 17,
112 [RESET_AO_UART2] = 22,
113 [RESET_AO_IR_BLASTER] = 23,
114};
115
116static struct clk_gate *gxbb_aoclk_gate[] = {
117 [CLKID_AO_REMOTE] = &remote_ao,
118 [CLKID_AO_I2C_MASTER] = &i2c_master_ao,
119 [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,
120 [CLKID_AO_UART1] = &uart1_ao,
121 [CLKID_AO_UART2] = &uart2_ao,
122 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
123};
124
125static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
126 .hws = {
127 [CLKID_AO_REMOTE] = &remote_ao.hw,
128 [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
129 [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
130 [CLKID_AO_UART1] = &uart1_ao.hw,
131 [CLKID_AO_UART2] = &uart2_ao.hw,
132 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
133 },
134 .num = ARRAY_SIZE(gxbb_aoclk_gate),
135};
136
137static int gxbb_aoclkc_probe(struct platform_device *pdev)
138{
139 struct resource *res;
140 void __iomem *base;
141 int ret, clkid;
142 struct device *dev = &pdev->dev;
143 struct gxbb_aoclk_reset_controller *rstc;
144
145 rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
146 if (!rstc)
147 return -ENOMEM;
148
149 /* Generic clocks */
150 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
151 base = devm_ioremap_resource(dev, res);
152 if (IS_ERR(base))
153 return PTR_ERR(base);
154
155 /* Reset Controller */
156 rstc->base = base;
157 rstc->data = gxbb_aoclk_reset;
158 rstc->reset.ops = &gxbb_aoclk_reset_ops;
159 rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
160 rstc->reset.of_node = dev->of_node;
161 ret = devm_reset_controller_register(dev, &rstc->reset);
162
163 /*
164 * Populate base address and register all clks
165 */
166 for (clkid = 0; clkid < gxbb_aoclk_onecell_data.num; clkid++) {
167 gxbb_aoclk_gate[clkid]->reg = base;
168
169 ret = devm_clk_hw_register(dev,
170 gxbb_aoclk_onecell_data.hws[clkid]);
171 if (ret)
172 return ret;
173 }
174
175 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
176 &gxbb_aoclk_onecell_data);
177}
178
179static const struct of_device_id gxbb_aoclkc_match_table[] = {
180 { .compatible = "amlogic,gxbb-aoclkc" },
181 { }
182};
183
184static struct platform_driver gxbb_aoclkc_driver = {
185 .probe = gxbb_aoclkc_probe,
186 .driver = {
187 .name = "gxbb-aoclkc",
188 .of_match_table = gxbb_aoclkc_match_table,
189 },
190};
191builtin_platform_driver(gxbb_aoclkc_driver);
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index a4c6684b3019..b3bd813a0772 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -565,90 +565,93 @@ static struct clk_gate gxbb_clk81 = {
565}; 565};
566 566
567/* Everything Else (EE) domain gates */ 567/* Everything Else (EE) domain gates */
568static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0); 568static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
569static MESON_GATE(dos, HHI_GCLK_MPEG0, 1); 569static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
570static MESON_GATE(isa, HHI_GCLK_MPEG0, 5); 570static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
571static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6); 571static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
572static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7); 572static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
573static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8); 573static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
574static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9); 574static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
575static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10); 575static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
576static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11); 576static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
577static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12); 577static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
578static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13); 578static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
579static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14); 579static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
580static MESON_GATE(stream, HHI_GCLK_MPEG0, 15); 580static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
581static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16); 581static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
582static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17); 582static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
583static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18); 583static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
584static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); 584static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
585static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23); 585static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
586static MESON_GATE(spi, HHI_GCLK_MPEG0, 30); 586static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
587 587static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
588static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); 588static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
589static MESON_GATE(eth, HHI_GCLK_MPEG1, 3); 589static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
590static MESON_GATE(demux, HHI_GCLK_MPEG1, 4); 590
591static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); 591static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
592static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7); 592static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
593static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8); 593static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
594static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9); 594static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
595static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10); 595static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
596static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11); 596static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
597static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); 597static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
598static MESON_GATE(adc, HHI_GCLK_MPEG1, 13); 598static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
599static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14); 599static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
600static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15); 600static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
601static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16); 601static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
602static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20); 602static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
603static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21); 603static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
604static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22); 604static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
605static MESON_GATE(reset, HHI_GCLK_MPEG1, 23); 605static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
606static MESON_GATE(nand, HHI_GCLK_MPEG1, 24); 606static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
607static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25); 607static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
608static MESON_GATE(usb, HHI_GCLK_MPEG1, 26); 608static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
609static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28); 609static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
610static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); 610static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
611static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30); 611static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
612static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31); 612static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
613 613static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
614static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); 614static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
615static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 615static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
616static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 616
617static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); 617static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
618static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 618static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
619static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 619static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
620static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); 620static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
621static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12); 621static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
622static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15); 622static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
623static MESON_GATE(sana, HHI_GCLK_MPEG2, 22); 623static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
624static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); 624static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
625static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 625static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
626static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); 626static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
627 627static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
628static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); 628static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
629static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); 629static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
630static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); 630
631static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); 631static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
632static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); 632static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
633static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); 633static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
634static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10); 634static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
635static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); 635static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
636static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16); 636static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
637static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20); 637static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
638static MESON_GATE(rng1, HHI_GCLK_OTHER, 21); 638static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
639static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); 639static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
640static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); 640static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
641static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); 641static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
642static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26); 642static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
643static MESON_GATE(edp, HHI_GCLK_OTHER, 31); 643static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
644static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
645static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
646static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
644 647
645/* Always On (AO) domain gates */ 648/* Always On (AO) domain gates */
646 649
647static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0); 650static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
648static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); 651static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
649static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); 652static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
650static MESON_GATE(ao_iface, HHI_GCLK_AO, 3); 653static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
651static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4); 654static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
652 655
653/* Array of all clocks provided by this provider */ 656/* Array of all clocks provided by this provider */
654 657
@@ -748,6 +751,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
748 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 751 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
749 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 752 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
750 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 753 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
754 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
755 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
756 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
751 }, 757 },
752 .num = NR_CLKS, 758 .num = NR_CLKS,
753}; 759};
@@ -847,6 +853,9 @@ static struct clk_gate *gxbb_clk_gates[] = {
847 &gxbb_ao_ahb_bus, 853 &gxbb_ao_ahb_bus,
848 &gxbb_ao_iface, 854 &gxbb_ao_iface,
849 &gxbb_ao_i2c, 855 &gxbb_ao_i2c,
856 &gxbb_emmc_a,
857 &gxbb_emmc_b,
858 &gxbb_emmc_c,
850}; 859};
851 860
852static int gxbb_clkc_probe(struct platform_device *pdev) 861static int gxbb_clkc_probe(struct platform_device *pdev)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index a2adf3448b59..0252939ba58f 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -170,11 +170,11 @@
170 */ 170 */
171#define CLKID_SYS_PLL 0 171#define CLKID_SYS_PLL 0
172/* CLKID_CPUCLK */ 172/* CLKID_CPUCLK */
173#define CLKID_HDMI_PLL 2 173/* CLKID_HDMI_PLL */
174#define CLKID_FIXED_PLL 3 174#define CLKID_FIXED_PLL 3
175#define CLKID_FCLK_DIV2 4 175/* CLKID_FCLK_DIV2 */
176#define CLKID_FCLK_DIV3 5 176/* CLKID_FCLK_DIV3 */
177#define CLKID_FCLK_DIV4 6 177/* CLKID_FCLK_DIV4 */
178#define CLKID_FCLK_DIV5 7 178#define CLKID_FCLK_DIV5 7
179#define CLKID_FCLK_DIV7 8 179#define CLKID_FCLK_DIV7 8
180#define CLKID_GP0_PLL 9 180#define CLKID_GP0_PLL 9
@@ -183,14 +183,14 @@
183/* CLKID_CLK81 */ 183/* CLKID_CLK81 */
184#define CLKID_MPLL0 13 184#define CLKID_MPLL0 13
185#define CLKID_MPLL1 14 185#define CLKID_MPLL1 14
186#define CLKID_MPLL2 15 186/* CLKID_MPLL2 */
187#define CLKID_DDR 16 187#define CLKID_DDR 16
188#define CLKID_DOS 17 188#define CLKID_DOS 17
189#define CLKID_ISA 18 189#define CLKID_ISA 18
190#define CLKID_PL301 19 190#define CLKID_PL301 19
191#define CLKID_PERIPHS 20 191#define CLKID_PERIPHS 20
192#define CLKID_SPICC 21 192#define CLKID_SPICC 21
193#define CLKID_I2C 22 193/* CLKID_I2C */
194#define CLKID_SAR_ADC 23 194#define CLKID_SAR_ADC 23
195#define CLKID_SMART_CARD 24 195#define CLKID_SMART_CARD 24
196#define CLKID_RNG0 25 196#define CLKID_RNG0 25
@@ -202,7 +202,7 @@
202#define CLKID_ABUF 31 202#define CLKID_ABUF 31
203#define CLKID_HIU_IFACE 32 203#define CLKID_HIU_IFACE 32
204#define CLKID_ASSIST_MISC 33 204#define CLKID_ASSIST_MISC 33
205#define CLKID_SPI 34 205/* CLKID_SPI */
206#define CLKID_I2S_SPDIF 35 206#define CLKID_I2S_SPDIF 35
207#define CLKID_ETH 36 207#define CLKID_ETH 36
208#define CLKID_DEMUX 37 208#define CLKID_DEMUX 37
@@ -218,12 +218,12 @@
218#define CLKID_AIU 47 218#define CLKID_AIU 47
219#define CLKID_UART1 48 219#define CLKID_UART1 48
220#define CLKID_G2D 49 220#define CLKID_G2D 49
221#define CLKID_USB0 50 221/* CLKID_USB0 */
222#define CLKID_USB1 51 222/* CLKID_USB1 */
223#define CLKID_RESET 52 223#define CLKID_RESET 52
224#define CLKID_NAND 53 224#define CLKID_NAND 53
225#define CLKID_DOS_PARSER 54 225#define CLKID_DOS_PARSER 54
226#define CLKID_USB 55 226/* CLKID_USB */
227#define CLKID_VDIN1 56 227#define CLKID_VDIN1 56
228#define CLKID_AHB_ARB0 57 228#define CLKID_AHB_ARB0 57
229#define CLKID_EFUSE 58 229#define CLKID_EFUSE 58
@@ -232,8 +232,8 @@
232#define CLKID_AHB_CTRL_BUS 61 232#define CLKID_AHB_CTRL_BUS 61
233#define CLKID_HDMI_INTR_SYNC 62 233#define CLKID_HDMI_INTR_SYNC 62
234#define CLKID_HDMI_PCLK 63 234#define CLKID_HDMI_PCLK 63
235#define CLKID_USB1_DDR_BRIDGE 64 235/* CLKID_USB1_DDR_BRIDGE */
236#define CLKID_USB0_DDR_BRIDGE 65 236/* CLKID_USB0_DDR_BRIDGE */
237#define CLKID_MMC_PCLK 66 237#define CLKID_MMC_PCLK 66
238#define CLKID_DVIN 67 238#define CLKID_DVIN 67
239#define CLKID_UART2 68 239#define CLKID_UART2 68
@@ -261,9 +261,12 @@
261#define CLKID_AO_AHB_SRAM 90 261#define CLKID_AO_AHB_SRAM 90
262#define CLKID_AO_AHB_BUS 91 262#define CLKID_AO_AHB_BUS 91
263#define CLKID_AO_IFACE 92 263#define CLKID_AO_IFACE 92
264#define CLKID_AO_I2C 93 264/* CLKID_AO_I2C */
265/* CLKID_SD_EMMC_A */
266/* CLKID_SD_EMMC_B */
267/* CLKID_SD_EMMC_C */
265 268
266#define NR_CLKS 94 269#define NR_CLKS 97
267 270
268/* include the CLKIDs that have been made part of the stable DT binding */ 271/* include the CLKIDs that have been made part of the stable DT binding */
269#include <dt-bindings/clock/gxbb-clkc.h> 272#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson8b-clkc.c b/drivers/clk/meson/meson8b.c
index 4c9413cdf373..e1d4aa145a03 100644
--- a/drivers/clk/meson/meson8b-clkc.c
+++ b/drivers/clk/meson/meson8b.c
@@ -23,27 +23,11 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/clk-provider.h> 24#include <linux/clk-provider.h>
25#include <linux/of_address.h> 25#include <linux/of_address.h>
26#include <dt-bindings/clock/meson8b-clkc.h>
27#include <linux/platform_device.h> 26#include <linux/platform_device.h>
28#include <linux/init.h> 27#include <linux/init.h>
29 28
30#include "clkc.h" 29#include "clkc.h"
31 30#include "meson8b.h"
32/*
33 * Clock controller register offsets
34 *
35 * Register offsets from the HardKernel[0] data sheet are listed in comment
36 * blocks below. Those offsets must be multiplied by 4 before adding them to
37 * the base address to get the right value
38 *
39 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
40 */
41#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
42#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
43#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
44#define MESON8B_REG_PLL_FIXED 0x0280
45#define MESON8B_REG_PLL_SYS 0x0300
46#define MESON8B_REG_PLL_VID 0x0320
47 31
48static DEFINE_SPINLOCK(clk_lock); 32static DEFINE_SPINLOCK(clk_lock);
49 33
@@ -128,17 +112,17 @@ static struct clk_fixed_rate meson8b_xtal = {
128 112
129static struct meson_clk_pll meson8b_fixed_pll = { 113static struct meson_clk_pll meson8b_fixed_pll = {
130 .m = { 114 .m = {
131 .reg_off = MESON8B_REG_PLL_FIXED, 115 .reg_off = HHI_MPLL_CNTL,
132 .shift = 0, 116 .shift = 0,
133 .width = 9, 117 .width = 9,
134 }, 118 },
135 .n = { 119 .n = {
136 .reg_off = MESON8B_REG_PLL_FIXED, 120 .reg_off = HHI_MPLL_CNTL,
137 .shift = 9, 121 .shift = 9,
138 .width = 5, 122 .width = 5,
139 }, 123 },
140 .od = { 124 .od = {
141 .reg_off = MESON8B_REG_PLL_FIXED, 125 .reg_off = HHI_MPLL_CNTL,
142 .shift = 16, 126 .shift = 16,
143 .width = 2, 127 .width = 2,
144 }, 128 },
@@ -154,17 +138,17 @@ static struct meson_clk_pll meson8b_fixed_pll = {
154 138
155static struct meson_clk_pll meson8b_vid_pll = { 139static struct meson_clk_pll meson8b_vid_pll = {
156 .m = { 140 .m = {
157 .reg_off = MESON8B_REG_PLL_VID, 141 .reg_off = HHI_VID_PLL_CNTL,
158 .shift = 0, 142 .shift = 0,
159 .width = 9, 143 .width = 9,
160 }, 144 },
161 .n = { 145 .n = {
162 .reg_off = MESON8B_REG_PLL_VID, 146 .reg_off = HHI_VID_PLL_CNTL,
163 .shift = 9, 147 .shift = 9,
164 .width = 5, 148 .width = 5,
165 }, 149 },
166 .od = { 150 .od = {
167 .reg_off = MESON8B_REG_PLL_VID, 151 .reg_off = HHI_VID_PLL_CNTL,
168 .shift = 16, 152 .shift = 16,
169 .width = 2, 153 .width = 2,
170 }, 154 },
@@ -180,17 +164,17 @@ static struct meson_clk_pll meson8b_vid_pll = {
180 164
181static struct meson_clk_pll meson8b_sys_pll = { 165static struct meson_clk_pll meson8b_sys_pll = {
182 .m = { 166 .m = {
183 .reg_off = MESON8B_REG_PLL_SYS, 167 .reg_off = HHI_SYS_PLL_CNTL,
184 .shift = 0, 168 .shift = 0,
185 .width = 9, 169 .width = 9,
186 }, 170 },
187 .n = { 171 .n = {
188 .reg_off = MESON8B_REG_PLL_SYS, 172 .reg_off = HHI_SYS_PLL_CNTL,
189 .shift = 9, 173 .shift = 9,
190 .width = 5, 174 .width = 5,
191 }, 175 },
192 .od = { 176 .od = {
193 .reg_off = MESON8B_REG_PLL_SYS, 177 .reg_off = HHI_SYS_PLL_CNTL,
194 .shift = 16, 178 .shift = 16,
195 .width = 2, 179 .width = 2,
196 }, 180 },
@@ -267,7 +251,7 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
267 * forthcoming coordinated clock rates feature 251 * forthcoming coordinated clock rates feature
268 */ 252 */
269static struct meson_clk_cpu meson8b_cpu_clk = { 253static struct meson_clk_cpu meson8b_cpu_clk = {
270 .reg_off = MESON8B_REG_SYS_CPU_CNTL1, 254 .reg_off = HHI_SYS_CPU_CLK_CNTL1,
271 .div_table = cpu_div_table, 255 .div_table = cpu_div_table,
272 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb, 256 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
273 .hw.init = &(struct clk_init_data){ 257 .hw.init = &(struct clk_init_data){
@@ -281,7 +265,7 @@ static struct meson_clk_cpu meson8b_cpu_clk = {
281static u32 mux_table_clk81[] = { 6, 5, 7 }; 265static u32 mux_table_clk81[] = { 6, 5, 7 };
282 266
283struct clk_mux meson8b_mpeg_clk_sel = { 267struct clk_mux meson8b_mpeg_clk_sel = {
284 .reg = (void *)MESON8B_REG_HHI_MPEG, 268 .reg = (void *)HHI_MPEG_CLK_CNTL,
285 .mask = 0x7, 269 .mask = 0x7,
286 .shift = 12, 270 .shift = 12,
287 .flags = CLK_MUX_READ_ONLY, 271 .flags = CLK_MUX_READ_ONLY,
@@ -303,7 +287,7 @@ struct clk_mux meson8b_mpeg_clk_sel = {
303}; 287};
304 288
305struct clk_divider meson8b_mpeg_clk_div = { 289struct clk_divider meson8b_mpeg_clk_div = {
306 .reg = (void *)MESON8B_REG_HHI_MPEG, 290 .reg = (void *)HHI_MPEG_CLK_CNTL,
307 .shift = 0, 291 .shift = 0,
308 .width = 7, 292 .width = 7,
309 .lock = &clk_lock, 293 .lock = &clk_lock,
@@ -317,7 +301,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
317}; 301};
318 302
319struct clk_gate meson8b_clk81 = { 303struct clk_gate meson8b_clk81 = {
320 .reg = (void *)MESON8B_REG_HHI_MPEG, 304 .reg = (void *)HHI_MPEG_CLK_CNTL,
321 .bit_idx = 7, 305 .bit_idx = 7,
322 .lock = &clk_lock, 306 .lock = &clk_lock,
323 .hw.init = &(struct clk_init_data){ 307 .hw.init = &(struct clk_init_data){
@@ -329,6 +313,92 @@ struct clk_gate meson8b_clk81 = {
329 }, 313 },
330}; 314};
331 315
316/* Everything Else (EE) domain gates */
317
318static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
319static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
320static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
321static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
322static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
323static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
324static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
325static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
326static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
327static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
328static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
329static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
330static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
331static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
332static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
333static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
334static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
335static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
336static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
337
338static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
339static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
340static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
341static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
342static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
343static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
344static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
345static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
346static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
347static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
348static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
349static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
350static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
351static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
352static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
353static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
354static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
355static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
356static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
357static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
358static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
359static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
360static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
361static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
362static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
363
364static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
365static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
366static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
367static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
368static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
369static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
370static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
371static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
372static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
373static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
374static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
375static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
376static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
377
378static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
379static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
380static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
381static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
382static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
383static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
384static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
385static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
386static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
387static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
388static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
389static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
390static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
391static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
392static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
393static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
394
395/* Always On (AO) domain gates */
396
397static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
398static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
399static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
400static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
401
332static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 402static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
333 .hws = { 403 .hws = {
334 [CLKID_XTAL] = &meson8b_xtal.hw, 404 [CLKID_XTAL] = &meson8b_xtal.hw,
@@ -344,6 +414,83 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
344 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, 414 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
345 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, 415 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
346 [CLKID_CLK81] = &meson8b_clk81.hw, 416 [CLKID_CLK81] = &meson8b_clk81.hw,
417 [CLKID_DDR] = &meson8b_ddr.hw,
418 [CLKID_DOS] = &meson8b_dos.hw,
419 [CLKID_ISA] = &meson8b_isa.hw,
420 [CLKID_PL301] = &meson8b_pl301.hw,
421 [CLKID_PERIPHS] = &meson8b_periphs.hw,
422 [CLKID_SPICC] = &meson8b_spicc.hw,
423 [CLKID_I2C] = &meson8b_i2c.hw,
424 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
425 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
426 [CLKID_RNG0] = &meson8b_rng0.hw,
427 [CLKID_UART0] = &meson8b_uart0.hw,
428 [CLKID_SDHC] = &meson8b_sdhc.hw,
429 [CLKID_STREAM] = &meson8b_stream.hw,
430 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
431 [CLKID_SDIO] = &meson8b_sdio.hw,
432 [CLKID_ABUF] = &meson8b_abuf.hw,
433 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
434 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
435 [CLKID_SPI] = &meson8b_spi.hw,
436 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
437 [CLKID_ETH] = &meson8b_eth.hw,
438 [CLKID_DEMUX] = &meson8b_demux.hw,
439 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
440 [CLKID_IEC958] = &meson8b_iec958.hw,
441 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
442 [CLKID_AMCLK] = &meson8b_amclk.hw,
443 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
444 [CLKID_MIXER] = &meson8b_mixer.hw,
445 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
446 [CLKID_ADC] = &meson8b_adc.hw,
447 [CLKID_BLKMV] = &meson8b_blkmv.hw,
448 [CLKID_AIU] = &meson8b_aiu.hw,
449 [CLKID_UART1] = &meson8b_uart1.hw,
450 [CLKID_G2D] = &meson8b_g2d.hw,
451 [CLKID_USB0] = &meson8b_usb0.hw,
452 [CLKID_USB1] = &meson8b_usb1.hw,
453 [CLKID_RESET] = &meson8b_reset.hw,
454 [CLKID_NAND] = &meson8b_nand.hw,
455 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
456 [CLKID_USB] = &meson8b_usb.hw,
457 [CLKID_VDIN1] = &meson8b_vdin1.hw,
458 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
459 [CLKID_EFUSE] = &meson8b_efuse.hw,
460 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
461 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
462 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
463 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
464 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
465 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
466 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
467 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
468 [CLKID_DVIN] = &meson8b_dvin.hw,
469 [CLKID_UART2] = &meson8b_uart2.hw,
470 [CLKID_SANA] = &meson8b_sana.hw,
471 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
472 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
473 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
474 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
475 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
476 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
477 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
478 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
479 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_vencp_int.hw,
480 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
481 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
482 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
483 [CLKID_ENC480P] = &meson8b_enc480p.hw,
484 [CLKID_RNG1] = &meson8b_rng1.hw,
485 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
486 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
487 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
488 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
489 [CLKID_EDP] = &meson8b_edp.hw,
490 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
491 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
492 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
493 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
347 }, 494 },
348 .num = CLK_NR_CLKS, 495 .num = CLK_NR_CLKS,
349}; 496};
@@ -354,6 +501,87 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = {
354 &meson8b_sys_pll, 501 &meson8b_sys_pll,
355}; 502};
356 503
504static struct clk_gate *meson8b_clk_gates[] = {
505 &meson8b_clk81,
506 &meson8b_ddr,
507 &meson8b_dos,
508 &meson8b_isa,
509 &meson8b_pl301,
510 &meson8b_periphs,
511 &meson8b_spicc,
512 &meson8b_i2c,
513 &meson8b_sar_adc,
514 &meson8b_smart_card,
515 &meson8b_rng0,
516 &meson8b_uart0,
517 &meson8b_sdhc,
518 &meson8b_stream,
519 &meson8b_async_fifo,
520 &meson8b_sdio,
521 &meson8b_abuf,
522 &meson8b_hiu_iface,
523 &meson8b_assist_misc,
524 &meson8b_spi,
525 &meson8b_i2s_spdif,
526 &meson8b_eth,
527 &meson8b_demux,
528 &meson8b_aiu_glue,
529 &meson8b_iec958,
530 &meson8b_i2s_out,
531 &meson8b_amclk,
532 &meson8b_aififo2,
533 &meson8b_mixer,
534 &meson8b_mixer_iface,
535 &meson8b_adc,
536 &meson8b_blkmv,
537 &meson8b_aiu,
538 &meson8b_uart1,
539 &meson8b_g2d,
540 &meson8b_usb0,
541 &meson8b_usb1,
542 &meson8b_reset,
543 &meson8b_nand,
544 &meson8b_dos_parser,
545 &meson8b_usb,
546 &meson8b_vdin1,
547 &meson8b_ahb_arb0,
548 &meson8b_efuse,
549 &meson8b_boot_rom,
550 &meson8b_ahb_data_bus,
551 &meson8b_ahb_ctrl_bus,
552 &meson8b_hdmi_intr_sync,
553 &meson8b_hdmi_pclk,
554 &meson8b_usb1_ddr_bridge,
555 &meson8b_usb0_ddr_bridge,
556 &meson8b_mmc_pclk,
557 &meson8b_dvin,
558 &meson8b_uart2,
559 &meson8b_sana,
560 &meson8b_vpu_intr,
561 &meson8b_sec_ahb_ahb3_bridge,
562 &meson8b_clk81_a9,
563 &meson8b_vclk2_venci0,
564 &meson8b_vclk2_venci1,
565 &meson8b_vclk2_vencp0,
566 &meson8b_vclk2_vencp1,
567 &meson8b_gclk_venci_int,
568 &meson8b_gclk_vencp_int,
569 &meson8b_dac_clk,
570 &meson8b_aoclk_gate,
571 &meson8b_iec958_gate,
572 &meson8b_enc480p,
573 &meson8b_rng1,
574 &meson8b_gclk_vencl_int,
575 &meson8b_vclk2_venclmcc,
576 &meson8b_vclk2_vencl,
577 &meson8b_vclk2_other,
578 &meson8b_edp,
579 &meson8b_ao_media_cpu,
580 &meson8b_ao_ahb_sram,
581 &meson8b_ao_ahb_bus,
582 &meson8b_ao_iface,
583};
584
357static int meson8b_clkc_probe(struct platform_device *pdev) 585static int meson8b_clkc_probe(struct platform_device *pdev)
358{ 586{
359 void __iomem *clk_base; 587 void __iomem *clk_base;
@@ -381,6 +609,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
381 meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; 609 meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
382 meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg; 610 meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
383 611
612 /* Populate base address for gates */
613 for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
614 meson8b_clk_gates[i]->reg = clk_base +
615 (u32)meson8b_clk_gates[i]->reg;
616
384 /* 617 /*
385 * register all clks 618 * register all clks
386 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 619 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
new file mode 100644
index 000000000000..010e9582888d
--- /dev/null
+++ b/drivers/clk/meson/meson8b.h
@@ -0,0 +1,151 @@
1/*
2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * Copyright (c) 2016 BayLibre, Inc.
6 * Michael Turquette <mturquette@baylibre.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __MESON8B_H
22#define __MESON8B_H
23
24/*
25 * Clock controller register offsets
26 *
27 * Register offsets from the HardKernel[0] data sheet are listed in comment
28 * blocks below. Those offsets must be multiplied by 4 before adding them to
29 * the base address to get the right value
30 *
31 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
32 */
33#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
34#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
35#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
36#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
37#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
38#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
39#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
40#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
41#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
42#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
43
44/*
45 * CLKID index values
46 *
47 * These indices are entirely contrived and do not map onto the hardware.
48 * Migrate them out of this header and into the DT header file when they need
49 * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
50 */
51
52/* CLKID_UNUSED */
53/* CLKID_XTAL */
54/* CLKID_PLL_FIXED */
55/* CLKID_PLL_VID */
56/* CLKID_PLL_SYS */
57/* CLKID_FCLK_DIV2 */
58/* CLKID_FCLK_DIV3 */
59/* CLKID_FCLK_DIV4 */
60/* CLKID_FCLK_DIV5 */
61/* CLKID_FCLK_DIV7 */
62/* CLKID_CLK81 */
63/* CLKID_MALI */
64/* CLKID_CPUCLK */
65/* CLKID_ZERO */
66/* CLKID_MPEG_SEL */
67/* CLKID_MPEG_DIV */
68#define CLKID_DDR 16
69#define CLKID_DOS 17
70#define CLKID_ISA 18
71#define CLKID_PL301 19
72#define CLKID_PERIPHS 20
73#define CLKID_SPICC 21
74#define CLKID_I2C 22
75#define CLKID_SAR_ADC 23
76#define CLKID_SMART_CARD 24
77#define CLKID_RNG0 25
78#define CLKID_UART0 26
79#define CLKID_SDHC 27
80#define CLKID_STREAM 28
81#define CLKID_ASYNC_FIFO 29
82#define CLKID_SDIO 30
83#define CLKID_ABUF 31
84#define CLKID_HIU_IFACE 32
85#define CLKID_ASSIST_MISC 33
86#define CLKID_SPI 34
87#define CLKID_I2S_SPDIF 35
88#define CLKID_ETH 36
89#define CLKID_DEMUX 37
90#define CLKID_AIU_GLUE 38
91#define CLKID_IEC958 39
92#define CLKID_I2S_OUT 40
93#define CLKID_AMCLK 41
94#define CLKID_AIFIFO2 42
95#define CLKID_MIXER 43
96#define CLKID_MIXER_IFACE 44
97#define CLKID_ADC 45
98#define CLKID_BLKMV 46
99#define CLKID_AIU 47
100#define CLKID_UART1 48
101#define CLKID_G2D 49
102#define CLKID_USB0 50
103#define CLKID_USB1 51
104#define CLKID_RESET 52
105#define CLKID_NAND 53
106#define CLKID_DOS_PARSER 54
107#define CLKID_USB 55
108#define CLKID_VDIN1 56
109#define CLKID_AHB_ARB0 57
110#define CLKID_EFUSE 58
111#define CLKID_BOOT_ROM 59
112#define CLKID_AHB_DATA_BUS 60
113#define CLKID_AHB_CTRL_BUS 61
114#define CLKID_HDMI_INTR_SYNC 62
115#define CLKID_HDMI_PCLK 63
116#define CLKID_USB1_DDR_BRIDGE 64
117#define CLKID_USB0_DDR_BRIDGE 65
118#define CLKID_MMC_PCLK 66
119#define CLKID_DVIN 67
120#define CLKID_UART2 68
121#define CLKID_SANA 69
122#define CLKID_VPU_INTR 70
123#define CLKID_SEC_AHB_AHB3_BRIDGE 71
124#define CLKID_CLK81_A9 72
125#define CLKID_VCLK2_VENCI0 73
126#define CLKID_VCLK2_VENCI1 74
127#define CLKID_VCLK2_VENCP0 75
128#define CLKID_VCLK2_VENCP1 76
129#define CLKID_GCLK_VENCI_INT 77
130#define CLKID_GCLK_VENCP_INT 78
131#define CLKID_DAC_CLK 79
132#define CLKID_AOCLK_GATE 80
133#define CLKID_IEC958_GATE 81
134#define CLKID_ENC480P 82
135#define CLKID_RNG1 83
136#define CLKID_GCLK_VENCL_INT 84
137#define CLKID_VCLK2_VENCLMCC 85
138#define CLKID_VCLK2_VENCL 86
139#define CLKID_VCLK2_OTHER 87
140#define CLKID_EDP 88
141#define CLKID_AO_MEDIA_CPU 89
142#define CLKID_AO_AHB_SRAM 90
143#define CLKID_AO_AHB_BUS 91
144#define CLKID_AO_IFACE 92
145
146#define CLK_NR_CLKS 93
147
148/* include the CLKIDs that have been made part of the stable DT binding */
149#include <dt-bindings/clock/meson8b-clkc.h>
150
151#endif /* __MESON8B_H */
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 0e22f241403b..bca172d42c74 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -209,5 +209,6 @@ config HAVE_ARM_SMCCC
209source "drivers/firmware/broadcom/Kconfig" 209source "drivers/firmware/broadcom/Kconfig"
210source "drivers/firmware/google/Kconfig" 210source "drivers/firmware/google/Kconfig"
211source "drivers/firmware/efi/Kconfig" 211source "drivers/firmware/efi/Kconfig"
212source "drivers/firmware/meson/Kconfig"
212 213
213endmenu 214endmenu
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 44a59dcfc398..898ac41fa8b3 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o
22CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a 22CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a
23 23
24obj-y += broadcom/ 24obj-y += broadcom/
25obj-y += meson/
25obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ 26obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
26obj-$(CONFIG_EFI) += efi/ 27obj-$(CONFIG_EFI) += efi/
27obj-$(CONFIG_UEFI_CPER) += efi/ 28obj-$(CONFIG_UEFI_CPER) += efi/
diff --git a/drivers/firmware/meson/Kconfig b/drivers/firmware/meson/Kconfig
new file mode 100644
index 000000000000..170d7e8bcdfb
--- /dev/null
+++ b/drivers/firmware/meson/Kconfig
@@ -0,0 +1,9 @@
1#
2# Amlogic Secure Monitor driver
3#
4config MESON_SM
5 bool
6 default ARCH_MESON
7 depends on ARM64_4K_PAGES
8 help
9 Say y here to enable the Amlogic secure monitor driver
diff --git a/drivers/firmware/meson/Makefile b/drivers/firmware/meson/Makefile
new file mode 100644
index 000000000000..9ab3884f96bc
--- /dev/null
+++ b/drivers/firmware/meson/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_MESON_SM) += meson_sm.o
diff --git a/drivers/firmware/meson/meson_sm.c b/drivers/firmware/meson/meson_sm.c
new file mode 100644
index 000000000000..b0d254930ed3
--- /dev/null
+++ b/drivers/firmware/meson/meson_sm.c
@@ -0,0 +1,248 @@
1/*
2 * Amlogic Secure Monitor driver
3 *
4 * Copyright (C) 2016 Endless Mobile, Inc.
5 * Author: Carlo Caione <carlo@endlessm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
13 */
14
15#define pr_fmt(fmt) "meson-sm: " fmt
16
17#include <linux/arm-smccc.h>
18#include <linux/bug.h>
19#include <linux/io.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/printk.h>
23#include <linux/types.h>
24#include <linux/sizes.h>
25
26#include <linux/firmware/meson/meson_sm.h>
27
28struct meson_sm_cmd {
29 unsigned int index;
30 u32 smc_id;
31};
32#define CMD(d, s) { .index = (d), .smc_id = (s), }
33
34struct meson_sm_chip {
35 unsigned int shmem_size;
36 u32 cmd_shmem_in_base;
37 u32 cmd_shmem_out_base;
38 struct meson_sm_cmd cmd[];
39};
40
41struct meson_sm_chip gxbb_chip = {
42 .shmem_size = SZ_4K,
43 .cmd_shmem_in_base = 0x82000020,
44 .cmd_shmem_out_base = 0x82000021,
45 .cmd = {
46 CMD(SM_EFUSE_READ, 0x82000030),
47 CMD(SM_EFUSE_WRITE, 0x82000031),
48 CMD(SM_EFUSE_USER_MAX, 0x82000033),
49 { /* sentinel */ },
50 },
51};
52
53struct meson_sm_firmware {
54 const struct meson_sm_chip *chip;
55 void __iomem *sm_shmem_in_base;
56 void __iomem *sm_shmem_out_base;
57};
58
59static struct meson_sm_firmware fw;
60
61static u32 meson_sm_get_cmd(const struct meson_sm_chip *chip,
62 unsigned int cmd_index)
63{
64 const struct meson_sm_cmd *cmd = chip->cmd;
65
66 while (cmd->smc_id && cmd->index != cmd_index)
67 cmd++;
68
69 return cmd->smc_id;
70}
71
72static u32 __meson_sm_call(u32 cmd, u32 arg0, u32 arg1, u32 arg2,
73 u32 arg3, u32 arg4)
74{
75 struct arm_smccc_res res;
76
77 arm_smccc_smc(cmd, arg0, arg1, arg2, arg3, arg4, 0, 0, &res);
78 return res.a0;
79}
80
81static void __iomem *meson_sm_map_shmem(u32 cmd_shmem, unsigned int size)
82{
83 u32 sm_phy_base;
84
85 sm_phy_base = __meson_sm_call(cmd_shmem, 0, 0, 0, 0, 0);
86 if (!sm_phy_base)
87 return 0;
88
89 return ioremap_cache(sm_phy_base, size);
90}
91
92/**
93 * meson_sm_call - generic SMC32 call to the secure-monitor
94 *
95 * @cmd_index: Index of the SMC32 function ID
96 * @ret: Returned value
97 * @arg0: SMC32 Argument 0
98 * @arg1: SMC32 Argument 1
99 * @arg2: SMC32 Argument 2
100 * @arg3: SMC32 Argument 3
101 * @arg4: SMC32 Argument 4
102 *
103 * Return: 0 on success, a negative value on error
104 */
105int meson_sm_call(unsigned int cmd_index, u32 *ret, u32 arg0,
106 u32 arg1, u32 arg2, u32 arg3, u32 arg4)
107{
108 u32 cmd, lret;
109
110 if (!fw.chip)
111 return -ENOENT;
112
113 cmd = meson_sm_get_cmd(fw.chip, cmd_index);
114 if (!cmd)
115 return -EINVAL;
116
117 lret = __meson_sm_call(cmd, arg0, arg1, arg2, arg3, arg4);
118
119 if (ret)
120 *ret = lret;
121
122 return 0;
123}
124EXPORT_SYMBOL(meson_sm_call);
125
126/**
127 * meson_sm_call_read - retrieve data from secure-monitor
128 *
129 * @buffer: Buffer to store the retrieved data
130 * @cmd_index: Index of the SMC32 function ID
131 * @arg0: SMC32 Argument 0
132 * @arg1: SMC32 Argument 1
133 * @arg2: SMC32 Argument 2
134 * @arg3: SMC32 Argument 3
135 * @arg4: SMC32 Argument 4
136 *
137 * Return: size of read data on success, a negative value on error
138 */
139int meson_sm_call_read(void *buffer, unsigned int cmd_index, u32 arg0,
140 u32 arg1, u32 arg2, u32 arg3, u32 arg4)
141{
142 u32 size;
143
144 if (!fw.chip)
145 return -ENOENT;
146
147 if (!fw.chip->cmd_shmem_out_base)
148 return -EINVAL;
149
150 if (meson_sm_call(cmd_index, &size, arg0, arg1, arg2, arg3, arg4) < 0)
151 return -EINVAL;
152
153 if (!size || size > fw.chip->shmem_size)
154 return -EINVAL;
155
156 if (buffer)
157 memcpy(buffer, fw.sm_shmem_out_base, size);
158
159 return size;
160}
161EXPORT_SYMBOL(meson_sm_call_read);
162
163/**
164 * meson_sm_call_write - send data to secure-monitor
165 *
166 * @buffer: Buffer containing data to send
167 * @size: Size of the data to send
168 * @cmd_index: Index of the SMC32 function ID
169 * @arg0: SMC32 Argument 0
170 * @arg1: SMC32 Argument 1
171 * @arg2: SMC32 Argument 2
172 * @arg3: SMC32 Argument 3
173 * @arg4: SMC32 Argument 4
174 *
175 * Return: size of sent data on success, a negative value on error
176 */
177int meson_sm_call_write(void *buffer, unsigned int size, unsigned int cmd_index,
178 u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4)
179{
180 u32 written;
181
182 if (!fw.chip)
183 return -ENOENT;
184
185 if (size > fw.chip->shmem_size)
186 return -EINVAL;
187
188 if (!fw.chip->cmd_shmem_in_base)
189 return -EINVAL;
190
191 memcpy(fw.sm_shmem_in_base, buffer, size);
192
193 if (meson_sm_call(cmd_index, &written, arg0, arg1, arg2, arg3, arg4) < 0)
194 return -EINVAL;
195
196 if (!written)
197 return -EINVAL;
198
199 return written;
200}
201EXPORT_SYMBOL(meson_sm_call_write);
202
203static const struct of_device_id meson_sm_ids[] = {
204 { .compatible = "amlogic,meson-gxbb-sm", .data = &gxbb_chip },
205 { /* sentinel */ },
206};
207
208int __init meson_sm_init(void)
209{
210 const struct meson_sm_chip *chip;
211 const struct of_device_id *matched_np;
212 struct device_node *np;
213
214 np = of_find_matching_node_and_match(NULL, meson_sm_ids, &matched_np);
215 if (!np)
216 return -ENODEV;
217
218 chip = matched_np->data;
219 if (!chip) {
220 pr_err("unable to setup secure-monitor data\n");
221 goto out;
222 }
223
224 if (chip->cmd_shmem_in_base) {
225 fw.sm_shmem_in_base = meson_sm_map_shmem(chip->cmd_shmem_in_base,
226 chip->shmem_size);
227 if (WARN_ON(!fw.sm_shmem_in_base))
228 goto out;
229 }
230
231 if (chip->cmd_shmem_out_base) {
232 fw.sm_shmem_out_base = meson_sm_map_shmem(chip->cmd_shmem_out_base,
233 chip->shmem_size);
234 if (WARN_ON(!fw.sm_shmem_out_base))
235 goto out_in_base;
236 }
237
238 fw.chip = chip;
239 pr_info("secure-monitor enabled\n");
240
241 return 0;
242
243out_in_base:
244 iounmap(fw.sm_shmem_in_base);
245out:
246 return -EINVAL;
247}
248device_initcall(meson_sm_init);
diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
index fcc3b82d1454..003fff07ade2 100644
--- a/drivers/media/rc/meson-ir.c
+++ b/drivers/media/rc/meson-ir.c
@@ -24,6 +24,7 @@
24 24
25#define DRIVER_NAME "meson-ir" 25#define DRIVER_NAME "meson-ir"
26 26
27/* valid on all Meson platforms */
27#define IR_DEC_LDR_ACTIVE 0x00 28#define IR_DEC_LDR_ACTIVE 0x00
28#define IR_DEC_LDR_IDLE 0x04 29#define IR_DEC_LDR_IDLE 0x04
29#define IR_DEC_LDR_REPEAT 0x08 30#define IR_DEC_LDR_REPEAT 0x08
@@ -32,12 +33,21 @@
32#define IR_DEC_FRAME 0x14 33#define IR_DEC_FRAME 0x14
33#define IR_DEC_STATUS 0x18 34#define IR_DEC_STATUS 0x18
34#define IR_DEC_REG1 0x1c 35#define IR_DEC_REG1 0x1c
36/* only available on Meson 8b and newer */
37#define IR_DEC_REG2 0x20
35 38
36#define REG0_RATE_MASK (BIT(11) - 1) 39#define REG0_RATE_MASK (BIT(11) - 1)
37 40
38#define REG1_MODE_MASK (BIT(7) | BIT(8)) 41#define DECODE_MODE_NEC 0x0
39#define REG1_MODE_NEC (0 << 7) 42#define DECODE_MODE_RAW 0x2
40#define REG1_MODE_GENERAL (2 << 7) 43
44/* Meson 6b uses REG1 to configure the mode */
45#define REG1_MODE_MASK GENMASK(8, 7)
46#define REG1_MODE_SHIFT 7
47
48/* Meson 8b / GXBB use REG2 to configure the mode */
49#define REG2_MODE_MASK GENMASK(3, 0)
50#define REG2_MODE_SHIFT 0
41 51
42#define REG1_TIME_IV_SHIFT 16 52#define REG1_TIME_IV_SHIFT 16
43#define REG1_TIME_IV_MASK ((BIT(13) - 1) << REG1_TIME_IV_SHIFT) 53#define REG1_TIME_IV_MASK ((BIT(13) - 1) << REG1_TIME_IV_SHIFT)
@@ -158,8 +168,15 @@ static int meson_ir_probe(struct platform_device *pdev)
158 /* Reset the decoder */ 168 /* Reset the decoder */
159 meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET); 169 meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET);
160 meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0); 170 meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0);
161 /* Set general operation mode */ 171
162 meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK, REG1_MODE_GENERAL); 172 /* Set general operation mode (= raw/software decoding) */
173 if (of_device_is_compatible(node, "amlogic,meson6-ir"))
174 meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
175 DECODE_MODE_RAW << REG1_MODE_SHIFT);
176 else
177 meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
178 DECODE_MODE_RAW << REG2_MODE_SHIFT);
179
163 /* Set rate */ 180 /* Set rate */
164 meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1); 181 meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1);
165 /* IRQ on rising and falling edges */ 182 /* IRQ on rising and falling edges */
@@ -197,6 +214,8 @@ static int meson_ir_remove(struct platform_device *pdev)
197 214
198static const struct of_device_id meson_ir_match[] = { 215static const struct of_device_id meson_ir_match[] = {
199 { .compatible = "amlogic,meson6-ir" }, 216 { .compatible = "amlogic,meson6-ir" },
217 { .compatible = "amlogic,meson8b-ir" },
218 { .compatible = "amlogic,meson-gxbb-ir" },
200 { }, 219 { },
201}; 220};
202 221
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 8f06a6621ab1..54de17529c97 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -61,13 +61,13 @@ config DWMAC_LPC18XX
61config DWMAC_MESON 61config DWMAC_MESON
62 tristate "Amlogic Meson dwmac support" 62 tristate "Amlogic Meson dwmac support"
63 default ARCH_MESON 63 default ARCH_MESON
64 depends on OF && (ARCH_MESON || COMPILE_TEST) 64 depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST)
65 help 65 help
66 Support for Ethernet controller on Amlogic Meson SoCs. 66 Support for Ethernet controller on Amlogic Meson SoCs.
67 67
68 This selects the Amlogic Meson SoC glue layer support for 68 This selects the Amlogic Meson SoC glue layer support for
69 the stmmac device driver. This driver is used for Meson6 and 69 the stmmac device driver. This driver is used for Meson6,
70 Meson8 SoCs. 70 Meson8, Meson8b and GXBB SoCs.
71 71
72config DWMAC_ROCKCHIP 72config DWMAC_ROCKCHIP
73 tristate "Rockchip dwmac support" 73 tristate "Rockchip dwmac support"
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 44b630cd1755..f77edb9c2fa9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -9,7 +9,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
9obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o 9obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
10obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o 10obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o
11obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o 11obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o
12obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o 12obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
13obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o 13obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
14obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o 14obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
15obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o 15obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
index c1bac1912b37..309d99536a2c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Amlogic Meson DWMAC glue layer 2 * Amlogic Meson6 and Meson8 DWMAC glue layer
3 * 3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 * 5 *
@@ -96,5 +96,5 @@ static struct platform_driver meson6_dwmac_driver = {
96module_platform_driver(meson6_dwmac_driver); 96module_platform_driver(meson6_dwmac_driver);
97 97
98MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); 98MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
99MODULE_DESCRIPTION("Amlogic Meson DWMAC glue layer"); 99MODULE_DESCRIPTION("Amlogic Meson6 and Meson8 DWMAC glue layer");
100MODULE_LICENSE("GPL v2"); 100MODULE_LICENSE("GPL v2");
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
new file mode 100644
index 000000000000..250e4ceafc8d
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -0,0 +1,324 @@
1/*
2 * Amlogic Meson8b and GXBB DWMAC glue layer
3 *
4 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/device.h>
17#include <linux/ethtool.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/module.h>
21#include <linux/of_net.h>
22#include <linux/mfd/syscon.h>
23#include <linux/platform_device.h>
24#include <linux/stmmac.h>
25
26#include "stmmac_platform.h"
27
28#define PRG_ETH0 0x0
29
30#define PRG_ETH0_RGMII_MODE BIT(0)
31
32/* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
33#define PRG_ETH0_CLK_M250_SEL_SHIFT 4
34#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
35
36#define PRG_ETH0_TXDLY_SHIFT 5
37#define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)
38#define PRG_ETH0_TXDLY_OFF (0x0 << PRG_ETH0_TXDLY_SHIFT)
39#define PRG_ETH0_TXDLY_QUARTER (0x1 << PRG_ETH0_TXDLY_SHIFT)
40#define PRG_ETH0_TXDLY_HALF (0x2 << PRG_ETH0_TXDLY_SHIFT)
41#define PRG_ETH0_TXDLY_THREE_QUARTERS (0x3 << PRG_ETH0_TXDLY_SHIFT)
42
43/* divider for the result of m250_sel */
44#define PRG_ETH0_CLK_M250_DIV_SHIFT 7
45#define PRG_ETH0_CLK_M250_DIV_WIDTH 3
46
47/* divides the result of m25_sel by either 5 (bit unset) or 10 (bit set) */
48#define PRG_ETH0_CLK_M25_DIV_SHIFT 10
49#define PRG_ETH0_CLK_M25_DIV_WIDTH 1
50
51#define PRG_ETH0_INVERTED_RMII_CLK BIT(11)
52#define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12)
53
54#define MUX_CLK_NUM_PARENTS 2
55
56struct meson8b_dwmac {
57 struct platform_device *pdev;
58
59 void __iomem *regs;
60
61 phy_interface_t phy_mode;
62
63 struct clk_mux m250_mux;
64 struct clk *m250_mux_clk;
65 struct clk *m250_mux_parent[MUX_CLK_NUM_PARENTS];
66
67 struct clk_divider m250_div;
68 struct clk *m250_div_clk;
69
70 struct clk_divider m25_div;
71 struct clk *m25_div_clk;
72};
73
74static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
75 u32 mask, u32 value)
76{
77 u32 data;
78
79 data = readl(dwmac->regs + reg);
80 data &= ~mask;
81 data |= (value & mask);
82
83 writel(data, dwmac->regs + reg);
84}
85
86static int meson8b_init_clk(struct meson8b_dwmac *dwmac)
87{
88 struct clk_init_data init;
89 int i, ret;
90 struct device *dev = &dwmac->pdev->dev;
91 char clk_name[32];
92 const char *clk_div_parents[1];
93 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
94 static struct clk_div_table clk_25m_div_table[] = {
95 { .val = 0, .div = 5 },
96 { .val = 1, .div = 10 },
97 { /* sentinel */ },
98 };
99
100 /* get the mux parents from DT */
101 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
102 char name[16];
103
104 snprintf(name, sizeof(name), "clkin%d", i);
105 dwmac->m250_mux_parent[i] = devm_clk_get(dev, name);
106 if (IS_ERR(dwmac->m250_mux_parent[i])) {
107 ret = PTR_ERR(dwmac->m250_mux_parent[i]);
108 if (ret != -EPROBE_DEFER)
109 dev_err(dev, "Missing clock %s\n", name);
110 return ret;
111 }
112
113 mux_parent_names[i] =
114 __clk_get_name(dwmac->m250_mux_parent[i]);
115 }
116
117 /* create the m250_mux */
118 snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev));
119 init.name = clk_name;
120 init.ops = &clk_mux_ops;
121 init.flags = 0;
122 init.parent_names = mux_parent_names;
123 init.num_parents = MUX_CLK_NUM_PARENTS;
124
125 dwmac->m250_mux.reg = dwmac->regs + PRG_ETH0;
126 dwmac->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
127 dwmac->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK;
128 dwmac->m250_mux.flags = 0;
129 dwmac->m250_mux.table = NULL;
130 dwmac->m250_mux.hw.init = &init;
131
132 dwmac->m250_mux_clk = devm_clk_register(dev, &dwmac->m250_mux.hw);
133 if (WARN_ON(IS_ERR(dwmac->m250_mux_clk)))
134 return PTR_ERR(dwmac->m250_mux_clk);
135
136 /* create the m250_div */
137 snprintf(clk_name, sizeof(clk_name), "%s#m250_div", dev_name(dev));
138 init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL);
139 init.ops = &clk_divider_ops;
140 init.flags = CLK_SET_RATE_PARENT;
141 clk_div_parents[0] = __clk_get_name(dwmac->m250_mux_clk);
142 init.parent_names = clk_div_parents;
143 init.num_parents = ARRAY_SIZE(clk_div_parents);
144
145 dwmac->m250_div.reg = dwmac->regs + PRG_ETH0;
146 dwmac->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
147 dwmac->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
148 dwmac->m250_div.hw.init = &init;
149 dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
150
151 dwmac->m250_div_clk = devm_clk_register(dev, &dwmac->m250_div.hw);
152 if (WARN_ON(IS_ERR(dwmac->m250_div_clk)))
153 return PTR_ERR(dwmac->m250_div_clk);
154
155 /* create the m25_div */
156 snprintf(clk_name, sizeof(clk_name), "%s#m25_div", dev_name(dev));
157 init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL);
158 init.ops = &clk_divider_ops;
159 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
160 clk_div_parents[0] = __clk_get_name(dwmac->m250_div_clk);
161 init.parent_names = clk_div_parents;
162 init.num_parents = ARRAY_SIZE(clk_div_parents);
163
164 dwmac->m25_div.reg = dwmac->regs + PRG_ETH0;
165 dwmac->m25_div.shift = PRG_ETH0_CLK_M25_DIV_SHIFT;
166 dwmac->m25_div.width = PRG_ETH0_CLK_M25_DIV_WIDTH;
167 dwmac->m25_div.table = clk_25m_div_table;
168 dwmac->m25_div.hw.init = &init;
169 dwmac->m25_div.flags = CLK_DIVIDER_ALLOW_ZERO;
170
171 dwmac->m25_div_clk = devm_clk_register(dev, &dwmac->m25_div.hw);
172 if (WARN_ON(IS_ERR(dwmac->m25_div_clk)))
173 return PTR_ERR(dwmac->m25_div_clk);
174
175 return 0;
176}
177
178static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
179{
180 int ret;
181 unsigned long clk_rate;
182
183 switch (dwmac->phy_mode) {
184 case PHY_INTERFACE_MODE_RGMII:
185 case PHY_INTERFACE_MODE_RGMII_ID:
186 case PHY_INTERFACE_MODE_RGMII_RXID:
187 case PHY_INTERFACE_MODE_RGMII_TXID:
188 /* Generate a 25MHz clock for the PHY */
189 clk_rate = 25 * 1000 * 1000;
190
191 /* enable RGMII mode */
192 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
193 PRG_ETH0_RGMII_MODE);
194
195 /* only relevant for RMII mode -> disable in RGMII mode */
196 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
197 PRG_ETH0_INVERTED_RMII_CLK, 0);
198
199 /* TX clock delay - all known boards use a 1/4 cycle delay */
200 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
201 PRG_ETH0_TXDLY_QUARTER);
202 break;
203
204 case PHY_INTERFACE_MODE_RMII:
205 /* Use the rate of the mux clock for the internal RMII PHY */
206 clk_rate = clk_get_rate(dwmac->m250_mux_clk);
207
208 /* disable RGMII mode -> enables RMII mode */
209 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
210 0);
211
212 /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
213 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
214 PRG_ETH0_INVERTED_RMII_CLK,
215 PRG_ETH0_INVERTED_RMII_CLK);
216
217 /* TX clock delay cannot be configured in RMII mode */
218 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
219 0);
220
221 break;
222
223 default:
224 dev_err(&dwmac->pdev->dev, "unsupported phy-mode %s\n",
225 phy_modes(dwmac->phy_mode));
226 return -EINVAL;
227 }
228
229 ret = clk_prepare_enable(dwmac->m25_div_clk);
230 if (ret) {
231 dev_err(&dwmac->pdev->dev, "failed to enable the PHY clock\n");
232 return ret;
233 }
234
235 ret = clk_set_rate(dwmac->m25_div_clk, clk_rate);
236 if (ret) {
237 clk_disable_unprepare(dwmac->m25_div_clk);
238
239 dev_err(&dwmac->pdev->dev, "failed to set PHY clock\n");
240 return ret;
241 }
242
243 /* enable TX_CLK and PHY_REF_CLK generator */
244 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
245 PRG_ETH0_TX_AND_PHY_REF_CLK);
246
247 return 0;
248}
249
250static int meson8b_dwmac_probe(struct platform_device *pdev)
251{
252 struct plat_stmmacenet_data *plat_dat;
253 struct stmmac_resources stmmac_res;
254 struct resource *res;
255 struct meson8b_dwmac *dwmac;
256 int ret;
257
258 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
259 if (ret)
260 return ret;
261
262 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
263 if (IS_ERR(plat_dat))
264 return PTR_ERR(plat_dat);
265
266 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
267 if (!dwmac)
268 return -ENOMEM;
269
270 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
271 dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
272 if (IS_ERR(dwmac->regs))
273 return PTR_ERR(dwmac->regs);
274
275 dwmac->pdev = pdev;
276 dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node);
277 if (dwmac->phy_mode < 0) {
278 dev_err(&pdev->dev, "missing phy-mode property\n");
279 return -EINVAL;
280 }
281
282 ret = meson8b_init_clk(dwmac);
283 if (ret)
284 return ret;
285
286 ret = meson8b_init_prg_eth(dwmac);
287 if (ret)
288 return ret;
289
290 plat_dat->bsp_priv = dwmac;
291
292 return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
293}
294
295static int meson8b_dwmac_remove(struct platform_device *pdev)
296{
297 struct meson8b_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev);
298
299 clk_disable_unprepare(dwmac->m25_div_clk);
300
301 return stmmac_pltfr_remove(pdev);
302}
303
304static const struct of_device_id meson8b_dwmac_match[] = {
305 { .compatible = "amlogic,meson8b-dwmac" },
306 { .compatible = "amlogic,meson-gxbb-dwmac" },
307 { }
308};
309MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
310
311static struct platform_driver meson8b_dwmac_driver = {
312 .probe = meson8b_dwmac_probe,
313 .remove = meson8b_dwmac_remove,
314 .driver = {
315 .name = "meson8b-dwmac",
316 .pm = &stmmac_pltfr_pm_ops,
317 .of_match_table = meson8b_dwmac_match,
318 },
319};
320module_platform_driver(meson8b_dwmac_driver);
321
322MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
323MODULE_DESCRIPTION("Amlogic Meson8b and GXBB DWMAC glue layer");
324MODULE_LICENSE("GPL v2");
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h
index ffeb8d9e2b2e..64e147f53a9c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h
@@ -30,4 +30,12 @@ int stmmac_get_platform_resources(struct platform_device *pdev,
30int stmmac_pltfr_remove(struct platform_device *pdev); 30int stmmac_pltfr_remove(struct platform_device *pdev);
31extern const struct dev_pm_ops stmmac_pltfr_pm_ops; 31extern const struct dev_pm_ops stmmac_pltfr_pm_ops;
32 32
33static inline void *get_stmmac_bsp_priv(struct device *dev)
34{
35 struct net_device *ndev = dev_get_drvdata(dev);
36 struct stmmac_priv *priv = netdev_priv(ndev);
37
38 return priv->plat->bsp_priv;
39}
40
33#endif /* __STMMAC_PLATFORM_H__ */ 41#endif /* __STMMAC_PLATFORM_H__ */
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index f550c4596a7a..ba140eaee5c8 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -101,4 +101,14 @@ config NVMEM_VF610_OCOTP
101 This driver can also be build as a module. If so, the module will 101 This driver can also be build as a module. If so, the module will
102 be called nvmem-vf610-ocotp. 102 be called nvmem-vf610-ocotp.
103 103
104config MESON_EFUSE
105 tristate "Amlogic eFuse Support"
106 depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM
107 help
108 This is a driver to retrieve specific values from the eFuse found on
109 the Amlogic Meson SoCs.
110
111 This driver can also be built as a module. If so, the module
112 will be called nvmem_meson_efuse.
113
104endif 114endif
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 45ab1ae08fa9..8f942a0cdaec 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -22,3 +22,5 @@ obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o
22nvmem_sunxi_sid-y := sunxi_sid.o 22nvmem_sunxi_sid-y := sunxi_sid.o
23obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o 23obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o
24nvmem-vf610-ocotp-y := vf610-ocotp.o 24nvmem-vf610-ocotp-y := vf610-ocotp.o
25obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o
26nvmem_meson_efuse-y := meson-efuse.o
diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c
new file mode 100644
index 000000000000..f207c3b10482
--- /dev/null
+++ b/drivers/nvmem/meson-efuse.c
@@ -0,0 +1,93 @@
1/*
2 * Amlogic eFuse Driver
3 *
4 * Copyright (c) 2016 Endless Computers, Inc.
5 * Author: Carlo Caione <carlo@endlessm.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 */
16
17#include <linux/module.h>
18#include <linux/nvmem-provider.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21
22#include <linux/firmware/meson/meson_sm.h>
23
24static int meson_efuse_read(void *context, unsigned int offset,
25 void *val, size_t bytes)
26{
27 u8 *buf = val;
28 int ret;
29
30 ret = meson_sm_call_read(buf, SM_EFUSE_READ, offset,
31 bytes, 0, 0, 0);
32 if (ret < 0)
33 return ret;
34
35 return 0;
36}
37
38static struct nvmem_config econfig = {
39 .name = "meson-efuse",
40 .owner = THIS_MODULE,
41 .stride = 1,
42 .word_size = 1,
43 .read_only = true,
44};
45
46static const struct of_device_id meson_efuse_match[] = {
47 { .compatible = "amlogic,meson-gxbb-efuse", },
48 { /* sentinel */ },
49};
50MODULE_DEVICE_TABLE(of, meson_efuse_match);
51
52static int meson_efuse_probe(struct platform_device *pdev)
53{
54 struct nvmem_device *nvmem;
55 unsigned int size;
56
57 if (meson_sm_call(SM_EFUSE_USER_MAX, &size, 0, 0, 0, 0, 0) < 0)
58 return -EINVAL;
59
60 econfig.dev = &pdev->dev;
61 econfig.reg_read = meson_efuse_read;
62 econfig.size = size;
63
64 nvmem = nvmem_register(&econfig);
65 if (IS_ERR(nvmem))
66 return PTR_ERR(nvmem);
67
68 platform_set_drvdata(pdev, nvmem);
69
70 return 0;
71}
72
73static int meson_efuse_remove(struct platform_device *pdev)
74{
75 struct nvmem_device *nvmem = platform_get_drvdata(pdev);
76
77 return nvmem_unregister(nvmem);
78}
79
80static struct platform_driver meson_efuse_driver = {
81 .probe = meson_efuse_probe,
82 .remove = meson_efuse_remove,
83 .driver = {
84 .name = "meson-efuse",
85 .of_match_table = meson_efuse_match,
86 },
87};
88
89module_platform_driver(meson_efuse_driver);
90
91MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
92MODULE_DESCRIPTION("Amlogic Meson NVMEM driver");
93MODULE_LICENSE("GPL v2");
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index fc6f5251de5d..8f7b34c8a5d4 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -181,6 +181,38 @@ static const struct dwc2_core_params params_ltq = {
181 .hibernation = -1, 181 .hibernation = -1,
182}; 182};
183 183
184static const struct dwc2_core_params params_amlogic = {
185 .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
186 .otg_ver = -1,
187 .dma_enable = 1,
188 .dma_desc_enable = 0,
189 .dma_desc_fs_enable = 0,
190 .speed = DWC2_SPEED_PARAM_HIGH,
191 .enable_dynamic_fifo = 1,
192 .en_multiple_tx_fifo = -1,
193 .host_rx_fifo_size = 512,
194 .host_nperio_tx_fifo_size = 500,
195 .host_perio_tx_fifo_size = 500,
196 .max_transfer_size = -1,
197 .max_packet_count = -1,
198 .host_channels = 16,
199 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
200 .phy_utmi_width = -1,
201 .phy_ulpi_ddr = -1,
202 .phy_ulpi_ext_vbus = -1,
203 .i2c_enable = -1,
204 .ulpi_fs_ls = -1,
205 .host_support_fs_ls_low_power = -1,
206 .host_ls_low_power_phy_clk = -1,
207 .ts_dline = -1,
208 .reload_ctl = 1,
209 .ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
210 GAHBCFG_HBSTLEN_SHIFT,
211 .uframe_sched = 0,
212 .external_id_pin_ctl = -1,
213 .hibernation = -1,
214};
215
184/* 216/*
185 * Check the dr_mode against the module configuration and hardware 217 * Check the dr_mode against the module configuration and hardware
186 * capabilities. 218 * capabilities.
@@ -464,6 +496,8 @@ static const struct of_device_id dwc2_of_match_table[] = {
464 { .compatible = "lantiq,xrx200-usb", .data = &params_ltq }, 496 { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
465 { .compatible = "snps,dwc2", .data = NULL }, 497 { .compatible = "snps,dwc2", .data = NULL },
466 { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, 498 { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
499 { .compatible = "amlogic,meson8b-usb", .data = &params_amlogic },
500 { .compatible = "amlogic,meson-gxbb-usb", .data = &params_amlogic },
467 {}, 501 {},
468}; 502};
469MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 503MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h
new file mode 100644
index 000000000000..31751482d13c
--- /dev/null
+++ b/include/dt-bindings/clock/gxbb-aoclkc.h
@@ -0,0 +1,66 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 BayLibre, SAS.
8 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 * The full GNU General Public License is included in this distribution
22 * in the file called COPYING.
23 *
24 * BSD LICENSE
25 *
26 * Copyright (c) 2016 BayLibre, SAS.
27 * Author: Neil Armstrong <narmstrong@baylibre.com>
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
57#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
58
59#define CLKID_AO_REMOTE 0
60#define CLKID_AO_I2C_MASTER 1
61#define CLKID_AO_I2C_SLAVE 2
62#define CLKID_AO_UART1 3
63#define CLKID_AO_UART2 4
64#define CLKID_AO_IR_BLASTER 5
65
66#endif
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index f889d80246cb..baade6f429d0 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -6,7 +6,23 @@
6#define __GXBB_CLKC_H 6#define __GXBB_CLKC_H
7 7
8#define CLKID_CPUCLK 1 8#define CLKID_CPUCLK 1
9#define CLKID_HDMI_PLL 2
10#define CLKID_FCLK_DIV2 4
11#define CLKID_FCLK_DIV3 5
12#define CLKID_FCLK_DIV4 6
9#define CLKID_CLK81 12 13#define CLKID_CLK81 12
14#define CLKID_MPLL2 15
15#define CLKID_SPI 34
16#define CLKID_I2C 22
10#define CLKID_ETH 36 17#define CLKID_ETH 36
18#define CLKID_USB0 50
19#define CLKID_USB1 51
20#define CLKID_USB 55
21#define CLKID_USB1_DDR_BRIDGE 64
22#define CLKID_USB0_DDR_BRIDGE 65
23#define CLKID_AO_I2C 93
24#define CLKID_SD_EMMC_A 94
25#define CLKID_SD_EMMC_B 95
26#define CLKID_SD_EMMC_C 96
11 27
12#endif /* __GXBB_CLKC_H */ 28#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 595a58d0969a..a55ff8c9b30f 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -22,6 +22,4 @@
22#define CLKID_MPEG_SEL 14 22#define CLKID_MPEG_SEL 14
23#define CLKID_MPEG_DIV 15 23#define CLKID_MPEG_DIV 15
24 24
25#define CLK_NR_CLKS (CLKID_MPEG_DIV + 1)
26
27#endif /* __MESON8B_CLKC_H */ 25#endif /* __MESON8B_CLKC_H */
diff --git a/include/dt-bindings/reset/gxbb-aoclkc.h b/include/dt-bindings/reset/gxbb-aoclkc.h
new file mode 100644
index 000000000000..9e3fd60c309c
--- /dev/null
+++ b/include/dt-bindings/reset/gxbb-aoclkc.h
@@ -0,0 +1,66 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 BayLibre, SAS.
8 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 * The full GNU General Public License is included in this distribution
22 * in the file called COPYING.
23 *
24 * BSD LICENSE
25 *
26 * Copyright (c) 2016 BayLibre, SAS.
27 * Author: Neil Armstrong <narmstrong@baylibre.com>
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
57#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
58
59#define RESET_AO_REMOTE 0
60#define RESET_AO_I2C_MASTER 1
61#define RESET_AO_I2C_SLAVE 2
62#define RESET_AO_UART1 3
63#define RESET_AO_UART2 4
64#define RESET_AO_IR_BLASTER 5
65
66#endif
diff --git a/include/linux/firmware/meson/meson_sm.h b/include/linux/firmware/meson/meson_sm.h
new file mode 100644
index 000000000000..8e953c6f394a
--- /dev/null
+++ b/include/linux/firmware/meson/meson_sm.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright (C) 2016 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 * You should have received a copy of the GNU General Public License
10 * along with this program. If not, see <http://www.gnu.org/licenses/>.
11 */
12
13#ifndef _MESON_SM_FW_H_
14#define _MESON_SM_FW_H_
15
16enum {
17 SM_EFUSE_READ,
18 SM_EFUSE_WRITE,
19 SM_EFUSE_USER_MAX,
20};
21
22struct meson_sm_firmware;
23
24int meson_sm_call(unsigned int cmd_index, u32 *ret, u32 arg0, u32 arg1,
25 u32 arg2, u32 arg3, u32 arg4);
26int meson_sm_call_write(void *buffer, unsigned int b_size, unsigned int cmd_index,
27 u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4);
28int meson_sm_call_read(void *buffer, unsigned int cmd_index, u32 arg0, u32 arg1,
29 u32 arg2, u32 arg3, u32 arg4);
30
31#endif /* _MESON_SM_FW_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 00:34:57 -0400