drm/amdgpu/gfx8: cache rb config values

Needed when for SR-IOV and when PG is enabled.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 15 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index ba36db8002e7..e0664415b18e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3694,6 +3694,21 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
                                                         num_rb_pipes);
         }
 
+        /* cache the values for userspace */
+        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
+                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
+                        gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
+                        adev->gfx.config.rb_config[i][j].rb_backend_disable =
+                                RREG32(mmCC_RB_BACKEND_DISABLE);
+                        adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
+                                RREG32(mmGC_USER_RB_BACKEND_DISABLE);
+                        adev->gfx.config.rb_config[i][j].raster_config =
+                                RREG32(mmPA_SC_RASTER_CONFIG);
+                        adev->gfx.config.rb_config[i][j].raster_config_1 =
+                                RREG32(mmPA_SC_RASTER_CONFIG_1);
+                }
+        }
+        gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
         mutex_unlock(&adev->grbm_idx_mutex);
 }