diff options
author | Evan Quan <evan.quan@amd.com> | 2017-12-29 01:46:13 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-02-19 14:17:05 -0500 |
commit | 39199b803bfe3376dc343088f25d7c7804f15b71 (patch) | |
tree | 38f64504be90e45af6875749548c69fe2b883a97 | |
parent | 8053e976cfe69afd5453a357761a885a2085c6c1 (diff) |
drm/amd/powerplay: removed hwmgr_handle_task unused parameter and given a better name for
other parameter
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 |
6 files changed, 18 insertions, 20 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index a8437a3296a6..8a8d09dd8750 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | |||
@@ -328,8 +328,8 @@ enum amdgpu_pcie_gen { | |||
328 | #define amdgpu_dpm_set_mclk_od(adev, value) \ | 328 | #define amdgpu_dpm_set_mclk_od(adev, value) \ |
329 | ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) | 329 | ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) |
330 | 330 | ||
331 | #define amdgpu_dpm_dispatch_task(adev, task_id, input, output) \ | 331 | #define amdgpu_dpm_dispatch_task(adev, task_id, user_state) \ |
332 | ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (input), (output)) | 332 | ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (user_state)) |
333 | 333 | ||
334 | #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \ | 334 | #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \ |
335 | ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal))) | 335 | ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal))) |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 01a996c6b802..e5ee7cf0e9d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | |||
@@ -116,7 +116,7 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev, | |||
116 | } | 116 | } |
117 | 117 | ||
118 | if (adev->powerplay.pp_funcs->dispatch_tasks) { | 118 | if (adev->powerplay.pp_funcs->dispatch_tasks) { |
119 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL); | 119 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state); |
120 | } else { | 120 | } else { |
121 | mutex_lock(&adev->pm.mutex); | 121 | mutex_lock(&adev->pm.mutex); |
122 | adev->pm.dpm.user_state = state; | 122 | adev->pm.dpm.user_state = state; |
@@ -316,7 +316,7 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev, | |||
316 | if (state != POWER_STATE_TYPE_INTERNAL_BOOT && | 316 | if (state != POWER_STATE_TYPE_INTERNAL_BOOT && |
317 | state != POWER_STATE_TYPE_DEFAULT) { | 317 | state != POWER_STATE_TYPE_DEFAULT) { |
318 | amdgpu_dpm_dispatch_task(adev, | 318 | amdgpu_dpm_dispatch_task(adev, |
319 | AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL); | 319 | AMD_PP_TASK_ENABLE_USER_STATE, &state); |
320 | adev->pp_force_state_enabled = true; | 320 | adev->pp_force_state_enabled = true; |
321 | } | 321 | } |
322 | } | 322 | } |
@@ -530,7 +530,7 @@ static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, | |||
530 | amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); | 530 | amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); |
531 | 531 | ||
532 | if (adev->powerplay.pp_funcs->dispatch_tasks) { | 532 | if (adev->powerplay.pp_funcs->dispatch_tasks) { |
533 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL); | 533 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL); |
534 | } else { | 534 | } else { |
535 | adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; | 535 | adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; |
536 | amdgpu_pm_compute_clocks(adev); | 536 | amdgpu_pm_compute_clocks(adev); |
@@ -574,7 +574,7 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, | |||
574 | amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); | 574 | amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); |
575 | 575 | ||
576 | if (adev->powerplay.pp_funcs->dispatch_tasks) { | 576 | if (adev->powerplay.pp_funcs->dispatch_tasks) { |
577 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL); | 577 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL); |
578 | } else { | 578 | } else { |
579 | adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; | 579 | adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; |
580 | amdgpu_pm_compute_clocks(adev); | 580 | amdgpu_pm_compute_clocks(adev); |
@@ -1462,7 +1462,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) | |||
1462 | } | 1462 | } |
1463 | 1463 | ||
1464 | if (adev->powerplay.pp_funcs->dispatch_tasks) { | 1464 | if (adev->powerplay.pp_funcs->dispatch_tasks) { |
1465 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL, NULL); | 1465 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL); |
1466 | } else { | 1466 | } else { |
1467 | mutex_lock(&adev->pm.mutex); | 1467 | mutex_lock(&adev->pm.mutex); |
1468 | adev->pm.dpm.new_active_crtcs = 0; | 1468 | adev->pm.dpm.new_active_crtcs = 0; |
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index ed27626dff14..0f89d2a8ebbf 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h | |||
@@ -256,7 +256,7 @@ struct amd_pm_funcs { | |||
256 | void (*powergate_vce)(void *handle, bool gate); | 256 | void (*powergate_vce)(void *handle, bool gate); |
257 | struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); | 257 | struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); |
258 | int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, | 258 | int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, |
259 | void *input, void *output); | 259 | enum amd_pm_state_type *user_state); |
260 | int (*load_firmware)(void *handle); | 260 | int (*load_firmware)(void *handle); |
261 | int (*wait_for_fw_loading_complete)(void *handle); | 261 | int (*wait_for_fw_loading_complete)(void *handle); |
262 | int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); | 262 | int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); |
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 4c3223a4d62b..8859b6754545 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c | |||
@@ -33,7 +33,7 @@ | |||
33 | #define PP_DPM_DISABLED 0xCCCC | 33 | #define PP_DPM_DISABLED 0xCCCC |
34 | 34 | ||
35 | static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, | 35 | static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, |
36 | void *input, void *output); | 36 | enum amd_pm_state_type *user_state); |
37 | 37 | ||
38 | static inline int pp_check(struct pp_instance *handle) | 38 | static inline int pp_check(struct pp_instance *handle) |
39 | { | 39 | { |
@@ -198,7 +198,7 @@ static int pp_late_init(void *handle) | |||
198 | ret = pp_check(pp_handle); | 198 | ret = pp_check(pp_handle); |
199 | if (ret == 0) | 199 | if (ret == 0) |
200 | pp_dpm_dispatch_tasks(pp_handle, | 200 | pp_dpm_dispatch_tasks(pp_handle, |
201 | AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); | 201 | AMD_PP_TASK_COMPLETE_INIT, NULL); |
202 | 202 | ||
203 | return 0; | 203 | return 0; |
204 | } | 204 | } |
@@ -392,7 +392,7 @@ static int pp_dpm_force_performance_level(void *handle, | |||
392 | mutex_lock(&pp_handle->pp_lock); | 392 | mutex_lock(&pp_handle->pp_lock); |
393 | pp_dpm_en_umd_pstate(hwmgr, &level); | 393 | pp_dpm_en_umd_pstate(hwmgr, &level); |
394 | hwmgr->request_dpm_level = level; | 394 | hwmgr->request_dpm_level = level; |
395 | hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL); | 395 | hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL); |
396 | mutex_unlock(&pp_handle->pp_lock); | 396 | mutex_unlock(&pp_handle->pp_lock); |
397 | 397 | ||
398 | return 0; | 398 | return 0; |
@@ -511,7 +511,7 @@ static void pp_dpm_powergate_uvd(void *handle, bool gate) | |||
511 | } | 511 | } |
512 | 512 | ||
513 | static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, | 513 | static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, |
514 | void *input, void *output) | 514 | enum amd_pm_state_type *user_state) |
515 | { | 515 | { |
516 | int ret = 0; | 516 | int ret = 0; |
517 | struct pp_instance *pp_handle = (struct pp_instance *)handle; | 517 | struct pp_instance *pp_handle = (struct pp_instance *)handle; |
@@ -522,7 +522,7 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, | |||
522 | return ret; | 522 | return ret; |
523 | 523 | ||
524 | mutex_lock(&pp_handle->pp_lock); | 524 | mutex_lock(&pp_handle->pp_lock); |
525 | ret = hwmgr_handle_task(pp_handle, task_id, input, output); | 525 | ret = hwmgr_handle_task(pp_handle, task_id, user_state); |
526 | mutex_unlock(&pp_handle->pp_lock); | 526 | mutex_unlock(&pp_handle->pp_lock); |
527 | 527 | ||
528 | return ret; | 528 | return ret; |
@@ -799,7 +799,7 @@ static int amd_powerplay_reset(void *handle) | |||
799 | if (ret) | 799 | if (ret) |
800 | return ret; | 800 | return ret; |
801 | 801 | ||
802 | return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); | 802 | return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL); |
803 | } | 803 | } |
804 | 804 | ||
805 | static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) | 805 | static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index ec3cdf5a2d4a..654cb11bdf65 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | |||
@@ -369,7 +369,7 @@ static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) | |||
369 | } | 369 | } |
370 | 370 | ||
371 | int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id, | 371 | int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id, |
372 | void *input, void *output) | 372 | enum amd_pm_state_type *user_state) |
373 | { | 373 | { |
374 | int ret = 0; | 374 | int ret = 0; |
375 | struct pp_hwmgr *hwmgr; | 375 | struct pp_hwmgr *hwmgr; |
@@ -391,17 +391,15 @@ int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id, | |||
391 | break; | 391 | break; |
392 | case AMD_PP_TASK_ENABLE_USER_STATE: | 392 | case AMD_PP_TASK_ENABLE_USER_STATE: |
393 | { | 393 | { |
394 | enum amd_pm_state_type ps; | ||
395 | enum PP_StateUILabel requested_ui_label; | 394 | enum PP_StateUILabel requested_ui_label; |
396 | struct pp_power_state *requested_ps = NULL; | 395 | struct pp_power_state *requested_ps = NULL; |
397 | 396 | ||
398 | if (input == NULL) { | 397 | if (user_state == NULL) { |
399 | ret = -EINVAL; | 398 | ret = -EINVAL; |
400 | break; | 399 | break; |
401 | } | 400 | } |
402 | ps = *(unsigned long *)input; | ||
403 | 401 | ||
404 | requested_ui_label = power_state_convert(ps); | 402 | requested_ui_label = power_state_convert(*user_state); |
405 | ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps); | 403 | ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps); |
406 | if (ret) | 404 | if (ret) |
407 | return ret; | 405 | return ret; |
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 565fe0832f41..bd2889f73426 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | |||
@@ -761,7 +761,7 @@ extern int hwmgr_hw_suspend(struct pp_instance *handle); | |||
761 | extern int hwmgr_hw_resume(struct pp_instance *handle); | 761 | extern int hwmgr_hw_resume(struct pp_instance *handle); |
762 | extern int hwmgr_handle_task(struct pp_instance *handle, | 762 | extern int hwmgr_handle_task(struct pp_instance *handle, |
763 | enum amd_pp_task task_id, | 763 | enum amd_pp_task task_id, |
764 | void *input, void *output); | 764 | enum amd_pm_state_type *user_state); |
765 | extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, | 765 | extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, |
766 | uint32_t value, uint32_t mask); | 766 | uint32_t value, uint32_t mask); |
767 | 767 | ||