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authorSuman Anna <s-anna@ti.com>2015-03-16 13:20:37 -0400
committerTony Lindgren <tony@atomide.com>2015-03-16 22:24:52 -0400
commit38b1565ca77f411c85427988fa30c3482d5d7e68 (patch)
tree663f1cf70f6a3ea63d6242d513db5e204db41ae3
parent624ce7616d90337738dfd24c8e6ff7adf0060ad7 (diff)
ARM: dts: DRA7: Remove ti,timer-dsp and ti,timer-pwm properties
Remove the 'ti,timer-dsp' and 'ti,timer-pwm' properties from the timer nodes that still have them. This seems to be copied from OMAP5, on which only certain timers are capable of providing PWM functionality or be able to interrupt the DSP. All the GPTimers On DRA7 are capable of PWM and interrupting any core (due to the presence of Crossbar). These properties were used by the driver to add capabilities to each timer, and support requesting timers by capability. In the DT world, we expect any users of timers to use phandles to the respective timer, and use the omap_dm_timer_request_by_node() API. The API to request using capabilities, omap_dm_timer_request_by_cap() API should be deprecated eventually. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/dra7.dtsi7
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 127608d79033..eea4a54d6cb3 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -658,7 +658,6 @@
658 reg = <0x48820000 0x80>; 658 reg = <0x48820000 0x80>;
659 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 659 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
660 ti,hwmods = "timer5"; 660 ti,hwmods = "timer5";
661 ti,timer-dsp;
662 }; 661 };
663 662
664 timer6: timer@48822000 { 663 timer6: timer@48822000 {
@@ -666,8 +665,6 @@
666 reg = <0x48822000 0x80>; 665 reg = <0x48822000 0x80>;
667 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 666 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
668 ti,hwmods = "timer6"; 667 ti,hwmods = "timer6";
669 ti,timer-dsp;
670 ti,timer-pwm;
671 }; 668 };
672 669
673 timer7: timer@48824000 { 670 timer7: timer@48824000 {
@@ -675,7 +672,6 @@
675 reg = <0x48824000 0x80>; 672 reg = <0x48824000 0x80>;
676 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 673 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 ti,hwmods = "timer7"; 674 ti,hwmods = "timer7";
678 ti,timer-dsp;
679 }; 675 };
680 676
681 timer8: timer@48826000 { 677 timer8: timer@48826000 {
@@ -683,8 +679,6 @@
683 reg = <0x48826000 0x80>; 679 reg = <0x48826000 0x80>;
684 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 680 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
685 ti,hwmods = "timer8"; 681 ti,hwmods = "timer8";
686 ti,timer-dsp;
687 ti,timer-pwm;
688 }; 682 };
689 683
690 timer9: timer@4803e000 { 684 timer9: timer@4803e000 {
@@ -706,7 +700,6 @@
706 reg = <0x48088000 0x80>; 700 reg = <0x48088000 0x80>;
707 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 701 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
708 ti,hwmods = "timer11"; 702 ti,hwmods = "timer11";
709 ti,timer-pwm;
710 }; 703 };
711 704
712 timer13: timer@48828000 { 705 timer13: timer@48828000 {