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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2016-10-29 17:31:27 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-01-26 02:24:36 -0500
commit387812143cbede75658d267ad224e653b83b498b (patch)
tree37171124de61a0c963203c9ae4947ff8644847b2
parent57a10f29e0b3b407336293139459012259885ce2 (diff)
ARM: dts: r8a7794: remove Z clock
commit 68cc085a4daaa32f7138de1e918331c05165a484 upstream. R8A7794 doesn't have Cortex-A15 CPUs, thus there's no Z clock... Fixes: 0dce5454d5c2 ("ARM: shmobile: Initial r8a7794 SoC device tree") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi3
-rw-r--r--include/dt-bindings/clock/r8a7794-clock.h3
2 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index a9368010fb8d..7e860d3737ff 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1025,8 +1025,7 @@
1025 clocks = <&extal_clk &usb_extal_clk>; 1025 clocks = <&extal_clk &usb_extal_clk>;
1026 #clock-cells = <1>; 1026 #clock-cells = <1>;
1027 clock-output-names = "main", "pll0", "pll1", "pll3", 1027 clock-output-names = "main", "pll0", "pll1", "pll3",
1028 "lb", "qspi", "sdh", "sd0", "z", 1028 "lb", "qspi", "sdh", "sd0", "rcan";
1029 "rcan";
1030 #power-domain-cells = <0>; 1029 #power-domain-cells = <0>;
1031 }; 1030 };
1032 /* Variable factor clocks */ 1031 /* Variable factor clocks */
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index 9d02f5317c7c..88e64846cf37 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -20,8 +20,7 @@
20#define R8A7794_CLK_QSPI 5 20#define R8A7794_CLK_QSPI 5
21#define R8A7794_CLK_SDH 6 21#define R8A7794_CLK_SDH 6
22#define R8A7794_CLK_SD0 7 22#define R8A7794_CLK_SD0 7
23#define R8A7794_CLK_Z 8 23#define R8A7794_CLK_RCAN 8
24#define R8A7794_CLK_RCAN 9
25 24
26/* MSTP0 */ 25/* MSTP0 */
27#define R8A7794_CLK_MSIOF0 0 26#define R8A7794_CLK_MSIOF0 0