xtensa: move S32C1I self-test to a separate file

The test is not called from any of the setup functions, so there's no
reason keeping it in the setup.c. Move it to s32c1i_selftest.c and drop
related #include directives.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

3 files changed, 129 insertions, 115 deletions

diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile
index c31f5d5afc7d..264fb89c444e 100644
--- a/arch/xtensa/kernel/Makefile
+++ b/arch/xtensa/kernel/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_FUNCTION_TRACER) += mcount.o
 obj-$(CONFIG_SMP) += smp.o mxhead.o
 obj-$(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) += perf_event.o
 obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
+obj-$(CONFIG_S32C1I_SELFTEST) += s32c1i_selftest.o
 
 AFLAGS_head.o += -mtext-section-literals
 AFLAGS_mxhead.o += -mtext-section-literals
diff --git a/arch/xtensa/kernel/s32c1i_selftest.c b/arch/xtensa/kernel/s32c1i_selftest.c
new file mode 100644
index 000000000000..07e56e3a9a8b
--- /dev/null
+++ b/arch/xtensa/kernel/s32c1i_selftest.c
@@ -0,0 +1,128 @@
+/*
+ * S32C1I selftest.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <asm/traps.h>
+
+#if XCHAL_HAVE_S32C1I
+
+static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
+
+/*
+ * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
+ *
+ * If *v == cmp, set *v = set.  Return previous *v.
+ */
+static inline int probed_compare_swap(int *v, int cmp, int set)
+{
+        int tmp;
+
+        __asm__ __volatile__(
+                        "       movi    %1, 1f\n"
+                        "       s32i    %1, %4, 0\n"
+                        "       wsr     %2, scompare1\n"
+                        "1:     s32c1i  %0, %3, 0\n"
+                        : "=a" (set), "=&a" (tmp)
+                        : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
+                        : "memory"
+                        );
+        return set;
+}
+
+/* Handle probed exception */
+
+static void __init do_probed_exception(struct pt_regs *regs,
+                                       unsigned long exccause)
+{
+        if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
+                regs->pc += 3;          /* skip the s32c1i instruction */
+                rcw_exc = exccause;
+        } else {
+                do_unhandled(regs, exccause);
+        }
+}
+
+/* Simple test of S32C1I (soc bringup assist) */
+
+static int __init check_s32c1i(void)
+{
+        int n, cause1, cause2;
+        void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
+
+        rcw_probe_pc = 0;
+        handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
+                        do_probed_exception);
+        handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
+                        do_probed_exception);
+        handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
+                        do_probed_exception);
+
+        /* First try an S32C1I that does not store: */
+        rcw_exc = 0;
+        rcw_word = 1;
+        n = probed_compare_swap(&rcw_word, 0, 2);
+        cause1 = rcw_exc;
+
+        /* took exception? */
+        if (cause1 != 0) {
+                /* unclean exception? */
+                if (n != 2 || rcw_word != 1)
+                        panic("S32C1I exception error");
+        } else if (rcw_word != 1 || n != 1) {
+                panic("S32C1I compare error");
+        }
+
+        /* Then an S32C1I that stores: */
+        rcw_exc = 0;
+        rcw_word = 0x1234567;
+        n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
+        cause2 = rcw_exc;
+
+        if (cause2 != 0) {
+                /* unclean exception? */
+                if (n != 0xabcde || rcw_word != 0x1234567)
+                        panic("S32C1I exception error (b)");
+        } else if (rcw_word != 0xabcde || n != 0x1234567) {
+                panic("S32C1I store error");
+        }
+
+        /* Verify consistency of exceptions: */
+        if (cause1 || cause2) {
+                pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
+                /* If emulation of S32C1I upon bus error gets implemented,
+                 * we can get rid of this panic for single core (not SMP)
+                 */
+                panic("S32C1I exceptions not currently supported");
+        }
+        if (cause1 != cause2)
+                panic("inconsistent S32C1I exceptions");
+
+        trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
+        trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
+        trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
+        return 0;
+}
+
+#else /* XCHAL_HAVE_S32C1I */
+
+/* This condition should not occur with a commercially deployed processor.
+ * Display reminder for early engr test or demo chips / FPGA bitstreams
+ */
+static int __init check_s32c1i(void)
+{
+        pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
+        return 0;
+}
+
+#endif /* XCHAL_HAVE_S32C1I */
+
+early_initcall(check_s32c1i);
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 80ed169dce07..848e8568fb3c 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -44,7 +44,6 @@
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/param.h>
-#include <asm/traps.h>
 #include <asm/smp.h>
 #include <asm/sysmem.h>
 
@@ -311,120 +310,6 @@ extern char _SecondaryResetVector_text_start;
 extern char _SecondaryResetVector_text_end;
 #endif
 
-
-#ifdef CONFIG_S32C1I_SELFTEST
-#if XCHAL_HAVE_S32C1I
-
-static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
-
-/*
- * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
- *
- * If *v == cmp, set *v = set.  Return previous *v.
- */
-static inline int probed_compare_swap(int *v, int cmp, int set)
-{
-        int tmp;
-
-        __asm__ __volatile__(
-                        "       movi    %1, 1f\n"
-                        "       s32i    %1, %4, 0\n"
-                        "       wsr     %2, scompare1\n"
-                        "1:     s32c1i  %0, %3, 0\n"
-                        : "=a" (set), "=&a" (tmp)
-                        : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
-                        : "memory"
-                        );
-        return set;
-}
-
-/* Handle probed exception */
-
-static void __init do_probed_exception(struct pt_regs *regs,
-                unsigned long exccause)
-{
-        if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
-                regs->pc += 3;          /* skip the s32c1i instruction */
-                rcw_exc = exccause;
-        } else {
-                do_unhandled(regs, exccause);
-        }
-}
-
-/* Simple test of S32C1I (soc bringup assist) */
-
-static int __init check_s32c1i(void)
-{
-        int n, cause1, cause2;
-        void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
-
-        rcw_probe_pc = 0;
-        handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
-                        do_probed_exception);
-        handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
-                        do_probed_exception);
-        handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
-                        do_probed_exception);
-
-        /* First try an S32C1I that does not store: */
-        rcw_exc = 0;
-        rcw_word = 1;
-        n = probed_compare_swap(&rcw_word, 0, 2);
-        cause1 = rcw_exc;
-
-        /* took exception? */
-        if (cause1 != 0) {
-                /* unclean exception? */
-                if (n != 2 || rcw_word != 1)
-                        panic("S32C1I exception error");
-        } else if (rcw_word != 1 || n != 1) {
-                panic("S32C1I compare error");
-        }
-
-        /* Then an S32C1I that stores: */
-        rcw_exc = 0;
-        rcw_word = 0x1234567;
-        n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
-        cause2 = rcw_exc;
-
-        if (cause2 != 0) {
-                /* unclean exception? */
-                if (n != 0xabcde || rcw_word != 0x1234567)
-                        panic("S32C1I exception error (b)");
-        } else if (rcw_word != 0xabcde || n != 0x1234567) {
-                panic("S32C1I store error");
-        }
-
-        /* Verify consistency of exceptions: */
-        if (cause1 || cause2) {
-                pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
-                /* If emulation of S32C1I upon bus error gets implemented,
-                   we can get rid of this panic for single core (not SMP) */
-                panic("S32C1I exceptions not currently supported");
-        }
-        if (cause1 != cause2)
-                panic("inconsistent S32C1I exceptions");
-
-        trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
-        trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
-        trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
-        return 0;
-}
-
-#else /* XCHAL_HAVE_S32C1I */
-
-/* This condition should not occur with a commercially deployed processor.
-   Display reminder for early engr test or demo chips / FPGA bitstreams */
-static int __init check_s32c1i(void)
-{
-        pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
-        return 0;
-}
-
-#endif /* XCHAL_HAVE_S32C1I */
-early_initcall(check_s32c1i);
-#endif /* CONFIG_S32C1I_SELFTEST */
-
 static inline int mem_reserve(unsigned long start, unsigned long end)
 {
         return memblock_reserve(start, end - start);