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authorStephen Boyd <sboyd@kernel.org>2018-05-15 18:49:49 -0400
committerStephen Boyd <sboyd@kernel.org>2018-05-15 18:49:49 -0400
commit37ffe9acecc689fdaba5dc6853054ebba4e7f1da (patch)
tree1106f2718122b59793d59b8484297da8c7c116fa
parent60cc43fc888428bb2f18f08997432d426a243338 (diff)
parent24a2e6796eb23d17d4e32a27f19336248666272c (diff)
Merge tag 'meson-clk-4.18-1' of https://github.com/BayLibre/clk-meson into clk-meson
Pull meson clk driver updates from Jerome Brunet: - Add meson8b nand clocks - Add gxbb video decoder clocks - Rework of gxbb AO clock controller code to allow code reuse - Add axg AO clock controller A rework of the AO clock controller found on the gxbb SoC family has been done to improve code re-usability before introducing a very similar controller for the axg SoC family. * tag 'meson-clk-4.18-1' of https://github.com/BayLibre/clk-meson: clk: meson: drop CLK_SET_RATE_PARENT flag clk: meson-axg: Add AO Clock and Reset controller driver clk: meson: aoclk: refactor common code into dedicated file clk: meson: migrate to devm_of_clk_add_hw_provider API clk: meson: gxbb: add the video decoder clocks clk: meson: meson8b: add support for the NAND clocks dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks dt-bindings: clock: meson8b: export the NAND clock
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt1
-rw-r--r--drivers/clk/meson/Kconfig8
-rw-r--r--drivers/clk/meson/Makefile3
-rw-r--r--drivers/clk/meson/axg-aoclk.c164
-rw-r--r--drivers/clk/meson/axg-aoclk.h29
-rw-r--r--drivers/clk/meson/gxbb-aoclk.c96
-rw-r--r--drivers/clk/meson/gxbb-aoclk.h5
-rw-r--r--drivers/clk/meson/gxbb.c114
-rw-r--r--drivers/clk/meson/gxbb.h6
-rw-r--r--drivers/clk/meson/meson-aoclk.c81
-rw-r--r--drivers/clk/meson/meson-aoclk.h34
-rw-r--r--drivers/clk/meson/meson8b.c54
-rw-r--r--drivers/clk/meson/meson8b.h5
-rw-r--r--include/dt-bindings/clock/axg-aoclkc.h26
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h2
-rw-r--r--include/dt-bindings/clock/meson8b-clkc.h1
-rw-r--r--include/dt-bindings/reset/axg-aoclkc.h20
17 files changed, 583 insertions, 66 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index 786dc39ca904..3a880528030e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -9,6 +9,7 @@ Required Properties:
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc" 9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" 10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc" 11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
12 followed by the common "amlogic,meson-gx-aoclkc" 13 followed by the common "amlogic,meson-gx-aoclkc"
13 14
14- #clock-cells: should be 1. 15- #clock-cells: should be 1.
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec522aec..815659eebea3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -3,6 +3,12 @@ config COMMON_CLK_AMLOGIC
3 depends on OF 3 depends on OF
4 depends on ARCH_MESON || COMPILE_TEST 4 depends on ARCH_MESON || COMPILE_TEST
5 5
6config COMMON_CLK_MESON_AO
7 bool
8 depends on OF
9 depends on ARCH_MESON || COMPILE_TEST
10 select COMMON_CLK_REGMAP_MESON
11
6config COMMON_CLK_REGMAP_MESON 12config COMMON_CLK_REGMAP_MESON
7 bool 13 bool
8 select REGMAP 14 select REGMAP
@@ -21,6 +27,7 @@ config COMMON_CLK_GXBB
21 bool 27 bool
22 depends on COMMON_CLK_AMLOGIC 28 depends on COMMON_CLK_AMLOGIC
23 select RESET_CONTROLLER 29 select RESET_CONTROLLER
30 select COMMON_CLK_MESON_AO
24 select COMMON_CLK_REGMAP_MESON 31 select COMMON_CLK_REGMAP_MESON
25 select MFD_SYSCON 32 select MFD_SYSCON
26 help 33 help
@@ -31,6 +38,7 @@ config COMMON_CLK_AXG
31 bool 38 bool
32 depends on COMMON_CLK_AMLOGIC 39 depends on COMMON_CLK_AMLOGIC
33 select RESET_CONTROLLER 40 select RESET_CONTROLLER
41 select COMMON_CLK_MESON_AO
34 select COMMON_CLK_REGMAP_MESON 42 select COMMON_CLK_REGMAP_MESON
35 select MFD_SYSCON 43 select MFD_SYSCON
36 help 44 help
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index ffee82e60b7a..d0d13aeb369a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,7 +3,8 @@
3# 3#
4 4
5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o 5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
6obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o 7obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o 8obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
8obj-$(CONFIG_COMMON_CLK_AXG) += axg.o 9obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
9obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o 10obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
new file mode 100644
index 000000000000..29e088542387
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -0,0 +1,164 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Amlogic Meson-AXG Clock Controller Driver
4 *
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
7 *
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 */
11#include <linux/clk-provider.h>
12#include <linux/platform_device.h>
13#include <linux/reset-controller.h>
14#include <linux/mfd/syscon.h>
15#include "clk-regmap.h"
16#include "meson-aoclk.h"
17#include "axg-aoclk.h"
18
19#define AXG_AO_GATE(_name, _bit) \
20static struct clk_regmap axg_aoclk_##_name = { \
21 .data = &(struct clk_regmap_gate_data) { \
22 .offset = (AO_RTI_GEN_CNTL_REG0), \
23 .bit_idx = (_bit), \
24 }, \
25 .hw.init = &(struct clk_init_data) { \
26 .name = "axg_ao_" #_name, \
27 .ops = &clk_regmap_gate_ops, \
28 .parent_names = (const char *[]){ "clk81" }, \
29 .num_parents = 1, \
30 .flags = CLK_IGNORE_UNUSED, \
31 }, \
32}
33
34AXG_AO_GATE(remote, 0);
35AXG_AO_GATE(i2c_master, 1);
36AXG_AO_GATE(i2c_slave, 2);
37AXG_AO_GATE(uart1, 3);
38AXG_AO_GATE(uart2, 5);
39AXG_AO_GATE(ir_blaster, 6);
40AXG_AO_GATE(saradc, 7);
41
42static struct clk_regmap axg_aoclk_clk81 = {
43 .data = &(struct clk_regmap_mux_data) {
44 .offset = AO_RTI_PWR_CNTL_REG0,
45 .mask = 0x1,
46 .shift = 8,
47 },
48 .hw.init = &(struct clk_init_data){
49 .name = "axg_ao_clk81",
50 .ops = &clk_regmap_mux_ro_ops,
51 .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
52 .num_parents = 2,
53 },
54};
55
56static struct clk_regmap axg_aoclk_saradc_mux = {
57 .data = &(struct clk_regmap_mux_data) {
58 .offset = AO_SAR_CLK,
59 .mask = 0x3,
60 .shift = 9,
61 },
62 .hw.init = &(struct clk_init_data){
63 .name = "axg_ao_saradc_mux",
64 .ops = &clk_regmap_mux_ops,
65 .parent_names = (const char *[]){ "xtal", "axg_ao_clk81" },
66 .num_parents = 2,
67 },
68};
69
70static struct clk_regmap axg_aoclk_saradc_div = {
71 .data = &(struct clk_regmap_div_data) {
72 .offset = AO_SAR_CLK,
73 .shift = 0,
74 .width = 8,
75 },
76 .hw.init = &(struct clk_init_data){
77 .name = "axg_ao_saradc_div",
78 .ops = &clk_regmap_divider_ops,
79 .parent_names = (const char *[]){ "axg_ao_saradc_mux" },
80 .num_parents = 1,
81 .flags = CLK_SET_RATE_PARENT,
82 },
83};
84
85static struct clk_regmap axg_aoclk_saradc_gate = {
86 .data = &(struct clk_regmap_gate_data) {
87 .offset = AO_SAR_CLK,
88 .bit_idx = 8,
89 },
90 .hw.init = &(struct clk_init_data){
91 .name = "axg_ao_saradc_gate",
92 .ops = &clk_regmap_gate_ops,
93 .parent_names = (const char *[]){ "axg_ao_saradc_div" },
94 .num_parents = 1,
95 .flags = CLK_SET_RATE_PARENT,
96 },
97};
98
99static const unsigned int axg_aoclk_reset[] = {
100 [RESET_AO_REMOTE] = 16,
101 [RESET_AO_I2C_MASTER] = 18,
102 [RESET_AO_I2C_SLAVE] = 19,
103 [RESET_AO_UART1] = 17,
104 [RESET_AO_UART2] = 22,
105 [RESET_AO_IR_BLASTER] = 23,
106};
107
108static struct clk_regmap *axg_aoclk_regmap[] = {
109 [CLKID_AO_REMOTE] = &axg_aoclk_remote,
110 [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master,
111 [CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave,
112 [CLKID_AO_UART1] = &axg_aoclk_uart1,
113 [CLKID_AO_UART2] = &axg_aoclk_uart2,
114 [CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster,
115 [CLKID_AO_SAR_ADC] = &axg_aoclk_saradc,
116 [CLKID_AO_CLK81] = &axg_aoclk_clk81,
117 [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux,
118 [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div,
119 [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate,
120};
121
122static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
123 .hws = {
124 [CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
125 [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
126 [CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
127 [CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
128 [CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
129 [CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
130 [CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
131 [CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
132 [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
133 [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
134 [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
135 },
136 .num = NR_CLKS,
137};
138
139static const struct meson_aoclk_data axg_aoclkc_data = {
140 .reset_reg = AO_RTI_GEN_CNTL_REG0,
141 .num_reset = ARRAY_SIZE(axg_aoclk_reset),
142 .reset = axg_aoclk_reset,
143 .num_clks = ARRAY_SIZE(axg_aoclk_regmap),
144 .clks = axg_aoclk_regmap,
145 .hw_data = &axg_aoclk_onecell_data,
146};
147
148static const struct of_device_id axg_aoclkc_match_table[] = {
149 {
150 .compatible = "amlogic,meson-axg-aoclkc",
151 .data = &axg_aoclkc_data,
152 },
153 { }
154};
155
156static struct platform_driver axg_aoclkc_driver = {
157 .probe = meson_aoclkc_probe,
158 .driver = {
159 .name = "axg-aoclkc",
160 .of_match_table = axg_aoclkc_match_table,
161 },
162};
163
164builtin_platform_driver(axg_aoclkc_driver);
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
new file mode 100644
index 000000000000..91384d8dd844
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.h
@@ -0,0 +1,29 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2017 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 */
9
10#ifndef __AXG_AOCLKC_H
11#define __AXG_AOCLKC_H
12
13#define NR_CLKS 11
14/* AO Configuration Clock registers offsets
15 * Register offsets from the data sheet must be multiplied by 4.
16 */
17#define AO_RTI_PWR_CNTL_REG1 0x0C
18#define AO_RTI_PWR_CNTL_REG0 0x10
19#define AO_RTI_GEN_CNTL_REG0 0x40
20#define AO_OSCIN_CNTL 0x58
21#define AO_CRT_CLK_CNTL1 0x68
22#define AO_SAR_CLK 0x90
23#define AO_RTC_ALT_CLK_CNTL0 0x94
24#define AO_RTC_ALT_CLK_CNTL1 0x98
25
26#include <dt-bindings/clock/axg-aoclkc.h>
27#include <dt-bindings/reset/axg-aoclkc.h>
28
29#endif /* __AXG_AOCLKC_H */
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 9ec23ae9a219..408e3e2fca18 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -52,39 +52,12 @@
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */ 54 */
55#include <linux/clk-provider.h>
56#include <linux/of_address.h>
57#include <linux/platform_device.h> 55#include <linux/platform_device.h>
58#include <linux/reset-controller.h>
59#include <linux/mfd/syscon.h> 56#include <linux/mfd/syscon.h>
60#include <linux/regmap.h>
61#include <linux/init.h>
62#include <linux/delay.h>
63#include <dt-bindings/clock/gxbb-aoclkc.h>
64#include <dt-bindings/reset/gxbb-aoclkc.h>
65#include "clk-regmap.h" 57#include "clk-regmap.h"
58#include "meson-aoclk.h"
66#include "gxbb-aoclk.h" 59#include "gxbb-aoclk.h"
67 60
68struct gxbb_aoclk_reset_controller {
69 struct reset_controller_dev reset;
70 unsigned int *data;
71 struct regmap *regmap;
72};
73
74static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
75 unsigned long id)
76{
77 struct gxbb_aoclk_reset_controller *reset =
78 container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
79
80 return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
81 BIT(reset->data[id]));
82}
83
84static const struct reset_control_ops gxbb_aoclk_reset_ops = {
85 .reset = gxbb_aoclk_do_reset,
86};
87
88#define GXBB_AO_GATE(_name, _bit) \ 61#define GXBB_AO_GATE(_name, _bit) \
89static struct clk_regmap _name##_ao = { \ 62static struct clk_regmap _name##_ao = { \
90 .data = &(struct clk_regmap_gate_data) { \ 63 .data = &(struct clk_regmap_gate_data) { \
@@ -96,7 +69,7 @@ static struct clk_regmap _name##_ao = { \
96 .ops = &clk_regmap_gate_ops, \ 69 .ops = &clk_regmap_gate_ops, \
97 .parent_names = (const char *[]){ "clk81" }, \ 70 .parent_names = (const char *[]){ "clk81" }, \
98 .num_parents = 1, \ 71 .num_parents = 1, \
99 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ 72 .flags = CLK_IGNORE_UNUSED, \
100 }, \ 73 }, \
101} 74}
102 75
@@ -117,7 +90,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
117 }, 90 },
118}; 91};
119 92
120static unsigned int gxbb_aoclk_reset[] = { 93static const unsigned int gxbb_aoclk_reset[] = {
121 [RESET_AO_REMOTE] = 16, 94 [RESET_AO_REMOTE] = 16,
122 [RESET_AO_I2C_MASTER] = 18, 95 [RESET_AO_I2C_MASTER] = 18,
123 [RESET_AO_I2C_SLAVE] = 19, 96 [RESET_AO_I2C_SLAVE] = 19,
@@ -135,7 +108,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
135 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao, 108 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
136}; 109};
137 110
138static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = { 111static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
139 .hws = { 112 .hws = {
140 [CLKID_AO_REMOTE] = &remote_ao.hw, 113 [CLKID_AO_REMOTE] = &remote_ao.hw,
141 [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw, 114 [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
@@ -145,58 +118,55 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
145 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw, 118 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
146 [CLKID_AO_CEC_32K] = &cec_32k_ao.hw, 119 [CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
147 }, 120 },
148 .num = 7, 121 .num = NR_CLKS,
149}; 122};
150 123
151static int gxbb_aoclkc_probe(struct platform_device *pdev) 124static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
152{ 125{
153 struct gxbb_aoclk_reset_controller *rstc;
154 struct device *dev = &pdev->dev; 126 struct device *dev = &pdev->dev;
155 struct regmap *regmap; 127 struct regmap *regmap;
156 int ret, clkid; 128 int ret;
157
158 rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
159 if (!rstc)
160 return -ENOMEM;
161 129
162 regmap = syscon_node_to_regmap(of_get_parent(dev->of_node)); 130 regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
163 if (IS_ERR(regmap)) { 131 if (IS_ERR(regmap)) {
164 dev_err(dev, "failed to get regmap\n"); 132 dev_err(dev, "failed to get regmap\n");
165 return -ENODEV; 133 return PTR_ERR(regmap);
166 }
167
168 /* Reset Controller */
169 rstc->regmap = regmap;
170 rstc->data = gxbb_aoclk_reset;
171 rstc->reset.ops = &gxbb_aoclk_reset_ops;
172 rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
173 rstc->reset.of_node = dev->of_node;
174 ret = devm_reset_controller_register(dev, &rstc->reset);
175
176 /*
177 * Populate regmap and register all clks
178 */
179 for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
180 gxbb_aoclk_gate[clkid]->map = regmap;
181
182 ret = devm_clk_hw_register(dev,
183 gxbb_aoclk_onecell_data.hws[clkid]);
184 if (ret)
185 return ret;
186 } 134 }
187 135
188 /* Specific clocks */ 136 /* Specific clocks */
189 cec_32k_ao.regmap = regmap; 137 cec_32k_ao.regmap = regmap;
190 ret = devm_clk_hw_register(dev, &cec_32k_ao.hw); 138 ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
139 if (ret) {
140 dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
141 return ret;
142 }
143
144 return 0;
145}
146
147static const struct meson_aoclk_data gxbb_aoclkc_data = {
148 .reset_reg = AO_RTI_GEN_CNTL_REG0,
149 .num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
150 .reset = gxbb_aoclk_reset,
151 .num_clks = ARRAY_SIZE(gxbb_aoclk_gate),
152 .clks = gxbb_aoclk_gate,
153 .hw_data = &gxbb_aoclk_onecell_data,
154};
155
156static int gxbb_aoclkc_probe(struct platform_device *pdev)
157{
158 int ret = gxbb_register_cec_ao_32k(pdev);
191 if (ret) 159 if (ret)
192 return ret; 160 return ret;
193 161
194 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 162 return meson_aoclkc_probe(pdev);
195 &gxbb_aoclk_onecell_data);
196} 163}
197 164
198static const struct of_device_id gxbb_aoclkc_match_table[] = { 165static const struct of_device_id gxbb_aoclkc_match_table[] = {
199 { .compatible = "amlogic,meson-gx-aoclkc" }, 166 {
167 .compatible = "amlogic,meson-gx-aoclkc",
168 .data = &gxbb_aoclkc_data,
169 },
200 { } 170 { }
201}; 171};
202 172
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index 0be78383f257..65962fc9ecdc 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -8,6 +8,8 @@
8#ifndef __GXBB_AOCLKC_H 8#ifndef __GXBB_AOCLKC_H
9#define __GXBB_AOCLKC_H 9#define __GXBB_AOCLKC_H
10 10
11#define NR_CLKS 7
12
11/* AO Configuration Clock registers offsets */ 13/* AO Configuration Clock registers offsets */
12#define AO_RTI_PWR_CNTL_REG1 0x0c 14#define AO_RTI_PWR_CNTL_REG1 0x0c
13#define AO_RTI_PWR_CNTL_REG0 0x10 15#define AO_RTI_PWR_CNTL_REG0 0x10
@@ -28,4 +30,7 @@ struct aoclk_cec_32k {
28 30
29extern const struct clk_ops meson_aoclk_cec_32k_ops; 31extern const struct clk_ops meson_aoclk_cec_32k_ops;
30 32
33#include <dt-bindings/clock/gxbb-aoclkc.h>
34#include <dt-bindings/reset/gxbb-aoclkc.h>
35
31#endif /* __GXBB_AOCLKC_H */ 36#endif /* __GXBB_AOCLKC_H */
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index b1e4d9557610..a893b1edda22 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1543,6 +1543,102 @@ static struct clk_regmap gxbb_vapb = {
1543 }, 1543 },
1544}; 1544};
1545 1545
1546/* VDEC clocks */
1547
1548static const char * const gxbb_vdec_parent_names[] = {
1549 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1550};
1551
1552static struct clk_regmap gxbb_vdec_1_sel = {
1553 .data = &(struct clk_regmap_mux_data){
1554 .offset = HHI_VDEC_CLK_CNTL,
1555 .mask = 0x3,
1556 .shift = 9,
1557 .flags = CLK_MUX_ROUND_CLOSEST,
1558 },
1559 .hw.init = &(struct clk_init_data){
1560 .name = "vdec_1_sel",
1561 .ops = &clk_regmap_mux_ops,
1562 .parent_names = gxbb_vdec_parent_names,
1563 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1564 .flags = CLK_SET_RATE_PARENT,
1565 },
1566};
1567
1568static struct clk_regmap gxbb_vdec_1_div = {
1569 .data = &(struct clk_regmap_div_data){
1570 .offset = HHI_VDEC_CLK_CNTL,
1571 .shift = 0,
1572 .width = 7,
1573 },
1574 .hw.init = &(struct clk_init_data){
1575 .name = "vdec_1_div",
1576 .ops = &clk_regmap_divider_ops,
1577 .parent_names = (const char *[]){ "vdec_1_sel" },
1578 .num_parents = 1,
1579 .flags = CLK_SET_RATE_PARENT,
1580 },
1581};
1582
1583static struct clk_regmap gxbb_vdec_1 = {
1584 .data = &(struct clk_regmap_gate_data){
1585 .offset = HHI_VDEC_CLK_CNTL,
1586 .bit_idx = 8,
1587 },
1588 .hw.init = &(struct clk_init_data) {
1589 .name = "vdec_1",
1590 .ops = &clk_regmap_gate_ops,
1591 .parent_names = (const char *[]){ "vdec_1_div" },
1592 .num_parents = 1,
1593 .flags = CLK_SET_RATE_PARENT,
1594 },
1595};
1596
1597static struct clk_regmap gxbb_vdec_hevc_sel = {
1598 .data = &(struct clk_regmap_mux_data){
1599 .offset = HHI_VDEC2_CLK_CNTL,
1600 .mask = 0x3,
1601 .shift = 25,
1602 .flags = CLK_MUX_ROUND_CLOSEST,
1603 },
1604 .hw.init = &(struct clk_init_data){
1605 .name = "vdec_hevc_sel",
1606 .ops = &clk_regmap_mux_ops,
1607 .parent_names = gxbb_vdec_parent_names,
1608 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1609 .flags = CLK_SET_RATE_PARENT,
1610 },
1611};
1612
1613static struct clk_regmap gxbb_vdec_hevc_div = {
1614 .data = &(struct clk_regmap_div_data){
1615 .offset = HHI_VDEC2_CLK_CNTL,
1616 .shift = 16,
1617 .width = 7,
1618 },
1619 .hw.init = &(struct clk_init_data){
1620 .name = "vdec_hevc_div",
1621 .ops = &clk_regmap_divider_ops,
1622 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1623 .num_parents = 1,
1624 .flags = CLK_SET_RATE_PARENT,
1625 },
1626};
1627
1628static struct clk_regmap gxbb_vdec_hevc = {
1629 .data = &(struct clk_regmap_gate_data){
1630 .offset = HHI_VDEC2_CLK_CNTL,
1631 .bit_idx = 24,
1632 },
1633 .hw.init = &(struct clk_init_data) {
1634 .name = "vdec_hevc",
1635 .ops = &clk_regmap_gate_ops,
1636 .parent_names = (const char *[]){ "vdec_hevc_div" },
1637 .num_parents = 1,
1638 .flags = CLK_SET_RATE_PARENT,
1639 },
1640};
1641
1546/* Everything Else (EE) domain gates */ 1642/* Everything Else (EE) domain gates */
1547static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 1643static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1548static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 1644static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1786,6 +1882,12 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1786 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 1882 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1787 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 1883 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1788 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 1884 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
1885 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
1886 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
1887 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
1888 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
1889 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
1890 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
1789 [NR_CLKS] = NULL, 1891 [NR_CLKS] = NULL,
1790 }, 1892 },
1791 .num = NR_CLKS, 1893 .num = NR_CLKS,
@@ -1942,6 +2044,12 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1942 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2044 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1943 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2045 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1944 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2046 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
2047 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
2048 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
2049 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
2050 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
2051 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
2052 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
1945 [NR_CLKS] = NULL, 2053 [NR_CLKS] = NULL,
1946 }, 2054 },
1947 .num = NR_CLKS, 2055 .num = NR_CLKS,
@@ -2100,6 +2208,12 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
2100 &gxbb_fclk_div4, 2208 &gxbb_fclk_div4,
2101 &gxbb_fclk_div5, 2209 &gxbb_fclk_div5,
2102 &gxbb_fclk_div7, 2210 &gxbb_fclk_div7,
2211 &gxbb_vdec_1_sel,
2212 &gxbb_vdec_1_div,
2213 &gxbb_vdec_1,
2214 &gxbb_vdec_hevc_sel,
2215 &gxbb_vdec_hevc_div,
2216 &gxbb_vdec_hevc,
2103}; 2217};
2104 2218
2105struct clkc_data { 2219struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 9febf3f03739..b3ef54f65a9d 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -204,8 +204,12 @@
204#define CLKID_FCLK_DIV4_DIV 148 204#define CLKID_FCLK_DIV4_DIV 148
205#define CLKID_FCLK_DIV5_DIV 149 205#define CLKID_FCLK_DIV5_DIV 149
206#define CLKID_FCLK_DIV7_DIV 150 206#define CLKID_FCLK_DIV7_DIV 150
207#define CLKID_VDEC_1_SEL 151
208#define CLKID_VDEC_1_DIV 152
209#define CLKID_VDEC_HEVC_SEL 154
210#define CLKID_VDEC_HEVC_DIV 155
207 211
208#define NR_CLKS 151 212#define NR_CLKS 157
209 213
210/* include the CLKIDs that have been made part of the DT binding */ 214/* include the CLKIDs that have been made part of the DT binding */
211#include <dt-bindings/clock/gxbb-clkc.h> 215#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
new file mode 100644
index 000000000000..f965845917e3
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -0,0 +1,81 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Amlogic Meson-AXG Clock Controller Driver
4 *
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 *
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 * Author: Yixun Lan <yixun.lan@amlogic.com>
11 */
12
13#include <linux/platform_device.h>
14#include <linux/reset-controller.h>
15#include <linux/mfd/syscon.h>
16#include <linux/of_device.h>
17#include "clk-regmap.h"
18#include "meson-aoclk.h"
19
20static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
21 unsigned long id)
22{
23 struct meson_aoclk_reset_controller *rstc =
24 container_of(rcdev, struct meson_aoclk_reset_controller, reset);
25
26 return regmap_write(rstc->regmap, rstc->data->reset_reg,
27 BIT(rstc->data->reset[id]));
28}
29
30static const struct reset_control_ops meson_aoclk_reset_ops = {
31 .reset = meson_aoclk_do_reset,
32};
33
34int meson_aoclkc_probe(struct platform_device *pdev)
35{
36 struct meson_aoclk_reset_controller *rstc;
37 struct meson_aoclk_data *data;
38 struct device *dev = &pdev->dev;
39 struct regmap *regmap;
40 int ret, clkid;
41
42 data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
43 if (!data)
44 return -ENODEV;
45
46 rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
47 if (!rstc)
48 return -ENOMEM;
49
50 regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
51 if (IS_ERR(regmap)) {
52 dev_err(dev, "failed to get regmap\n");
53 return PTR_ERR(regmap);
54 }
55
56 /* Reset Controller */
57 rstc->data = data;
58 rstc->regmap = regmap;
59 rstc->reset.ops = &meson_aoclk_reset_ops;
60 rstc->reset.nr_resets = data->num_reset,
61 rstc->reset.of_node = dev->of_node;
62 ret = devm_reset_controller_register(dev, &rstc->reset);
63 if (ret) {
64 dev_err(dev, "failed to register reset controller\n");
65 return ret;
66 }
67
68 /*
69 * Populate regmap and register all clks
70 */
71 for (clkid = 0; clkid < data->num_clks; clkid++) {
72 data->clks[clkid]->map = regmap;
73
74 ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
75 if (ret)
76 return ret;
77 }
78
79 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
80 (void *) data->hw_data);
81}
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
new file mode 100644
index 000000000000..ab2819e88922
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -0,0 +1,34 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2017 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 * Author: Yixun Lan <yixun.lan@amlogic.com>
9 */
10
11#ifndef __MESON_AOCLK_H__
12#define __MESON_AOCLK_H__
13
14#include <linux/platform_device.h>
15#include <linux/reset-controller.h>
16#include "clk-regmap.h"
17
18struct meson_aoclk_data {
19 const unsigned int reset_reg;
20 const int num_reset;
21 const unsigned int *reset;
22 int num_clks;
23 struct clk_regmap **clks;
24 const struct clk_hw_onecell_data *hw_data;
25};
26
27struct meson_aoclk_reset_controller {
28 struct reset_controller_dev reset;
29 const struct meson_aoclk_data *data;
30 struct regmap *regmap;
31};
32
33int meson_aoclkc_probe(struct platform_device *pdev);
34#endif
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index cc2992493e0b..e6e9a9db1095 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -639,6 +639,54 @@ static struct clk_regmap meson8b_cpu_clk = {
639 }, 639 },
640}; 640};
641 641
642static struct clk_regmap meson8b_nand_clk_sel = {
643 .data = &(struct clk_regmap_mux_data){
644 .offset = HHI_NAND_CLK_CNTL,
645 .mask = 0x7,
646 .shift = 9,
647 .flags = CLK_MUX_ROUND_CLOSEST,
648 },
649 .hw.init = &(struct clk_init_data){
650 .name = "nand_clk_sel",
651 .ops = &clk_regmap_mux_ops,
652 /* FIXME all other parents are unknown: */
653 .parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
654 "fclk_div5", "fclk_div7", "xtal" },
655 .num_parents = 5,
656 .flags = CLK_SET_RATE_PARENT,
657 },
658};
659
660static struct clk_regmap meson8b_nand_clk_div = {
661 .data = &(struct clk_regmap_div_data){
662 .offset = HHI_NAND_CLK_CNTL,
663 .shift = 0,
664 .width = 7,
665 .flags = CLK_DIVIDER_ROUND_CLOSEST,
666 },
667 .hw.init = &(struct clk_init_data){
668 .name = "nand_clk_div",
669 .ops = &clk_regmap_divider_ops,
670 .parent_names = (const char *[]){ "nand_clk_sel" },
671 .num_parents = 1,
672 .flags = CLK_SET_RATE_PARENT,
673 },
674};
675
676static struct clk_regmap meson8b_nand_clk_gate = {
677 .data = &(struct clk_regmap_gate_data){
678 .offset = HHI_NAND_CLK_CNTL,
679 .bit_idx = 8,
680 },
681 .hw.init = &(struct clk_init_data){
682 .name = "nand_clk_gate",
683 .ops = &clk_regmap_gate_ops,
684 .parent_names = (const char *[]){ "nand_clk_div" },
685 .num_parents = 1,
686 .flags = CLK_SET_RATE_PARENT,
687 },
688};
689
642/* Everything Else (EE) domain gates */ 690/* Everything Else (EE) domain gates */
643 691
644static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); 692static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -834,6 +882,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
834 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 882 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
835 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 883 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
836 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 884 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
885 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
886 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
887 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
837 [CLK_NR_CLKS] = NULL, 888 [CLK_NR_CLKS] = NULL,
838 }, 889 },
839 .num = CLK_NR_CLKS, 890 .num = CLK_NR_CLKS,
@@ -939,6 +990,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
939 &meson8b_fclk_div4, 990 &meson8b_fclk_div4,
940 &meson8b_fclk_div5, 991 &meson8b_fclk_div5,
941 &meson8b_fclk_div7, 992 &meson8b_fclk_div7,
993 &meson8b_nand_clk_sel,
994 &meson8b_nand_clk_div,
995 &meson8b_nand_clk_gate,
942}; 996};
943 997
944static const struct meson8b_clk_reset_line { 998static const struct meson8b_clk_reset_line {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 6e414bd36981..a687dc60b6d0 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -40,6 +40,7 @@
40#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 40#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
41#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ 41#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
42#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 42#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
43#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
43#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 44#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
44#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 45#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
45#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 46#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
@@ -83,8 +84,10 @@
83#define CLKID_FCLK_DIV4_DIV 107 84#define CLKID_FCLK_DIV4_DIV 107
84#define CLKID_FCLK_DIV5_DIV 108 85#define CLKID_FCLK_DIV5_DIV 108
85#define CLKID_FCLK_DIV7_DIV 109 86#define CLKID_FCLK_DIV7_DIV 109
87#define CLKID_NAND_SEL 110
88#define CLKID_NAND_DIV 111
86 89
87#define CLK_NR_CLKS 110 90#define CLK_NR_CLKS 113
88 91
89/* 92/*
90 * include the CLKID and RESETID that have 93 * include the CLKID and RESETID that have
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..61955016a55b
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright (c) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 */
9
10#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
11#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
12
13#define CLKID_AO_REMOTE 0
14#define CLKID_AO_I2C_MASTER 1
15#define CLKID_AO_I2C_SLAVE 2
16#define CLKID_AO_UART1 3
17#define CLKID_AO_UART2 4
18#define CLKID_AO_IR_BLASTER 5
19#define CLKID_AO_SAR_ADC 6
20#define CLKID_AO_CLK81 7
21#define CLKID_AO_SAR_ADC_SEL 8
22#define CLKID_AO_SAR_ADC_DIV 9
23#define CLKID_AO_SAR_ADC_CLK 10
24#define CLKID_AO_ALT_XTAL 11
25
26#endif
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 8ba99a5e3fd3..7a892be90549 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -125,5 +125,7 @@
125#define CLKID_VAPB_1 138 125#define CLKID_VAPB_1 138
126#define CLKID_VAPB_SEL 139 126#define CLKID_VAPB_SEL 139
127#define CLKID_VAPB 140 127#define CLKID_VAPB 140
128#define CLKID_VDEC_1 153
129#define CLKID_VDEC_HEVC 156
128 130
129#endif /* __GXBB_CLKC_H */ 131#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index dea9d46d4fa7..a60f47b49231 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -102,5 +102,6 @@
102#define CLKID_MPLL0 93 102#define CLKID_MPLL0 93
103#define CLKID_MPLL1 94 103#define CLKID_MPLL1 94
104#define CLKID_MPLL2 95 104#define CLKID_MPLL2 95
105#define CLKID_NAND_CLK 112
105 106
106#endif /* __MESON8B_CLKC_H */ 107#endif /* __MESON8B_CLKC_H */
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..d342c0b6b2a7
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright (c) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 */
9
10#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
11#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
12
13#define RESET_AO_REMOTE 0
14#define RESET_AO_I2C_MASTER 1
15#define RESET_AO_I2C_SLAVE 2
16#define RESET_AO_UART1 3
17#define RESET_AO_UART2 4
18#define RESET_AO_IR_BLASTER 5
19
20#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 20:02:22 -0400