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authorIcenowy Zheng <icenowy@aosc.io>2017-04-07 12:19:03 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-04-10 03:04:23 -0400
commit37cabc74e57d15d683a8e49159bc8dcd5a50516a (patch)
treea7d3aa67743c32d2d6c719183b026c4e5fdc18a7
parentcb545960dea2749771c88b0cb26e5adfd12a0315 (diff)
clk: sunxi-ng: fix PRCM CCU ir clk parent
The first parent of ir clk in PRCM CCU is wrongly written as "osc32K" instead of "osc32k". Change it to "osc32k". Fixes: cdb8b80b6093 ("clk: sunxi-ng: add support for PRCM CCUs") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-r.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index 0d027d53dbdf..119f47b568ea 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -81,7 +81,7 @@ static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0",
81static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0", 81static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0",
82 0x28, BIT(7), 0); 82 0x28, BIT(7), 0);
83 83
84static const char * const r_mod0_default_parents[] = { "osc32K", "osc24M" }; 84static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
85static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", 85static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
86 r_mod0_default_parents, 0x54, 86 r_mod0_default_parents, 0x54,
87 0, 4, /* M */ 87 0, 4, /* M */