aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2013-06-25 16:43:28 -0400
committerOlof Johansson <olof@lixom.net>2013-06-25 16:43:28 -0400
commit37c5a9f7d73352650447c3984a39007304287303 (patch)
tree67b00299aa0e2bbe9b879ad957eff17bfed72e4e
parent2655e828350cc7558d1a74cd4464e34b81e17f36 (diff)
parent40e3e6725370481b7b81d969dbde056f50d870ae (diff)
Merge branch 'sti/soc' into next/late
From Srinivas Kandagatla <srinivas.kandagatla@st.com>: This patch-set adds basic support for STMicroelectronics STi series SOCs which includes STiH415 and STiH416 with B2000 and B2020 board support. STiH415 and STiH416 are dual-core ARM Cortex-A9 CPU, designed for use in Set-top-boxes. The SOC support is available in mach-sti which contains support code for STiH415, STiH416 SOCs including the generic board support. The reason for adding two SOCs at this patch set is to show that no new C code is required for second SOC(STiH416) support. * sti/soc: ARM: stih41x: Add B2020 board support ARM: stih41x: Add B2000 board support ARM: sti: Add DEBUG_LL console support ARM: sti: Add STiH416 SOC support ARM: sti: Add STiH415 SOC support Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/arm/sti/overview.txt33
-rw-r--r--Documentation/arm/sti/stih415-overview.txt12
-rw-r--r--Documentation/arm/sti/stih416-overview.txt12
-rw-r--r--MAINTAINERS9
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/Kconfig.debug35
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/st-pincfg.h71
-rw-r--r--arch/arm/boot/dts/stih415-b2000.dts15
-rw-r--r--arch/arm/boot/dts/stih415-b2020.dts15
-rw-r--r--arch/arm/boot/dts/stih415-clock.dtsi38
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi268
-rw-r--r--arch/arm/boot/dts/stih415.dtsi87
-rw-r--r--arch/arm/boot/dts/stih416-b2000.dts16
-rw-r--r--arch/arm/boot/dts/stih416-b2020.dts16
-rw-r--r--arch/arm/boot/dts/stih416-clock.dtsi41
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi295
-rw-r--r--arch/arm/boot/dts/stih416.dtsi96
-rw-r--r--arch/arm/boot/dts/stih41x-b2000.dtsi41
-rw-r--r--arch/arm/boot/dts/stih41x-b2020.dtsi42
-rw-r--r--arch/arm/boot/dts/stih41x.dtsi38
-rw-r--r--arch/arm/include/debug/sti.S61
-rw-r--r--arch/arm/mach-sti/Kconfig45
-rw-r--r--arch/arm/mach-sti/Makefile2
-rw-r--r--arch/arm/mach-sti/board-dt.c48
-rw-r--r--arch/arm/mach-sti/headsmp.S44
-rw-r--r--arch/arm/mach-sti/platsmp.c117
-rw-r--r--arch/arm/mach-sti/smp.h17
29 files changed, 1521 insertions, 0 deletions
diff --git a/Documentation/arm/sti/overview.txt b/Documentation/arm/sti/overview.txt
new file mode 100644
index 000000000000..1a4e93d6027f
--- /dev/null
+++ b/Documentation/arm/sti/overview.txt
@@ -0,0 +1,33 @@
1 STi ARM Linux Overview
2 ==========================
3
4Introduction
5------------
6
7 The ST Microelectronics Multimedia and Application Processors range of
8 CortexA9 System-on-Chip are supported by the 'STi' platform of
9 ARM Linux. Currently STiH415, STiH416 SOCs are supported with both
10 B2000 and B2020 Reference boards.
11
12
13 configuration
14 -------------
15
16 A generic configuration is provided for both STiH415/416, and can be used as the
17 default by
18 make stih41x_defconfig
19
20 Layout
21 ------
22 All the files for multiple machine families (STiH415, STiH416, and STiG125)
23 are located in the platform code contained in arch/arm/mach-sti
24
25 There is a generic board board-dt.c in the mach folder which support
26 Flattened Device Tree, which means, It works with any compatible board with
27 Device Trees.
28
29
30 Document Author
31 ---------------
32
33 Srinivas Kandagatla <srinivas.kandagatla@st.com>, (c) 2013 ST Microelectronics
diff --git a/Documentation/arm/sti/stih415-overview.txt b/Documentation/arm/sti/stih415-overview.txt
new file mode 100644
index 000000000000..1383e33f265d
--- /dev/null
+++ b/Documentation/arm/sti/stih415-overview.txt
@@ -0,0 +1,12 @@
1 STiH415 Overview
2 ================
3
4Introduction
5------------
6
7 The STiH415 is the next generation of HD, AVC set-top box processors
8 for satellite, cable, terrestrial and IP-STB markets.
9
10 Features
11 - ARM Cortex-A9 1.0 GHz, dual-core CPU
12 - SATA2x2,USB 2.0x3, PCIe, Gbit Ethernet MACx2
diff --git a/Documentation/arm/sti/stih416-overview.txt b/Documentation/arm/sti/stih416-overview.txt
new file mode 100644
index 000000000000..558444c201c6
--- /dev/null
+++ b/Documentation/arm/sti/stih416-overview.txt
@@ -0,0 +1,12 @@
1 STiH416 Overview
2 ================
3
4Introduction
5------------
6
7 The STiH416 is the next generation of HD, AVC set-top box processors
8 for satellite, cable, terrestrial and IP-STB markets.
9
10 Features
11 - ARM Cortex-A9 1.2 GHz dual core CPU
12 - SATA2x2,USB 2.0x3, PCIe, Gbit Ethernet MACx2
diff --git a/MAINTAINERS b/MAINTAINERS
index 5be702cc8449..599d50a8901e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1201,6 +1201,15 @@ M: Dinh Nguyen <dinguyen@altera.com>
1201S: Maintained 1201S: Maintained
1202F: drivers/clk/socfpga/ 1202F: drivers/clk/socfpga/
1203 1203
1204ARM/STI ARCHITECTURE
1205M: Srinivas Kandagatla <srinivas.kandagatla@st.com>
1206M: Stuart Menefy <stuart.menefy@st.com>
1207L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1208L: kernel@stlinux.com
1209W: http://www.stlinux.com
1210S: Maintained
1211F: arch/arm/mach-sti/
1212
1204ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT 1213ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
1205M: Lennert Buytenhek <kernel@wantstofly.org> 1214M: Lennert Buytenhek <kernel@wantstofly.org>
1206L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1215L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aa27704be4e4..9fbdc10fe835 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -991,6 +991,8 @@ source "arch/arm/mach-socfpga/Kconfig"
991 991
992source "arch/arm/mach-spear/Kconfig" 992source "arch/arm/mach-spear/Kconfig"
993 993
994source "arch/arm/mach-sti/Kconfig"
995
994source "arch/arm/mach-s3c24xx/Kconfig" 996source "arch/arm/mach-s3c24xx/Kconfig"
995 997
996if ARCH_S3C64XX 998if ARCH_S3C64XX
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index fe079417daa2..b3ae502427bf 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -497,6 +497,16 @@ choice
497 This option selects UART0 on VIA/Wondermedia System-on-a-chip 497 This option selects UART0 on VIA/Wondermedia System-on-a-chip
498 devices, including VT8500, WM8505, WM8650 and WM8850. 498 devices, including VT8500, WM8505, WM8650 and WM8850.
499 499
500 config DEBUG_STI_UART
501 depends on ARCH_STI
502 bool "Use StiH415/416 ASC for low-level debug"
503 help
504 Say Y here if you want kernel low-level debugging support
505 on StiH415/416 based platforms like B2000, B2020.
506 It support UART2 and SBC_UART1.
507
508 If unsure, say N.
509
500 config DEBUG_LL_UART_NONE 510 config DEBUG_LL_UART_NONE
501 bool "No low-level debugging UART" 511 bool "No low-level debugging UART"
502 depends on !ARCH_MULTIPLATFORM 512 depends on !ARCH_MULTIPLATFORM
@@ -631,6 +641,30 @@ choice
631 641
632endchoice 642endchoice
633 643
644choice
645 prompt "Low-level debug console UART"
646 depends on DEBUG_LL && DEBUG_STI_UART
647
648 config STIH41X_DEBUG_ASC2
649 bool "ASC2 UART"
650 help
651 Say Y here if you want kernel low-level debugging support
652 on STiH415/416 based platforms like b2000, which has
653 default UART wired up to ASC2.
654
655 If unsure, say N.
656
657 config STIH41X_DEBUG_SBC_ASC1
658 bool "SBC ASC1 UART"
659 help
660 Say Y here if you want kernel low-level debugging support
661 on STiH415/416 based platforms like b2020. which has
662 default UART wired up to SBC ASC1.
663
664 If unsure, say N.
665
666endchoice
667
634config DEBUG_LL_INCLUDE 668config DEBUG_LL_INCLUDE
635 string 669 string
636 default "debug/bcm2835.S" if DEBUG_BCM2835 670 default "debug/bcm2835.S" if DEBUG_BCM2835
@@ -657,6 +691,7 @@ config DEBUG_LL_INCLUDE
657 DEBUG_MMP_UART3 691 DEBUG_MMP_UART3
658 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 692 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
659 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART 693 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
694 default "debug/sti.S" if DEBUG_STI_UART
660 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 695 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
661 default "debug/tegra.S" if DEBUG_TEGRA_UART 696 default "debug/tegra.S" if DEBUG_TEGRA_UART
662 default "debug/ux500.S" if DEBUG_UX500_UART 697 default "debug/ux500.S" if DEBUG_UX500_UART
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b4615aa9bf7a..996bc6d20658 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -192,6 +192,7 @@ machine-$(CONFIG_ARCH_W90X900) += w90x900
192machine-$(CONFIG_FOOTBRIDGE) += footbridge 192machine-$(CONFIG_FOOTBRIDGE) += footbridge
193machine-$(CONFIG_ARCH_SOCFPGA) += socfpga 193machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
194machine-$(CONFIG_PLAT_SPEAR) += spear 194machine-$(CONFIG_PLAT_SPEAR) += spear
195machine-$(CONFIG_ARCH_STI) += sti
195machine-$(CONFIG_ARCH_VIRT) += virt 196machine-$(CONFIG_ARCH_VIRT) += virt
196machine-$(CONFIG_ARCH_ZYNQ) += zynq 197machine-$(CONFIG_ARCH_ZYNQ) += zynq
197machine-$(CONFIG_ARCH_SUNXI) += sunxi 198machine-$(CONFIG_ARCH_SUNXI) += sunxi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 60404661585d..3027d0e4aedd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -182,6 +182,10 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
182 spear320-evb.dtb \ 182 spear320-evb.dtb \
183 spear320-hmi.dtb 183 spear320-hmi.dtb
184dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 184dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
185dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
186 stih416-b2000.dtb \
187 stih415-b2020.dtb \
188 stih416-b2020.dtb
185dtb-$(CONFIG_ARCH_SUNXI) += \ 189dtb-$(CONFIG_ARCH_SUNXI) += \
186 sun4i-a10-cubieboard.dtb \ 190 sun4i-a10-cubieboard.dtb \
187 sun4i-a10-mini-xplus.dtb \ 191 sun4i-a10-mini-xplus.dtb \
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
new file mode 100644
index 000000000000..8c45d85ac13e
--- /dev/null
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -0,0 +1,71 @@
1#ifndef _ST_PINCFG_H_
2#define _ST_PINCFG_H_
3
4/* Alternate functions */
5#define ALT1 1
6#define ALT2 2
7#define ALT3 3
8#define ALT4 4
9#define ALT5 5
10#define ALT6 6
11#define ALT7 7
12
13/* Output enable */
14#define OE (1 << 27)
15/* Pull Up */
16#define PU (1 << 26)
17/* Open Drain */
18#define OD (1 << 26)
19#define RT (1 << 23)
20#define INVERTCLK (1 << 22)
21#define CLKNOTDATA (1 << 21)
22#define DOUBLE_EDGE (1 << 20)
23#define CLK_A (0 << 18)
24#define CLK_B (1 << 18)
25#define CLK_C (2 << 18)
26#define CLK_D (3 << 18)
27
28/* User-frendly defines for Pin Direction */
29 /* oe = 0, pu = 0, od = 0 */
30#define IN (0)
31 /* oe = 0, pu = 1, od = 0 */
32#define IN_PU (PU)
33 /* oe = 1, pu = 0, od = 0 */
34#define OUT (OE)
35 /* oe = 1, pu = 0, od = 1 */
36#define BIDIR (OE | OD)
37 /* oe = 1, pu = 1, od = 1 */
38#define BIDIR_PU (OE | PU | OD)
39
40/* RETIME_TYPE */
41/*
42 * B Mode
43 * Bypass retime with optional delay parameter
44 */
45#define BYPASS (0)
46/*
47 * R0, R1, R0D, R1D modes
48 * single-edge data non inverted clock, retime data with clk
49 */
50#define SE_NICLK_IO (RT)
51/*
52 * RIV0, RIV1, RIV0D, RIV1D modes
53 * single-edge data inverted clock, retime data with clk
54 */
55#define SE_ICLK_IO (RT | INVERTCLK)
56/*
57 * R0E, R1E, R0ED, R1ED modes
58 * double-edge data, retime data with clk
59 */
60#define DE_IO (RT | DOUBLE_EDGE)
61/*
62 * CIV0, CIV1 modes with inverted clock
63 * Retiming the clk pins will park clock & reduce the noise within the core.
64 */
65#define ICLK (RT | CLKNOTDATA | INVERTCLK)
66/*
67 * CLK0, CLK1 modes with non-inverted clock
68 * Retiming the clk pins will park clock & reduce the noise within the core.
69 */
70#define NICLK (RT | CLKNOTDATA)
71#endif /* _ST_PINCFG_H_ */
diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts
new file mode 100644
index 000000000000..d4af53160435
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2000.dts
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih415.dtsi"
11#include "stih41x-b2000.dtsi"
12/ {
13 model = "STiH415 B2000 Board";
14 compatible = "st,stih415", "st,stih415-b2000";
15};
diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 000000000000..442b019e9a3a
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih415.dtsi"
11#include "stih41x-b2020.dtsi"
12/ {
13 model = "STiH415 B2020 Board";
14 compatible = "st,stih415", "st,stih415-b2020";
15};
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
new file mode 100644
index 000000000000..174c799df741
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/ {
9 clocks {
10 /*
11 * Fixed 30MHz oscillator input to SoC
12 */
13 CLK_SYSIN: CLK_SYSIN {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <30000000>;
17 };
18
19 /*
20 * ARM Peripheral clock for timers
21 */
22 arm_periph_clk: arm_periph_clk {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <500000000>;
26 };
27
28 /*
29 * Bootloader initialized system infrastructure clock for
30 * serial devices.
31 */
32 CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
33 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 clock-frequency = <100000000>;
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
new file mode 100644
index 000000000000..1d322b24d1e4
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -0,0 +1,268 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10/ {
11
12 aliases {
13 gpio0 = &PIO0;
14 gpio1 = &PIO1;
15 gpio2 = &PIO2;
16 gpio3 = &PIO3;
17 gpio4 = &PIO4;
18 gpio5 = &PIO5;
19 gpio6 = &PIO6;
20 gpio7 = &PIO7;
21 gpio8 = &PIO8;
22 gpio9 = &PIO9;
23 gpio10 = &PIO10;
24 gpio11 = &PIO11;
25 gpio12 = &PIO12;
26 gpio13 = &PIO13;
27 gpio14 = &PIO14;
28 gpio15 = &PIO15;
29 gpio16 = &PIO16;
30 gpio17 = &PIO17;
31 gpio18 = &PIO18;
32 gpio19 = &PIO100;
33 gpio20 = &PIO101;
34 gpio21 = &PIO102;
35 gpio22 = &PIO103;
36 gpio23 = &PIO104;
37 gpio24 = &PIO105;
38 gpio25 = &PIO106;
39 gpio26 = &PIO107;
40 };
41
42 soc {
43 pin-controller-sbc {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "st,stih415-sbc-pinctrl";
47 st,syscfg = <&syscfg_sbc>;
48 ranges = <0 0xfe610000 0x5000>;
49
50 PIO0: gpio@fe610000 {
51 gpio-controller;
52 #gpio-cells = <1>;
53 reg = <0 0x100>;
54 st,bank-name = "PIO0";
55 };
56 PIO1: gpio@fe611000 {
57 gpio-controller;
58 #gpio-cells = <1>;
59 reg = <0x1000 0x100>;
60 st,bank-name = "PIO1";
61 };
62 PIO2: gpio@fe612000 {
63 gpio-controller;
64 #gpio-cells = <1>;
65 reg = <0x2000 0x100>;
66 st,bank-name = "PIO2";
67 };
68 PIO3: gpio@fe613000 {
69 gpio-controller;
70 #gpio-cells = <1>;
71 reg = <0x3000 0x100>;
72 st,bank-name = "PIO3";
73 };
74 PIO4: gpio@fe614000 {
75 gpio-controller;
76 #gpio-cells = <1>;
77 reg = <0x4000 0x100>;
78 st,bank-name = "PIO4";
79 };
80
81 sbc_serial1 {
82 pinctrl_sbc_serial1:sbc_serial1 {
83 st,pins {
84 tx = <&PIO2 6 ALT3 OUT>;
85 rx = <&PIO2 7 ALT3 IN>;
86 };
87 };
88 };
89 };
90
91 pin-controller-front {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "st,stih415-front-pinctrl";
95 st,syscfg = <&syscfg_front>;
96 ranges = <0 0xfee00000 0x8000>;
97
98 PIO5: gpio@fee00000 {
99 gpio-controller;
100 #gpio-cells = <1>;
101 reg = <0 0x100>;
102 st,bank-name = "PIO5";
103 };
104 PIO6: gpio@fee01000 {
105 gpio-controller;
106 #gpio-cells = <1>;
107 reg = <0x1000 0x100>;
108 st,bank-name = "PIO6";
109 };
110 PIO7: gpio@fee02000 {
111 gpio-controller;
112 #gpio-cells = <1>;
113 reg = <0x2000 0x100>;
114 st,bank-name = "PIO7";
115 };
116 PIO8: gpio@fee03000 {
117 gpio-controller;
118 #gpio-cells = <1>;
119 reg = <0x3000 0x100>;
120 st,bank-name = "PIO8";
121 };
122 PIO9: gpio@fee04000 {
123 gpio-controller;
124 #gpio-cells = <1>;
125 reg = <0x4000 0x100>;
126 st,bank-name = "PIO9";
127 };
128 PIO10: gpio@fee05000 {
129 gpio-controller;
130 #gpio-cells = <1>;
131 reg = <0x5000 0x100>;
132 st,bank-name = "PIO10";
133 };
134 PIO11: gpio@fee06000 {
135 gpio-controller;
136 #gpio-cells = <1>;
137 reg = <0x6000 0x100>;
138 st,bank-name = "PIO11";
139 };
140 PIO12: gpio@fee07000 {
141 gpio-controller;
142 #gpio-cells = <1>;
143 reg = <0x7000 0x100>;
144 st,bank-name = "PIO12";
145 };
146 };
147
148 pin-controller-rear {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "st,stih415-rear-pinctrl";
152 st,syscfg = <&syscfg_rear>;
153 ranges = <0 0xfe820000 0x8000>;
154
155 PIO13: gpio@fe820000 {
156 gpio-controller;
157 #gpio-cells = <1>;
158 reg = <0 0x100>;
159 st,bank-name = "PIO13";
160 };
161 PIO14: gpio@fe821000 {
162 gpio-controller;
163 #gpio-cells = <1>;
164 reg = <0x1000 0x100>;
165 st,bank-name = "PIO14";
166 };
167 PIO15: gpio@fe822000 {
168 gpio-controller;
169 #gpio-cells = <1>;
170 reg = <0x2000 0x100>;
171 st,bank-name = "PIO15";
172 };
173 PIO16: gpio@fe823000 {
174 gpio-controller;
175 #gpio-cells = <1>;
176 reg = <0x3000 0x100>;
177 st,bank-name = "PIO16";
178 };
179 PIO17: gpio@fe824000 {
180 gpio-controller;
181 #gpio-cells = <1>;
182 reg = <0x4000 0x100>;
183 st,bank-name = "PIO17";
184 };
185 PIO18: gpio@fe825000 {
186 gpio-controller;
187 #gpio-cells = <1>;
188 reg = <0x5000 0x100>;
189 st,bank-name = "PIO18";
190 };
191
192 serial2 {
193 pinctrl_serial2: serial2-0 {
194 st,pins {
195 tx = <&PIO17 4 ALT2 OUT>;
196 rx = <&PIO17 5 ALT2 IN>;
197 };
198 };
199 };
200 };
201
202 pin-controller-left {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "st,stih415-left-pinctrl";
206 st,syscfg = <&syscfg_left>;
207 ranges = <0 0xfd6b0000 0x3000>;
208
209 PIO100: gpio@fd6b0000 {
210 gpio-controller;
211 #gpio-cells = <1>;
212 reg = <0 0x100>;
213 st,bank-name = "PIO100";
214 };
215 PIO101: gpio@fd6b1000 {
216 gpio-controller;
217 #gpio-cells = <1>;
218 reg = <0x1000 0x100>;
219 st,bank-name = "PIO101";
220 };
221 PIO102: gpio@fd6b2000 {
222 gpio-controller;
223 #gpio-cells = <1>;
224 reg = <0x2000 0x100>;
225 st,bank-name = "PIO102";
226 };
227 };
228
229 pin-controller-right {
230 #address-cells = <1>;
231 #size-cells = <1>;
232 compatible = "st,stih415-right-pinctrl";
233 st,syscfg = <&syscfg_right>;
234 ranges = <0 0xfd330000 0x5000>;
235
236 PIO103: gpio@fd330000 {
237 gpio-controller;
238 #gpio-cells = <1>;
239 reg = <0 0x100>;
240 st,bank-name = "PIO103";
241 };
242 PIO104: gpio@fd331000 {
243 gpio-controller;
244 #gpio-cells = <1>;
245 reg = <0x1000 0x100>;
246 st,bank-name = "PIO104";
247 };
248 PIO105: gpio@fd332000 {
249 gpio-controller;
250 #gpio-cells = <1>;
251 reg = <0x2000 0x100>;
252 st,bank-name = "PIO105";
253 };
254 PIO106: gpio@fd333000 {
255 gpio-controller;
256 #gpio-cells = <1>;
257 reg = <0x3000 0x100>;
258 st,bank-name = "PIO106";
259 };
260 PIO107: gpio@fd334000 {
261 gpio-controller;
262 #gpio-cells = <1>;
263 reg = <0x4000 0x100>;
264 st,bank-name = "PIO107";
265 };
266 };
267 };
268};
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
new file mode 100644
index 000000000000..74ab8ded4b49
--- /dev/null
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -0,0 +1,87 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih41x.dtsi"
10#include "stih415-clock.dtsi"
11#include "stih415-pinctrl.dtsi"
12/ {
13
14 L2: cache-controller {
15 compatible = "arm,pl310-cache";
16 reg = <0xfffe2000 0x1000>;
17 arm,data-latency = <3 2 2>;
18 arm,tag-latency = <1 1 1>;
19 cache-unified;
20 cache-level = <2>;
21 };
22
23 soc {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 interrupt-parent = <&intc>;
27 ranges;
28 compatible = "simple-bus";
29
30 syscfg_sbc: sbc-syscfg@fe600000{
31 compatible = "st,stih415-sbc-syscfg", "syscon";
32 reg = <0xfe600000 0xb4>;
33 };
34
35 syscfg_front: front-syscfg@fee10000{
36 compatible = "st,stih415-front-syscfg", "syscon";
37 reg = <0xfee10000 0x194>;
38 };
39
40 syscfg_rear: rear-syscfg@fe830000{
41 compatible = "st,stih415-rear-syscfg", "syscon";
42 reg = <0xfe830000 0x190>;
43 };
44
45 /* MPE syscfgs */
46 syscfg_left: left-syscfg@fd690000{
47 compatible = "st,stih415-left-syscfg", "syscon";
48 reg = <0xfd690000 0x78>;
49 };
50
51 syscfg_right: right-syscfg@fd320000{
52 compatible = "st,stih415-right-syscfg", "syscon";
53 reg = <0xfd320000 0x180>;
54 };
55
56 syscfg_system: system-syscfg@fdde0000 {
57 compatible = "st,stih415-system-syscfg", "syscon";
58 reg = <0xfdde0000 0x15c>;
59 };
60
61 syscfg_lpm: lpm-syscfg@fe4b5100{
62 compatible = "st,stih415-lpm-syscfg", "syscon";
63 reg = <0xfe4b5100 0x08>;
64 };
65
66 serial2: serial@fed32000 {
67 compatible = "st,asc";
68 status = "disabled";
69 reg = <0xfed32000 0x2c>;
70 interrupts = <0 197 0>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_serial2>;
73 clocks = <&CLKS_ICN_REG_0>;
74 };
75
76 /* SBC comms block ASCs in SASG1 */
77 sbc_serial1: serial@fe531000 {
78 compatible = "st,asc";
79 status = "disabled";
80 reg = <0xfe531000 0x2c>;
81 interrupts = <0 210 0>;
82 clocks = <&CLK_SYSIN>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_sbc_serial1>;
85 };
86 };
87};
diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts
new file mode 100644
index 000000000000..a5eb6eee10bf
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2000.dts
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih416.dtsi"
11#include "stih41x-b2000.dtsi"
12
13/ {
14 compatible = "st,stih416", "st,stih416-b2000";
15 model = "STiH416 B2000";
16};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
new file mode 100644
index 000000000000..276f28da573a
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih416.dtsi"
11#include "stih41x-b2020.dtsi"
12/ {
13 model = "STiH416 B2020";
14 compatible = "st,stih416", "st,stih416-b2020";
15
16};
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
new file mode 100644
index 000000000000..7026bf1158d8
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics R&D Limited
3 * <stlinux-devel@stlinux.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/ {
10 clocks {
11 /*
12 * Fixed 30MHz oscillator inputs to SoC
13 */
14 CLK_SYSIN: CLK_SYSIN {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <30000000>;
18 clock-output-names = "CLK_SYSIN";
19 };
20
21 /*
22 * ARM Peripheral clock for timers
23 */
24 arm_periph_clk: arm_periph_clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <600000000>;
28 };
29
30 /*
31 * Bootloader initialized system infrastructure clock for
32 * serial devices.
33 */
34 CLK_S_ICN_REG_0: clockgenA0@4 {
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <100000000>;
38 clock-output-names = "CLK_S_ICN_REG_0";
39 };
40 };
41};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
new file mode 100644
index 000000000000..957b21a71b4b
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -0,0 +1,295 @@
1
2/*
3 * Copyright (C) 2013 STMicroelectronics Limited.
4 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10#include "st-pincfg.h"
11/ {
12
13 aliases {
14 gpio0 = &PIO0;
15 gpio1 = &PIO1;
16 gpio2 = &PIO2;
17 gpio3 = &PIO3;
18 gpio4 = &PIO4;
19 gpio5 = &PIO40;
20 gpio6 = &PIO5;
21 gpio7 = &PIO6;
22 gpio8 = &PIO7;
23 gpio9 = &PIO8;
24 gpio10 = &PIO9;
25 gpio11 = &PIO10;
26 gpio12 = &PIO11;
27 gpio13 = &PIO12;
28 gpio14 = &PIO30;
29 gpio15 = &PIO31;
30 gpio16 = &PIO13;
31 gpio17 = &PIO14;
32 gpio18 = &PIO15;
33 gpio19 = &PIO16;
34 gpio20 = &PIO17;
35 gpio21 = &PIO18;
36 gpio22 = &PIO100;
37 gpio23 = &PIO101;
38 gpio24 = &PIO102;
39 gpio25 = &PIO103;
40 gpio26 = &PIO104;
41 gpio27 = &PIO105;
42 gpio28 = &PIO106;
43 gpio29 = &PIO107;
44 };
45
46 soc {
47 pin-controller-sbc {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stih416-sbc-pinctrl";
51 st,syscfg = <&syscfg_sbc>;
52 ranges = <0 0xfe610000 0x6000>;
53
54 PIO0: gpio@fe610000 {
55 gpio-controller;
56 #gpio-cells = <1>;
57 reg = <0 0x100>;
58 st,bank-name = "PIO0";
59 };
60 PIO1: gpio@fe611000 {
61 gpio-controller;
62 #gpio-cells = <1>;
63 reg = <0x1000 0x100>;
64 st,bank-name = "PIO1";
65 };
66 PIO2: gpio@fe612000 {
67 gpio-controller;
68 #gpio-cells = <1>;
69 reg = <0x2000 0x100>;
70 st,bank-name = "PIO2";
71 };
72 PIO3: gpio@fe613000 {
73 gpio-controller;
74 #gpio-cells = <1>;
75 reg = <0x3000 0x100>;
76 st,bank-name = "PIO3";
77 };
78 PIO4: gpio@fe614000 {
79 gpio-controller;
80 #gpio-cells = <1>;
81 reg = <0x4000 0x100>;
82 st,bank-name = "PIO4";
83 };
84 PIO40: gpio@fe615000 {
85 gpio-controller;
86 #gpio-cells = <1>;
87 reg = <0x5000 0x100>;
88 st,bank-name = "PIO40";
89 st,retime-pin-mask = <0x7f>;
90 };
91
92 sbc_serial1 {
93 pinctrl_sbc_serial1: sbc_serial1 {
94 st,pins {
95 tx = <&PIO2 6 ALT3 OUT>;
96 rx = <&PIO2 7 ALT3 IN>;
97 };
98 };
99 };
100 };
101
102 pin-controller-front {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "st,stih416-front-pinctrl";
106 st,syscfg = <&syscfg_front>;
107 ranges = <0 0xfee00000 0x10000>;
108
109 PIO5: gpio@fee00000 {
110 gpio-controller;
111 #gpio-cells = <1>;
112 reg = <0 0x100>;
113 st,bank-name = "PIO5";
114 };
115 PIO6: gpio@fee01000 {
116 gpio-controller;
117 #gpio-cells = <1>;
118 reg = <0x1000 0x100>;
119 st,bank-name = "PIO6";
120 };
121 PIO7: gpio@fee02000 {
122 gpio-controller;
123 #gpio-cells = <1>;
124 reg = <0x2000 0x100>;
125 st,bank-name = "PIO7";
126 };
127 PIO8: gpio@fee03000 {
128 gpio-controller;
129 #gpio-cells = <1>;
130 reg = <0x3000 0x100>;
131 st,bank-name = "PIO8";
132 };
133 PIO9: gpio@fee04000 {
134 gpio-controller;
135 #gpio-cells = <1>;
136 reg = <0x4000 0x100>;
137 st,bank-name = "PIO9";
138 };
139 PIO10: gpio@fee05000 {
140 gpio-controller;
141 #gpio-cells = <1>;
142 reg = <0x5000 0x100>;
143 st,bank-name = "PIO10";
144 };
145 PIO11: gpio@fee06000 {
146 gpio-controller;
147 #gpio-cells = <1>;
148 reg = <0x6000 0x100>;
149 st,bank-name = "PIO11";
150 };
151 PIO12: gpio@fee07000 {
152 gpio-controller;
153 #gpio-cells = <1>;
154 reg = <0x7000 0x100>;
155 st,bank-name = "PIO12";
156 };
157 PIO30: gpio@fee08000 {
158 gpio-controller;
159 #gpio-cells = <1>;
160 reg = <0x8000 0x100>;
161 st,bank-name = "PIO30";
162 };
163 PIO31: gpio@fee09000 {
164 gpio-controller;
165 #gpio-cells = <1>;
166 reg = <0x9000 0x100>;
167 st,bank-name = "PIO31";
168 };
169 };
170
171 pin-controller-rear {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 compatible = "st,stih416-rear-pinctrl";
175 st,syscfg = <&syscfg_rear>;
176 ranges = <0 0xfe820000 0x6000>;
177
178 PIO13: gpio@fe820000 {
179 gpio-controller;
180 #gpio-cells = <1>;
181 reg = <0 0x100>;
182 st,bank-name = "PIO13";
183 };
184 PIO14: gpio@fe821000 {
185 gpio-controller;
186 #gpio-cells = <1>;
187 reg = <0x1000 0x100>;
188 st,bank-name = "PIO14";
189 };
190 PIO15: gpio@fe822000 {
191 gpio-controller;
192 #gpio-cells = <1>;
193 reg = <0x2000 0x100>;
194 st,bank-name = "PIO15";
195 };
196 PIO16: gpio@fe823000 {
197 gpio-controller;
198 #gpio-cells = <1>;
199 reg = <0x3000 0x100>;
200 st,bank-name = "PIO16";
201 };
202 PIO17: gpio@fe824000 {
203 gpio-controller;
204 #gpio-cells = <1>;
205 reg = <0x4000 0x100>;
206 st,bank-name = "PIO17";
207 };
208 PIO18: gpio@fe825000 {
209 gpio-controller;
210 #gpio-cells = <1>;
211 reg = <0x5000 0x100>;
212 st,bank-name = "PIO18";
213 st,retime-pin-mask = <0xf>;
214 };
215
216 serial2 {
217 pinctrl_serial2: serial2-0 {
218 st,pins {
219 tx = <&PIO17 4 ALT2 OUT>;
220 rx = <&PIO17 5 ALT2 IN>;
221 output-enable = <&PIO11 3 ALT2 OUT>;
222 };
223 };
224 };
225 };
226
227 pin-controller-fvdp-fe {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "st,stih416-fvdp-fe-pinctrl";
231 st,syscfg = <&syscfg_fvdp_fe>;
232 ranges = <0 0xfd6b0000 0x3000>;
233
234 PIO100: gpio@fd6b0000 {
235 gpio-controller;
236 #gpio-cells = <1>;
237 reg = <0 0x100>;
238 st,bank-name = "PIO100";
239 };
240 PIO101: gpio@fd6b1000 {
241 gpio-controller;
242 #gpio-cells = <1>;
243 reg = <0x1000 0x100>;
244 st,bank-name = "PIO101";
245 };
246 PIO102: gpio@fd6b2000 {
247 gpio-controller;
248 #gpio-cells = <1>;
249 reg = <0x2000 0x100>;
250 st,bank-name = "PIO102";
251 };
252 };
253
254 pin-controller-fvdp-lite {
255 #address-cells = <1>;
256 #size-cells = <1>;
257 compatible = "st,stih416-fvdp-lite-pinctrl";
258 st,syscfg = <&syscfg_fvdp_lite>;
259 ranges = <0 0xfd330000 0x5000>;
260
261 PIO103: gpio@fd330000 {
262 gpio-controller;
263 #gpio-cells = <1>;
264 reg = <0 0x100>;
265 st,bank-name = "PIO103";
266 };
267 PIO104: gpio@fd331000 {
268 gpio-controller;
269 #gpio-cells = <1>;
270 reg = <0x1000 0x100>;
271 st,bank-name = "PIO104";
272 };
273 PIO105: gpio@fd332000 {
274 gpio-controller;
275 #gpio-cells = <1>;
276 reg = <0x2000 0x100>;
277 st,bank-name = "PIO105";
278 };
279 PIO106: gpio@fd333000 {
280 gpio-controller;
281 #gpio-cells = <1>;
282 reg = <0x3000 0x100>;
283 st,bank-name = "PIO106";
284 };
285
286 PIO107: gpio@fd334000 {
287 gpio-controller;
288 #gpio-cells = <1>;
289 reg = <0x4000 0x100>;
290 st,bank-name = "PIO107";
291 st,retime-pin-mask = <0xf>;
292 };
293 };
294 };
295};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
new file mode 100644
index 000000000000..3cecd9689a49
--- /dev/null
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -0,0 +1,96 @@
1/*
2 * Copyright (C) 2012 STMicroelectronics Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih41x.dtsi"
10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi"
12/ {
13 L2: cache-controller {
14 compatible = "arm,pl310-cache";
15 reg = <0xfffe2000 0x1000>;
16 arm,data-latency = <3 3 3>;
17 arm,tag-latency = <2 2 2>;
18 cache-unified;
19 cache-level = <2>;
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 interrupt-parent = <&intc>;
26 ranges;
27 compatible = "simple-bus";
28
29 syscfg_sbc:sbc-syscfg@fe600000{
30 compatible = "st,stih416-sbc-syscfg", "syscon";
31 reg = <0xfe600000 0x1000>;
32 };
33
34 syscfg_front:front-syscfg@fee10000{
35 compatible = "st,stih416-front-syscfg", "syscon";
36 reg = <0xfee10000 0x1000>;
37 };
38
39 syscfg_rear:rear-syscfg@fe830000{
40 compatible = "st,stih416-rear-syscfg", "syscon";
41 reg = <0xfe830000 0x1000>;
42 };
43
44 /* MPE */
45 syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
46 compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
47 reg = <0xfddf0000 0x1000>;
48 };
49
50 syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
51 compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
52 reg = <0xfd6a0000 0x1000>;
53 };
54
55 syscfg_cpu:cpu-syscfg@fdde0000{
56 compatible = "st,stih416-cpu-syscfg", "syscon";
57 reg = <0xfdde0000 0x1000>;
58 };
59
60 syscfg_compo:compo-syscfg@fd320000{
61 compatible = "st,stih416-compo-syscfg", "syscon";
62 reg = <0xfd320000 0x1000>;
63 };
64
65 syscfg_transport:transport-syscfg@fd690000{
66 compatible = "st,stih416-transport-syscfg", "syscon";
67 reg = <0xfd690000 0x1000>;
68 };
69
70 syscfg_lpm:lpm-syscfg@fe4b5100{
71 compatible = "st,stih416-lpm-syscfg", "syscon";
72 reg = <0xfe4b5100 0x8>;
73 };
74
75 serial2: serial@fed32000{
76 compatible = "st,asc";
77 status = "disabled";
78 reg = <0xfed32000 0x2c>;
79 interrupts = <0 197 0>;
80 clocks = <&CLK_S_ICN_REG_0>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_serial2>;
83 };
84
85 /* SBC_UART1 */
86 sbc_serial1: serial@fe531000 {
87 compatible = "st,asc";
88 status = "disabled";
89 reg = <0xfe531000 0x2c>;
90 interrupts = <0 210 0>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_sbc_serial1>;
93 clocks = <&CLK_SYSIN>;
94 };
95 };
96};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
new file mode 100644
index 000000000000..8e694d2b8f5b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/ {
10
11 memory{
12 device_type = "memory";
13 reg = <0x60000000 0x40000000>;
14 };
15
16 chosen {
17 bootargs = "console=ttyAS0,115200";
18 linux,stdout-path = &serial2;
19 };
20
21 aliases {
22 ttyAS0 = &serial2;
23 };
24
25 soc {
26 serial2: serial@fed32000 {
27 status = "okay";
28 };
29
30 leds {
31 compatible = "gpio-leds";
32 fp_led {
33 #gpio-cells = <1>;
34 label = "Front Panel LED";
35 gpios = <&PIO105 7>;
36 linux,default-trigger = "heartbeat";
37 };
38 };
39
40 };
41};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
new file mode 100644
index 000000000000..133e18143b1b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/ {
10 memory{
11 device_type = "memory";
12 reg = <0x40000000 0x80000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyAS0,115200";
17 linux,stdout-path = &sbc_serial1;
18 };
19
20 aliases {
21 ttyAS0 = &sbc_serial1;
22 };
23 soc {
24 sbc_serial1: serial@fe531000 {
25 status = "okay";
26 };
27
28 leds {
29 compatible = "gpio-leds";
30 red {
31 #gpio-cells = <1>;
32 label = "Front Panel LED";
33 gpios = <&PIO4 1>;
34 linux,default-trigger = "heartbeat";
35 };
36 green {
37 gpios = <&PIO4 7>;
38 default-state = "off";
39 };
40 };
41 };
42};
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi
new file mode 100644
index 000000000000..7321403cab8a
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x.dtsi
@@ -0,0 +1,38 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4
5 cpus {
6 #address-cells = <1>;
7 #size-cells = <0>;
8 cpu@0 {
9 compatible = "arm,cortex-a9";
10 reg = <0>;
11 };
12 cpu@1 {
13 compatible = "arm,cortex-a9";
14 reg = <1>;
15 };
16 };
17
18 intc: interrupt-controller@fffe1000 {
19 compatible = "arm,cortex-a9-gic";
20 #interrupt-cells = <3>;
21 interrupt-controller;
22 reg = <0xfffe1000 0x1000>,
23 <0xfffe0100 0x100>;
24 };
25
26 scu@fffe0000 {
27 compatible = "arm,cortex-a9-scu";
28 reg = <0xfffe0000 0x1000>;
29 };
30
31 timer@fffe0200 {
32 interrupt-parent = <&intc>;
33 compatible = "arm,cortex-a9-global-timer";
34 reg = <0xfffe0200 0x100>;
35 interrupts = <1 11 0x04>;
36 clocks = <&arm_periph_clk>;
37 };
38};
diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S
new file mode 100644
index 000000000000..e3aa58ff1776
--- /dev/null
+++ b/arch/arm/include/debug/sti.S
@@ -0,0 +1,61 @@
1/*
2 * arch/arm/include/debug/sti.S
3 *
4 * Debugging macro include header
5 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#define STIH41X_COMMS_BASE 0xfed00000
13#define STIH41X_ASC2_BASE (STIH41X_COMMS_BASE+0x32000)
14
15#define STIH41X_SBC_LPM_BASE 0xfe400000
16#define STIH41X_SBC_COMMS_BASE (STIH41X_SBC_LPM_BASE + 0x100000)
17#define STIH41X_SBC_ASC1_BASE (STIH41X_SBC_COMMS_BASE + 0x31000)
18
19
20#define VIRT_ADDRESS(x) (x - 0x1000000)
21
22#if IS_ENABLED(CONFIG_STIH41X_DEBUG_ASC2)
23#define DEBUG_LL_UART_BASE STIH41X_ASC2_BASE
24#endif
25
26#if IS_ENABLED(CONFIG_STIH41X_DEBUG_SBC_ASC1)
27#define DEBUG_LL_UART_BASE STIH41X_SBC_ASC1_BASE
28#endif
29
30#ifndef DEBUG_LL_UART_BASE
31#error "DEBUG UART is not Configured"
32#endif
33
34#define ASC_TX_BUF_OFF 0x04
35#define ASC_CTRL_OFF 0x0c
36#define ASC_STA_OFF 0x14
37
38#define ASC_STA_TX_FULL (1<<9)
39#define ASC_STA_TX_EMPTY (1<<1)
40
41
42 .macro addruart, rp, rv, tmp
43 ldr \rp, =DEBUG_LL_UART_BASE @ physical base
44 ldr \rv, =VIRT_ADDRESS(DEBUG_LL_UART_BASE) @ virt base
45 .endm
46
47 .macro senduart,rd,rx
48 strb \rd, [\rx, #ASC_TX_BUF_OFF]
49 .endm
50
51 .macro waituart,rd,rx
521001: ldr \rd, [\rx, #ASC_STA_OFF]
53 tst \rd, #ASC_STA_TX_FULL
54 bne 1001b
55 .endm
56
57 .macro busyuart,rd,rx
581001: ldr \rd, [\rx, #ASC_STA_OFF]
59 tst \rd, #ASC_STA_TX_EMPTY
60 beq 1001b
61 .endm
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
new file mode 100644
index 000000000000..d04e3bfe1918
--- /dev/null
+++ b/arch/arm/mach-sti/Kconfig
@@ -0,0 +1,45 @@
1menuconfig ARCH_STI
2 bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
3 select GENERIC_CLOCKEVENTS
4 select CLKDEV_LOOKUP
5 select ARM_GIC
6 select ARM_GLOBAL_TIMER
7 select PINCTRL
8 select PINCTRL_ST
9 select MFD_SYSCON
10 select MIGHT_HAVE_CACHE_L2X0
11 select HAVE_SMP
12 select HAVE_ARM_SCU if SMP
13 select ARCH_REQUIRE_GPIOLIB
14 select ARM_ERRATA_720789
15 select ARM_ERRATA_754322
16 select PL310_ERRATA_753970 if CACHE_PL310
17 select PL310_ERRATA_769419 if CACHE_PL310
18 help
19 Include support for STiH41x SOCs like STiH415/416 using the device tree
20 for discovery
21 More information at Documentation/arm/STiH41x and
22 at Documentation/devicetree
23
24
25if ARCH_STI
26
27config SOC_STIH415
28 bool "STiH415 STMicroelectronics Consumer Electronics family"
29 default y
30 help
31 This enables support for STMicroelectronics Digital Consumer
32 Electronics family StiH415 parts, primarily targetted at set-top-box
33 and other digital audio/video applications using Flattned Device
34 Trees.
35
36config SOC_STIH416
37 bool "STiH416 STMicroelectronics Consumer Electronics family"
38 default y
39 help
40 This enables support for STMicroelectronics Digital Consumer
41 Electronics family StiH416 parts, primarily targetted at set-top-box
42 and other digital audio/video applications using Flattened Device
43 Trees.
44
45endif
diff --git a/arch/arm/mach-sti/Makefile b/arch/arm/mach-sti/Makefile
new file mode 100644
index 000000000000..acb330916333
--- /dev/null
+++ b/arch/arm/mach-sti/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_SMP) += platsmp.o headsmp.o
2obj-$(CONFIG_ARCH_STI) += board-dt.o
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
new file mode 100644
index 000000000000..8fe6f0c46480
--- /dev/null
+++ b/arch/arm/mach-sti/board-dt.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author(s): Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/clocksource.h>
12#include <linux/irq.h>
13#include <asm/hardware/cache-l2x0.h>
14#include <asm/mach/arch.h>
15
16#include "smp.h"
17
18void __init stih41x_l2x0_init(void)
19{
20 u32 way_size = 0x4;
21 u32 aux_ctrl;
22 /* may be this can be encoded in macros like BIT*() */
23 aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
24 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
25 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
26 (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
27
28 l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
29}
30
31static void __init stih41x_timer_init(void)
32{
33 of_clk_init(NULL);
34 clocksource_of_init();
35 stih41x_l2x0_init();
36}
37
38static const char *stih41x_dt_match[] __initdata = {
39 "st,stih415",
40 "st,stih416",
41 NULL
42};
43
44DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
45 .init_time = stih41x_timer_init,
46 .smp = smp_ops(sti_smp_ops),
47 .dt_compat = stih41x_dt_match,
48MACHINE_END
diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S
new file mode 100644
index 000000000000..78ebc7559f53
--- /dev/null
+++ b/arch/arm/mach-sti/headsmp.S
@@ -0,0 +1,44 @@
1/*
2 * arch/arm/mach-sti/headsmp.S
3 *
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * http://www.st.com
6 *
7 * Cloned from linux/arch/arm/mach-vexpress/headsmp.S
8 *
9 * Copyright (c) 2003 ARM Limited
10 * All Rights Reserved
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/linkage.h>
17#include <linux/init.h>
18
19 __INIT
20
21/*
22 * ST specific entry point for secondary CPUs. This provides
23 * a "holding pen" into which all secondary cores are held until we're
24 * ready for them to initialise.
25 */
26ENTRY(sti_secondary_startup)
27 mrc p15, 0, r0, c0, c0, 5
28 and r0, r0, #15
29 adr r4, 1f
30 ldmia r4, {r5, r6}
31 sub r4, r4, r5
32 add r6, r6, r4
33pen: ldr r7, [r6]
34 cmp r7, r0
35 bne pen
36
37 /*
38 * we've been released from the holding pen: secondary_stack
39 * should now contain the SVC stack for this core
40 */
41 b secondary_startup
42
431: .long .
44 .long pen_release
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
new file mode 100644
index 000000000000..977a863468fc
--- /dev/null
+++ b/arch/arm/mach-sti/platsmp.c
@@ -0,0 +1,117 @@
1/*
2 * arch/arm/mach-sti/platsmp.c
3 *
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * http://www.st.com
6 *
7 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 *
9 * Copyright (C) 2002 ARM Ltd.
10 * All Rights Reserved
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/delay.h>
19#include <linux/smp.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23
24#include <asm/cacheflush.h>
25#include <asm/smp_plat.h>
26#include <asm/smp_scu.h>
27
28#include "smp.h"
29
30static void __cpuinit write_pen_release(int val)
31{
32 pen_release = val;
33 smp_wmb();
34 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
35 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
36}
37
38static DEFINE_SPINLOCK(boot_lock);
39
40void __cpuinit sti_secondary_init(unsigned int cpu)
41{
42 trace_hardirqs_off();
43
44 /*
45 * let the primary processor know we're out of the
46 * pen, then head off into the C entry point
47 */
48 write_pen_release(-1);
49
50 /*
51 * Synchronise with the boot thread.
52 */
53 spin_lock(&boot_lock);
54 spin_unlock(&boot_lock);
55}
56
57int __cpuinit sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
58{
59 unsigned long timeout;
60
61 /*
62 * set synchronisation state between this boot processor
63 * and the secondary one
64 */
65 spin_lock(&boot_lock);
66
67 /*
68 * The secondary processor is waiting to be released from
69 * the holding pen - release it, then wait for it to flag
70 * that it has been released by resetting pen_release.
71 *
72 * Note that "pen_release" is the hardware CPU ID, whereas
73 * "cpu" is Linux's internal ID.
74 */
75 write_pen_release(cpu_logical_map(cpu));
76
77 /*
78 * Send the secondary CPU a soft interrupt, thereby causing
79 * it to jump to the secondary entrypoint.
80 */
81 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
82
83 timeout = jiffies + (1 * HZ);
84 while (time_before(jiffies, timeout)) {
85 smp_rmb();
86 if (pen_release == -1)
87 break;
88
89 udelay(10);
90 }
91
92 /*
93 * now the secondary core is starting up let it run its
94 * calibrations, then wait for it to finish
95 */
96 spin_unlock(&boot_lock);
97
98 return pen_release != -1 ? -ENOSYS : 0;
99}
100
101void __init sti_smp_prepare_cpus(unsigned int max_cpus)
102{
103 void __iomem *scu_base = NULL;
104 struct device_node *np = of_find_compatible_node(
105 NULL, NULL, "arm,cortex-a9-scu");
106 if (np) {
107 scu_base = of_iomap(np, 0);
108 scu_enable(scu_base);
109 of_node_put(np);
110 }
111}
112
113struct smp_operations __initdata sti_smp_ops = {
114 .smp_prepare_cpus = sti_smp_prepare_cpus,
115 .smp_secondary_init = sti_secondary_init,
116 .smp_boot_secondary = sti_boot_secondary,
117};
diff --git a/arch/arm/mach-sti/smp.h b/arch/arm/mach-sti/smp.h
new file mode 100644
index 000000000000..1871b72b1a7e
--- /dev/null
+++ b/arch/arm/mach-sti/smp.h
@@ -0,0 +1,17 @@
1/*
2 * arch/arm/mach-sti/smp.h
3 *
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * http://www.st.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __MACH_STI_SMP_H
13#define __MACH_STI_SMP_H
14
15extern struct smp_operations sti_smp_ops;
16
17#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 22:34:03 -0400