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authorOlof Johansson <olof@lixom.net>2019-06-25 07:52:55 -0400
committerOlof Johansson <olof@lixom.net>2019-06-25 07:52:55 -0400
commit37937ee73ba4d24850df666261f5243d611d1cc5 (patch)
treea07606de112f1476d0c82cf1a43ad6c6766f370a
parent09253fccca37137afec66ca5b9470cd566186af7 (diff)
parent01407158e4c7a6ac646901b7b034b5a7d605b480 (diff)
Merge tag 'imx-dt64-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree changes for 5.3: - Add i.MX8MQ based Librem5 devkit support. - Add SNVS power key support for i.MX8MQ and i.MX8MM. - Add GPIO alias for imx8mq and i.MX8QXP. - A series from Daniel Baluta to add SAI devices and enable audio support for imx8mm-evk board. - Add DDR performance monitor unit support for i.MX8QXP. - Add irqsteer interrupt controller device for i.MX8MQ SoC. - Add CPU speed grading and all OPPs for i.MX8MM and i.MX8MQ. - Add OCOTP device node for i.MX8QXP. - Various device addition for LS1028A: SATA, qDMA, USB, Mali DP500 and temperature sensor. - Random minor coding style improvements. * tag 'imx-dt64-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (32 commits) arm64: dts: librem5: enable the SNVS power key arm64: dts: librem5: Limit the USB to 5V arm64: dts: imx8qxp: added ddr performance monitor nodes arm64: dts: imx8qxp: sort LSIO subsystem devices arm64: dts: imx8qxp: sort alias alphabetically arm64: dts: imx8qxp: Add lsio_mu13 node arm64: dts: imx8mm-evk: Enable audio codec wm8524 arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit arm64: dts: fsl: ls1028a: Add qDMA node arm64: dts: imx8mm: Enable SNVS power key according to board design arm64: dts: imx8mq-evk: Enable SNVS power key arm64: dts: ls1028a: add crypto node arm64: dts: ls1028a: Add temperature sensor node arm64: dts: imx8mm: Move gic node into soc node arm64: dts: imx8mm: Move usbphy out of soc node arm64: dts: imx8mm: Pass the 'ranges' property arm64: dts: imx8mm: Pass a unit name for the 'soc' node arm64: dts: fsl: imx8mq: add the snvs power key node arm64: dts: ls1028a: fix watchdog device node arm64: dts: ls1028a: Enable sata. ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm64/boot/dts/freescale/Makefile1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts20
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts20
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi136
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-evk.dts190
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm.dtsi144
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-evk.dts4
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts809
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq.dtsi60
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp.dtsi134
10 files changed, 1429 insertions, 89 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 0bd122f60549..c043aca66572 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
22 22
23dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb 23dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
24dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb 24dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
25dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
25dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb 26dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
26dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb 27dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
27dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb 28dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index b359068d9605..de6ef39f3118 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -17,6 +17,7 @@
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; 17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
18 18
19 aliases { 19 aliases {
20 crypto = &crypto;
20 gpio0 = &gpio1; 21 gpio0 = &gpio1;
21 gpio1 = &gpio2; 22 gpio1 = &gpio2;
22 gpio2 = &gpio3; 23 gpio2 = &gpio3;
@@ -47,6 +48,15 @@
47 regulator-always-on; 48 regulator-always-on;
48 }; 49 };
49 50
51 sb_3v3: regulator-sb3v3 {
52 compatible = "regulator-fixed";
53 regulator-name = "3v3_vbus";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59
50 sound { 60 sound {
51 compatible = "simple-audio-card"; 61 compatible = "simple-audio-card";
52 simple-audio-card,format = "i2s"; 62 simple-audio-card,format = "i2s";
@@ -117,6 +127,12 @@
117 #size-cells = <0>; 127 #size-cells = <0>;
118 reg = <0x3>; 128 reg = <0x3>;
119 129
130 temperature-sensor@4c {
131 compatible = "nxp,sa56004";
132 reg = <0x4c>;
133 vcc-supply = <&sb_3v3>;
134 };
135
120 rtc@51 { 136 rtc@51 {
121 compatible = "nxp,pcf2129"; 137 compatible = "nxp,pcf2129";
122 reg = <0x51>; 138 reg = <0x51>;
@@ -153,3 +169,7 @@
153&sai1 { 169&sai1 {
154 status = "okay"; 170 status = "okay";
155}; 171};
172
173&sata {
174 status = "okay";
175};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f9c272fb0738..9fb911317ecd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -16,6 +16,7 @@
16 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; 16 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
17 17
18 aliases { 18 aliases {
19 crypto = &crypto;
19 serial0 = &duart0; 20 serial0 = &duart0;
20 serial1 = &duart1; 21 serial1 = &duart1;
21 }; 22 };
@@ -43,6 +44,15 @@
43 regulator-always-on; 44 regulator-always-on;
44 }; 45 };
45 46
47 sb_3v3: regulator-sb3v3 {
48 compatible = "regulator-fixed";
49 regulator-name = "3v3_vbus";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-boot-on;
53 regulator-always-on;
54 };
55
46 sound { 56 sound {
47 compatible = "simple-audio-card"; 57 compatible = "simple-audio-card";
48 simple-audio-card,format = "i2s"; 58 simple-audio-card,format = "i2s";
@@ -115,6 +125,12 @@
115 #size-cells = <0>; 125 #size-cells = <0>;
116 reg = <0x3>; 126 reg = <0x3>;
117 127
128 temperature-sensor@4c {
129 compatible = "nxp,sa56004";
130 reg = <0x4c>;
131 vcc-supply = <&sb_3v3>;
132 };
133
118 rtc@51 { 134 rtc@51 {
119 compatible = "nxp,pcf2129"; 135 compatible = "nxp,pcf2129";
120 reg = <0x51>; 136 reg = <0x51>;
@@ -151,3 +167,7 @@
151&sai4 { 167&sai4 {
152 status = "okay"; 168 status = "okay";
153}; 169};
170
171&sata {
172 status = "okay";
173};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index b04581249f0b..8d03b9c950e1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -70,6 +70,27 @@
70 clock-output-names = "sysclk"; 70 clock-output-names = "sysclk";
71 }; 71 };
72 72
73 dpclk: clock-dp {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <27000000>;
77 clock-output-names= "dpclk";
78 };
79
80 aclk: clock-axi {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <650000000>;
84 clock-output-names= "aclk";
85 };
86
87 pclk: clock-apb {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <650000000>;
91 clock-output-names= "pclk";
92 };
93
73 reboot { 94 reboot {
74 compatible ="syscon-reboot"; 95 compatible ="syscon-reboot";
75 regmap = <&dcfg>; 96 regmap = <&dcfg>;
@@ -285,13 +306,24 @@
285 #interrupt-cells = <2>; 306 #interrupt-cells = <2>;
286 }; 307 };
287 308
288 wdog0: watchdog@23c0000 { 309 usb0: usb@3100000 {
289 compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt"; 310 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
290 reg = <0x0 0x23c0000 0x0 0x10000>; 311 reg = <0x0 0x3100000 0x0 0x10000>;
291 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 312 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clockgen 4 1>; 313 dr_mode = "host";
293 big-endian; 314 snps,dis_rxdet_inp3_quirk;
294 status = "disabled"; 315 snps,quirk-frame-length-adjustment = <0x20>;
316 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
317 };
318
319 usb1: usb@3110000 {
320 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
321 reg = <0x0 0x3110000 0x0 0x10000>;
322 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
323 dr_mode = "host";
324 snps,dis_rxdet_inp3_quirk;
325 snps,quirk-frame-length-adjustment = <0x20>;
326 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
295 }; 327 };
296 328
297 sata: sata@3200000 { 329 sata: sata@3200000 {
@@ -356,6 +388,79 @@
356 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 388 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
357 }; 389 };
358 390
391 crypto: crypto@8000000 {
392 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
393 fsl,sec-era = <10>;
394 #address-cells = <1>;
395 #size-cells = <1>;
396 ranges = <0x0 0x00 0x8000000 0x100000>;
397 reg = <0x00 0x8000000 0x0 0x100000>;
398 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
399 dma-coherent;
400
401 sec_jr0: jr@10000 {
402 compatible = "fsl,sec-v5.0-job-ring",
403 "fsl,sec-v4.0-job-ring";
404 reg = <0x10000 0x10000>;
405 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
406 };
407
408 sec_jr1: jr@20000 {
409 compatible = "fsl,sec-v5.0-job-ring",
410 "fsl,sec-v4.0-job-ring";
411 reg = <0x20000 0x10000>;
412 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
413 };
414
415 sec_jr2: jr@30000 {
416 compatible = "fsl,sec-v5.0-job-ring",
417 "fsl,sec-v4.0-job-ring";
418 reg = <0x30000 0x10000>;
419 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
420 };
421
422 sec_jr3: jr@40000 {
423 compatible = "fsl,sec-v5.0-job-ring",
424 "fsl,sec-v4.0-job-ring";
425 reg = <0x40000 0x10000>;
426 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
427 };
428 };
429
430 qdma: dma-controller@8380000 {
431 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
432 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
433 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
434 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
435 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-names = "qdma-error", "qdma-queue0",
441 "qdma-queue1", "qdma-queue2", "qdma-queue3";
442 dma-channels = <8>;
443 block-number = <1>;
444 block-offset = <0x10000>;
445 fsl,dma-queues = <2>;
446 status-sizes = <64>;
447 queue-sizes = <64 64>;
448 };
449
450 cluster1_core0_watchdog: watchdog@c000000 {
451 compatible = "arm,sp805", "arm,primecell";
452 reg = <0x0 0xc000000 0x0 0x1000>;
453 clocks = <&clockgen 4 15>, <&clockgen 4 15>;
454 clock-names = "apb_pclk", "wdog_clk";
455 };
456
457 cluster1_core1_watchdog: watchdog@c010000 {
458 compatible = "arm,sp805", "arm,primecell";
459 reg = <0x0 0xc010000 0x0 0x1000>;
460 clocks = <&clockgen 4 15>, <&clockgen 4 15>;
461 clock-names = "apb_pclk", "wdog_clk";
462 };
463
359 sai1: audio-controller@f100000 { 464 sai1: audio-controller@f100000 {
360 #sound-dai-cells = <0>; 465 #sound-dai-cells = <0>;
361 compatible = "fsl,vf610-sai"; 466 compatible = "fsl,vf610-sai";
@@ -433,4 +538,21 @@
433 }; 538 };
434 }; 539 };
435 }; 540 };
541
542 malidp0: display@f080000 {
543 compatible = "arm,mali-dp500";
544 reg = <0x0 0xf080000 0x0 0x10000>;
545 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
546 <0 223 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "DE", "SE";
548 clocks = <&dpclk>, <&aclk>, <&aclk>, <&pclk>;
549 clock-names = "pxlclk", "mclk", "aclk", "pclk";
550 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
551
552 port {
553 dp0_out: endpoint {
554
555 };
556 };
557 };
436}; 558};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index 2d5d89475b76..ee7f2b2fc1ff 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -37,6 +37,41 @@
37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
38 enable-active-high; 38 enable-active-high;
39 }; 39 };
40
41 wm8524: audio-codec {
42 #sound-dai-cells = <0>;
43 compatible = "wlf,wm8524";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpio_wlf>;
46 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
47 };
48
49 sound-wm8524 {
50 compatible = "simple-audio-card";
51 simple-audio-card,name = "wm8524-audio";
52 simple-audio-card,format = "i2s";
53 simple-audio-card,frame-master = <&cpudai>;
54 simple-audio-card,bitclock-master = <&cpudai>;
55 simple-audio-card,widgets =
56 "Line", "Left Line Out Jack",
57 "Line", "Right Line Out Jack";
58 simple-audio-card,routing =
59 "Left Line Out Jack", "LINEVOUTL",
60 "Right Line Out Jack", "LINEVOUTR";
61
62 cpudai: simple-audio-card,cpu {
63 sound-dai = <&sai3>;
64 };
65
66 simple-audio-card,codec {
67 sound-dai = <&wm8524>;
68 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
69 };
70 };
71};
72
73&A53_0 {
74 cpu-supply = <&buck2_reg>;
40}; 75};
41 76
42&fec1 { 77&fec1 {
@@ -61,6 +96,19 @@
61 }; 96 };
62}; 97};
63 98
99&sai3 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_sai3>;
102 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
103 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
104 assigned-clock-rates = <24576000>;
105 status = "okay";
106};
107
108&snvs_pwrkey {
109 status = "okay";
110};
111
64&uart2 { /* console */ 112&uart2 { /* console */
65 pinctrl-names = "default"; 113 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_uart2>; 114 pinctrl-0 = <&pinctrl_uart2>;
@@ -95,6 +143,120 @@
95 status = "okay"; 143 status = "okay";
96}; 144};
97 145
146&i2c1 {
147 clock-frequency = <400000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c1>;
150 status = "okay";
151
152 pmic@4b {
153 compatible = "rohm,bd71847";
154 reg = <0x4b>;
155 pinctrl-0 = <&pinctrl_pmic>;
156 interrupt-parent = <&gpio1>;
157 interrupts = <3 GPIO_ACTIVE_LOW>;
158 rohm,reset-snvs-powered;
159
160 regulators {
161 buck1_reg: BUCK1 {
162 regulator-name = "BUCK1";
163 regulator-min-microvolt = <700000>;
164 regulator-max-microvolt = <1300000>;
165 regulator-boot-on;
166 regulator-always-on;
167 regulator-ramp-delay = <1250>;
168 };
169
170 buck2_reg: BUCK2 {
171 regulator-name = "BUCK2";
172 regulator-min-microvolt = <700000>;
173 regulator-max-microvolt = <1300000>;
174 regulator-boot-on;
175 regulator-always-on;
176 regulator-ramp-delay = <1250>;
177 rohm,dvs-run-voltage = <1000000>;
178 rohm,dvs-idle-voltage = <900000>;
179 };
180
181 buck3_reg: BUCK3 {
182 // BUCK5 in datasheet
183 regulator-name = "BUCK3";
184 regulator-min-microvolt = <700000>;
185 regulator-max-microvolt = <1350000>;
186 regulator-boot-on;
187 regulator-always-on;
188 };
189
190 buck4_reg: BUCK4 {
191 // BUCK6 in datasheet
192 regulator-name = "BUCK4";
193 regulator-min-microvolt = <3000000>;
194 regulator-max-microvolt = <3300000>;
195 regulator-boot-on;
196 regulator-always-on;
197 };
198
199 buck5_reg: BUCK5 {
200 // BUCK7 in datasheet
201 regulator-name = "BUCK5";
202 regulator-min-microvolt = <1605000>;
203 regulator-max-microvolt = <1995000>;
204 regulator-boot-on;
205 regulator-always-on;
206 };
207
208 buck6_reg: BUCK6 {
209 // BUCK8 in datasheet
210 regulator-name = "BUCK6";
211 regulator-min-microvolt = <800000>;
212 regulator-max-microvolt = <1400000>;
213 regulator-boot-on;
214 regulator-always-on;
215 };
216
217 ldo1_reg: LDO1 {
218 regulator-name = "LDO1";
219 regulator-min-microvolt = <3000000>;
220 regulator-max-microvolt = <3300000>;
221 regulator-boot-on;
222 regulator-always-on;
223 };
224
225 ldo2_reg: LDO2 {
226 regulator-name = "LDO2";
227 regulator-min-microvolt = <900000>;
228 regulator-max-microvolt = <900000>;
229 regulator-boot-on;
230 regulator-always-on;
231 };
232
233 ldo3_reg: LDO3 {
234 regulator-name = "LDO3";
235 regulator-min-microvolt = <1800000>;
236 regulator-max-microvolt = <3300000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240
241 ldo4_reg: LDO4 {
242 regulator-name = "LDO4";
243 regulator-min-microvolt = <900000>;
244 regulator-max-microvolt = <1800000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248
249 ldo6_reg: LDO6 {
250 regulator-name = "LDO6";
251 regulator-min-microvolt = <900000>;
252 regulator-max-microvolt = <1800000>;
253 regulator-boot-on;
254 regulator-always-on;
255 };
256 };
257 };
258};
259
98&iomuxc { 260&iomuxc {
99 pinctrl-names = "default"; 261 pinctrl-names = "default";
100 262
@@ -124,12 +286,40 @@
124 >; 286 >;
125 }; 287 };
126 288
289 pinctrl_gpio_wlf: gpiowlfgrp {
290 fsl,pins = <
291 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
292 >;
293 };
294
295 pinctrl_i2c1: i2c1grp {
296 fsl,pins = <
297 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
298 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
299 >;
300 };
301
302 pinctrl_pmic: pmicirq {
303 fsl,pins = <
304 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
305 >;
306 };
307
127 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { 308 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
128 fsl,pins = < 309 fsl,pins = <
129 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 310 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
130 >; 311 >;
131 }; 312 };
132 313
314 pinctrl_sai3: sai3grp {
315 fsl,pins = <
316 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
317 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
318 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
319 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
320 >;
321 };
322
133 pinctrl_uart2: uart2grp { 323 pinctrl_uart2: uart2grp {
134 fsl,pins = < 324 fsl,pins = <
135 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 325 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a357d82b2833..232a7412755a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -53,6 +53,8 @@
53 enable-method = "psci"; 53 enable-method = "psci";
54 next-level-cache = <&A53_L2>; 54 next-level-cache = <&A53_L2>;
55 operating-points-v2 = <&a53_opp_table>; 55 operating-points-v2 = <&a53_opp_table>;
56 nvmem-cells = <&cpu_speed_grade>;
57 nvmem-cell-names = "speed_grade";
56 }; 58 };
57 59
58 A53_1: cpu@1 { 60 A53_1: cpu@1 {
@@ -100,14 +102,23 @@
100 opp-1200000000 { 102 opp-1200000000 {
101 opp-hz = /bits/ 64 <1200000000>; 103 opp-hz = /bits/ 64 <1200000000>;
102 opp-microvolt = <850000>; 104 opp-microvolt = <850000>;
105 opp-supported-hw = <0xe>, <0x7>;
103 clock-latency-ns = <150000>; 106 clock-latency-ns = <150000>;
104 }; 107 };
105 108
106 opp-1600000000 { 109 opp-1600000000 {
107 opp-hz = /bits/ 64 <1600000000>; 110 opp-hz = /bits/ 64 <1600000000>;
108 opp-microvolt = <900000>; 111 opp-microvolt = <900000>;
112 opp-supported-hw = <0xc>, <0x7>;
113 clock-latency-ns = <150000>;
114 };
115
116 opp-1800000000 {
117 opp-hz = /bits/ 64 <1800000000>;
118 opp-microvolt = <1000000>;
119 /* Consumer only but rely on speed grading */
120 opp-supported-hw = <0x8>, <0x7>;
109 clock-latency-ns = <150000>; 121 clock-latency-ns = <150000>;
110 opp-suspend;
111 }; 122 };
112 }; 123 };
113 124
@@ -158,15 +169,6 @@
158 clock-output-names = "clk_ext4"; 169 clock-output-names = "clk_ext4";
159 }; 170 };
160 171
161 gic: interrupt-controller@38800000 {
162 compatible = "arm,gic-v3";
163 reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
164 <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
165 #interrupt-cells = <3>;
166 interrupt-controller;
167 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
168 };
169
170 psci { 172 psci {
171 compatible = "arm,psci-1.0"; 173 compatible = "arm,psci-1.0";
172 method = "smc"; 174 method = "smc";
@@ -189,7 +191,23 @@
189 arm,no-tick-in-suspend; 191 arm,no-tick-in-suspend;
190 }; 192 };
191 193
192 soc { 194 usbphynop1: usbphynop1 {
195 compatible = "usb-nop-xceiv";
196 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
197 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
198 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
199 clock-names = "main_clk";
200 };
201
202 usbphynop2: usbphynop2 {
203 compatible = "usb-nop-xceiv";
204 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
205 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
206 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
207 clock-names = "main_clk";
208 };
209
210 soc@0 {
193 compatible = "simple-bus"; 211 compatible = "simple-bus";
194 #address-cells = <1>; 212 #address-cells = <1>;
195 #size-cells = <1>; 213 #size-cells = <1>;
@@ -199,7 +217,73 @@
199 compatible = "fsl,aips-bus", "simple-bus"; 217 compatible = "fsl,aips-bus", "simple-bus";
200 #address-cells = <1>; 218 #address-cells = <1>;
201 #size-cells = <1>; 219 #size-cells = <1>;
202 ranges; 220 ranges = <0x30000000 0x30000000 0x400000>;
221
222 sai1: sai@30010000 {
223 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
224 reg = <0x30010000 0x10000>;
225 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
227 <&clk IMX8MM_CLK_SAI1_ROOT>,
228 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
229 clock-names = "bus", "mclk1", "mclk2", "mclk3";
230 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
231 dma-names = "rx", "tx";
232 status = "disabled";
233 };
234
235 sai2: sai@30020000 {
236 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
237 reg = <0x30020000 0x10000>;
238 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
240 <&clk IMX8MM_CLK_SAI2_ROOT>,
241 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
242 clock-names = "bus", "mclk1", "mclk2", "mclk3";
243 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
244 dma-names = "rx", "tx";
245 status = "disabled";
246 };
247
248 sai3: sai@30030000 {
249 #sound-dai-cells = <0>;
250 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
251 reg = <0x30030000 0x10000>;
252 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
254 <&clk IMX8MM_CLK_SAI3_ROOT>,
255 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
256 clock-names = "bus", "mclk1", "mclk2", "mclk3";
257 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
258 dma-names = "rx", "tx";
259 status = "disabled";
260 };
261
262 sai5: sai@30050000 {
263 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
264 reg = <0x30050000 0x10000>;
265 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
267 <&clk IMX8MM_CLK_SAI5_ROOT>,
268 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
269 clock-names = "bus", "mclk1", "mclk2", "mclk3";
270 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
271 dma-names = "rx", "tx";
272 status = "disabled";
273 };
274
275 sai6: sai@30060000 {
276 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
277 reg = <0x30060000 0x10000>;
278 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
280 <&clk IMX8MM_CLK_SAI6_ROOT>,
281 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
282 clock-names = "bus", "mclk1", "mclk2", "mclk3";
283 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
284 dma-names = "rx", "tx";
285 status = "disabled";
286 };
203 287
204 gpio1: gpio@30200000 { 288 gpio1: gpio@30200000 {
205 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 289 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
@@ -324,6 +408,10 @@
324 /* For nvmem subnodes */ 408 /* For nvmem subnodes */
325 #address-cells = <1>; 409 #address-cells = <1>;
326 #size-cells = <1>; 410 #size-cells = <1>;
411
412 cpu_speed_grade: speed-grade@10 {
413 reg = <0x10 4>;
414 };
327 }; 415 };
328 416
329 anatop: anatop@30360000 { 417 anatop: anatop@30360000 {
@@ -351,6 +439,7 @@
351 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 439 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
352 linux,keycode = <KEY_POWER>; 440 linux,keycode = <KEY_POWER>;
353 wakeup-source; 441 wakeup-source;
442 status = "disabled";
354 }; 443 };
355 }; 444 };
356 445
@@ -376,7 +465,7 @@
376 compatible = "fsl,aips-bus", "simple-bus"; 465 compatible = "fsl,aips-bus", "simple-bus";
377 #address-cells = <1>; 466 #address-cells = <1>;
378 #size-cells = <1>; 467 #size-cells = <1>;
379 ranges; 468 ranges = <0x30400000 0x30400000 0x400000>;
380 469
381 pwm1: pwm@30660000 { 470 pwm1: pwm@30660000 {
382 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 471 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
@@ -427,7 +516,7 @@
427 compatible = "fsl,aips-bus", "simple-bus"; 516 compatible = "fsl,aips-bus", "simple-bus";
428 #address-cells = <1>; 517 #address-cells = <1>;
429 #size-cells = <1>; 518 #size-cells = <1>;
430 ranges; 519 ranges = <0x30800000 0x30800000 0x400000>;
431 520
432 ecspi1: spi@30820000 { 521 ecspi1: spi@30820000 {
433 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 522 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
@@ -646,7 +735,7 @@
646 compatible = "fsl,aips-bus", "simple-bus"; 735 compatible = "fsl,aips-bus", "simple-bus";
647 #address-cells = <1>; 736 #address-cells = <1>;
648 #size-cells = <1>; 737 #size-cells = <1>;
649 ranges; 738 ranges = <0x32c00000 0x32c00000 0x400000>;
650 739
651 usbotg1: usb@32e40000 { 740 usbotg1: usb@32e40000 {
652 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 741 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
@@ -663,14 +752,6 @@
663 status = "disabled"; 752 status = "disabled";
664 }; 753 };
665 754
666 usbphynop1: usbphynop1 {
667 compatible = "usb-nop-xceiv";
668 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
669 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
670 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
671 clock-names = "main_clk";
672 };
673
674 usbmisc1: usbmisc@32e40200 { 755 usbmisc1: usbmisc@32e40200 {
675 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 756 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
676 #index-cells = <1>; 757 #index-cells = <1>;
@@ -692,14 +773,6 @@
692 status = "disabled"; 773 status = "disabled";
693 }; 774 };
694 775
695 usbphynop2: usbphynop2 {
696 compatible = "usb-nop-xceiv";
697 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
698 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
699 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
700 clock-names = "main_clk";
701 };
702
703 usbmisc2: usbmisc@32e50200 { 776 usbmisc2: usbmisc@32e50200 {
704 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 777 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
705 #index-cells = <1>; 778 #index-cells = <1>;
@@ -736,5 +809,14 @@
736 dma-names = "rx-tx"; 809 dma-names = "rx-tx";
737 status = "disabled"; 810 status = "disabled";
738 }; 811 };
812
813 gic: interrupt-controller@38800000 {
814 compatible = "arm,gic-v3";
815 reg = <0x38800000 0x10000>, /* GIC Dist */
816 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
817 #interrupt-cells = <3>;
818 interrupt-controller;
819 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
820 };
739 }; 821 };
740}; 822};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index b2038be8bbd7..e3df9b8cd9ca 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -242,6 +242,10 @@
242 power-supply = <&sw1a_reg>; 242 power-supply = <&sw1a_reg>;
243}; 243};
244 244
245&snvs_pwrkey {
246 status = "okay";
247};
248
245&uart1 { 249&uart1 {
246 pinctrl-names = "default"; 250 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_uart1>; 251 pinctrl-0 = <&pinctrl_uart1>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
new file mode 100644
index 000000000000..5179e22f5126
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
@@ -0,0 +1,809 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 Purism SPC
4 */
5
6/dts-v1/;
7
8#include "dt-bindings/input/input.h"
9#include "dt-bindings/pwm/pwm.h"
10#include "dt-bindings/usb/pd.h"
11#include "imx8mq.dtsi"
12
13/ {
14 model = "Purism Librem 5 devkit";
15 compatible = "purism,librem5-devkit", "fsl,imx8mq";
16
17 backlight_dsi: backlight-dsi {
18 compatible = "pwm-backlight";
19 /* 200 Hz for the PAM2841 */
20 pwms = <&pwm1 0 5000000>;
21 brightness-levels = <0 100>;
22 num-interpolated-steps = <100>;
23 /* Default brightness level (index into the array defined by */
24 /* the "brightness-levels" property) */
25 default-brightness-level = <0>;
26 power-supply = <&reg_22v4_p>;
27 };
28
29 chosen {
30 stdout-path = &uart1;
31 };
32
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_gpio_keys>;
37
38 btn1 {
39 label = "VOL_UP";
40 gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
41 wakeup-source;
42 linux,code = <KEY_VOLUMEUP>;
43 };
44
45 btn2 {
46 label = "VOL_DOWN";
47 gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
48 wakeup-source;
49 linux,code = <KEY_VOLUMEDOWN>;
50 };
51
52 hp-det {
53 label = "HP_DET";
54 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
55 wakeup-source;
56 linux,code = <KEY_HP>;
57 };
58 };
59
60 leds {
61 compatible = "gpio-leds";
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_gpio_leds>;
64
65 led1 {
66 label = "LED 1";
67 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
68 default-state = "off";
69 };
70 };
71
72 pmic_osc: clock-pmic {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <32768>;
76 clock-output-names = "pmic_osc";
77 };
78
79 reg_1v8_p: regulator-1v8-p {
80 compatible = "regulator-fixed";
81 regulator-name = "1v8_p";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
84 vin-supply = <&reg_pwr_en>;
85 };
86
87 reg_2v8_p: regulator-2v8-p {
88 compatible = "regulator-fixed";
89 regulator-name = "2v8_p";
90 regulator-min-microvolt = <2800000>;
91 regulator-max-microvolt = <2800000>;
92 vin-supply = <&reg_pwr_en>;
93 };
94
95 reg_3v3_p: regulator-3v3-p {
96 compatible = "regulator-fixed";
97 regulator-name = "3v3_p";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 vin-supply = <&reg_pwr_en>;
101
102 regulator-state-mem {
103 regulator-on-in-suspend;
104 };
105 };
106
107 reg_5v_p: regulator-5v-p {
108 compatible = "regulator-fixed";
109 regulator-name = "5v_p";
110 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>;
112 vin-supply = <&reg_pwr_en>;
113
114 regulator-state-mem {
115 regulator-on-in-suspend;
116 };
117 };
118
119 reg_22v4_p: regulator-22v4-p {
120 compatible = "regulator-fixed";
121 regulator-name = "22v4_P";
122 regulator-min-microvolt = <22400000>;
123 regulator-max-microvolt = <22400000>;
124 vin-supply = <&reg_pwr_en>;
125 };
126
127 reg_pwr_en: regulator-pwr-en {
128 compatible = "regulator-fixed";
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_pwr_en>;
131 regulator-name = "PWR_EN";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
135 enable-active-high;
136 regulator-always-on;
137 };
138
139 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
140 compatible = "regulator-fixed";
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_usdhc2_pwr>;
143 regulator-name = "VSD_3V3";
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
146 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
147 enable-active-high;
148 regulator-always-on;
149 };
150
151 vibrator {
152 compatible = "gpio-vibrator";
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_haptic>;
155 enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
156 vcc-supply = <&reg_3v3_p>;
157 };
158
159 wifi_pwr_en: regulator-wifi-en {
160 compatible = "regulator-fixed";
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_wifi_pwr_en>;
163 regulator-name = "WIFI_EN";
164 regulator-min-microvolt = <3300000>;
165 regulator-max-microvolt = <3300000>;
166 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
167 enable-active-high;
168 regulator-always-on;
169 };
170};
171
172&clk {
173 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
174 assigned-clock-rates = <786432000>, <722534400>;
175};
176
177&fec1 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_fec1>;
180 phy-mode = "rgmii-id";
181 phy-handle = <&ethphy0>;
182 fsl,magic-packet;
183 phy-supply = <&reg_3v3_p>;
184 status = "okay";
185
186 mdio {
187 #address-cells = <1>;
188 #size-cells = <0>;
189
190 ethphy0: ethernet-phy@1 {
191 compatible = "ethernet-phy-ieee802.3-c22";
192 reg = <1>;
193 };
194 };
195};
196
197&i2c1 {
198 clock-frequency = <100000>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_i2c1>;
201 status = "okay";
202
203 pmic: pmic@4b {
204 compatible = "rohm,bd71837";
205 reg = <0x4b>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_pmic>;
208 clocks = <&pmic_osc>;
209 clock-names = "osc";
210 clock-output-names = "pmic_clk";
211 interrupt-parent = <&gpio1>;
212 interrupts = <3 GPIO_ACTIVE_LOW>;
213 interrupt-names = "irq";
214 rohm,reset-snvs-powered;
215
216 regulators {
217 buck1_reg: BUCK1 {
218 regulator-name = "buck1";
219 regulator-min-microvolt = <700000>;
220 regulator-max-microvolt = <1300000>;
221 regulator-boot-on;
222 regulator-ramp-delay = <1250>;
223 rohm,dvs-run-voltage = <900000>;
224 rohm,dvs-idle-voltage = <850000>;
225 rohm,dvs-suspend-voltage = <800000>;
226 };
227
228 buck2_reg: BUCK2 {
229 regulator-name = "buck2";
230 regulator-min-microvolt = <700000>;
231 regulator-max-microvolt = <1300000>;
232 regulator-boot-on;
233 regulator-ramp-delay = <1250>;
234 rohm,dvs-run-voltage = <1000000>;
235 rohm,dvs-idle-voltage = <900000>;
236 };
237
238 buck3_reg: BUCK3 {
239 regulator-name = "buck3";
240 regulator-min-microvolt = <700000>;
241 regulator-max-microvolt = <1300000>;
242 regulator-boot-on;
243 rohm,dvs-run-voltage = <1000000>;
244 };
245
246 buck4_reg: BUCK4 {
247 regulator-name = "buck4";
248 regulator-min-microvolt = <700000>;
249 regulator-max-microvolt = <1300000>;
250 rohm,dvs-run-voltage = <1000000>;
251 };
252
253 buck5_reg: BUCK5 {
254 regulator-name = "buck5";
255 regulator-min-microvolt = <700000>;
256 regulator-max-microvolt = <1350000>;
257 regulator-boot-on;
258 };
259
260 buck6_reg: BUCK6 {
261 regulator-name = "buck6";
262 regulator-min-microvolt = <3000000>;
263 regulator-max-microvolt = <3300000>;
264 regulator-boot-on;
265 };
266
267 buck7_reg: BUCK7 {
268 regulator-name = "buck7";
269 regulator-min-microvolt = <1605000>;
270 regulator-max-microvolt = <1995000>;
271 regulator-boot-on;
272 };
273
274 buck8_reg: BUCK8 {
275 regulator-name = "buck8";
276 regulator-min-microvolt = <800000>;
277 regulator-max-microvolt = <1400000>;
278 regulator-boot-on;
279 };
280
281 ldo1_reg: LDO1 {
282 regulator-name = "ldo1";
283 regulator-min-microvolt = <3000000>;
284 regulator-max-microvolt = <3300000>;
285 regulator-boot-on;
286 /* leave on for snvs power button */
287 regulator-always-on;
288 };
289
290 ldo2_reg: LDO2 {
291 regulator-name = "ldo2";
292 regulator-min-microvolt = <900000>;
293 regulator-max-microvolt = <900000>;
294 regulator-boot-on;
295 /* leave on for snvs power button */
296 regulator-always-on;
297 };
298
299 ldo3_reg: LDO3 {
300 regulator-name = "ldo3";
301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <3300000>;
303 regulator-boot-on;
304 };
305
306 ldo4_reg: LDO4 {
307 regulator-name = "ldo4";
308 regulator-min-microvolt = <900000>;
309 regulator-max-microvolt = <1800000>;
310 regulator-boot-on;
311 };
312
313 ldo5_reg: LDO5 {
314 regulator-name = "ldo5";
315 regulator-min-microvolt = <1800000>;
316 regulator-max-microvolt = <3300000>;
317 };
318
319 ldo6_reg: LDO6 {
320 regulator-name = "ldo6";
321 regulator-min-microvolt = <900000>;
322 regulator-max-microvolt = <1800000>;
323 regulator-boot-on;
324 };
325
326 ldo7_reg: LDO7 {
327 regulator-name = "ldo7";
328 regulator-min-microvolt = <1800000>;
329 regulator-max-microvolt = <3300000>;
330 regulator-boot-on;
331 };
332 };
333 };
334
335 typec_ptn5100: usb_typec@52 {
336 compatible = "nxp,ptn5110";
337 reg = <0x52>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_typec>;
340 interrupt-parent = <&gpio3>;
341 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
342
343 connector {
344 compatible = "usb-c-connector";
345 label = "USB-C";
346 data-role = "dual";
347 power-role = "dual";
348 try-power-role = "sink";
349 source-pdos = <PDO_FIXED(5000, 2000,
350 PDO_FIXED_USB_COMM |
351 PDO_FIXED_DUAL_ROLE |
352 PDO_FIXED_DATA_SWAP )>;
353 sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM |
354 PDO_FIXED_DUAL_ROLE |
355 PDO_FIXED_DATA_SWAP )
356 PDO_VAR(5000, 3000, 3000)>;
357 op-sink-microwatt = <10000000>;
358
359 ports {
360 #address-cells = <1>;
361 #size-cells = <0>;
362
363 port@0 {
364 reg = <0>;
365
366 usb_con_hs: endpoint {
367 remote-endpoint = <&typec_hs>;
368 };
369 };
370
371 port@1 {
372 reg = <1>;
373
374 usb_con_ss: endpoint {
375 remote-endpoint = <&typec_ss>;
376 };
377 };
378 };
379 };
380 };
381
382 rtc@68 {
383 compatible = "microcrystal,rv4162";
384 reg = <0x68>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_rtc>;
387 interrupt-parent = <&gpio4>;
388 interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
389 };
390
391 charger@6b { /* bq25896 */
392 compatible = "ti,bq25890";
393 reg = <0x6b>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_charger>;
396 interrupt-parent = <&gpio3>;
397 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
398 ti,battery-regulation-voltage = <4192000>; /* 4.192V */
399 ti,charge-current = <1600000>; /* 1.6A */
400 ti,termination-current = <66000>; /* 66mA */
401 ti,precharge-current = <130000>; /* 130mA */
402 ti,minimum-sys-voltage = <3000000>; /* 3V */
403 ti,boost-voltage = <5000000>; /* 5V */
404 ti,boost-max-current = <50000>; /* 50mA */
405 };
406};
407
408&i2c3 {
409 clock-frequency = <100000>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_i2c3>;
412 status = "okay";
413
414 magnetometer@1e {
415 compatible = "st,lsm9ds1-magn";
416 reg = <0x1e>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_imu>;
419 interrupt-parent = <&gpio3>;
420 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
421 vdd-supply = <&reg_3v3_p>;
422 vddio-supply = <&reg_3v3_p>;
423 };
424
425 touchscreen@5d {
426 compatible = "goodix,gt5688";
427 reg = <0x5d>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_ts>;
430 interrupt-parent = <&gpio3>;
431 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
432 reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
433 irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
434 touchscreen-size-x = <720>;
435 touchscreen-size-y = <1440>;
436 AVDD28-supply = <&reg_2v8_p>;
437 VDDIO-supply = <&reg_1v8_p>;
438 };
439};
440
441&iomuxc {
442 pinctrl_bl: blgrp {
443 fsl,pins = <
444 MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */
445 >;
446 };
447
448 pinctrl_bt: btgrp {
449 fsl,pins = <
450 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */
451 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */
452 >;
453 };
454
455 pinctrl_charger: chargergrp {
456 fsl,pins = <
457 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */
458 >;
459 };
460
461 pinctrl_fec1: fec1grp {
462 fsl,pins = <
463 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
464 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
465 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
466 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
467 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
468 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
469 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
470 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
471 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
472 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
473 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
474 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
475 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
476 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
477 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
478 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
479 >;
480 };
481
482 pinctrl_ts: tsgrp {
483 fsl,pins = <
484 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */
485 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */
486 >;
487 };
488
489 pinctrl_gpio_leds: gpioledgrp {
490 fsl,pins = <
491 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
492 >;
493 };
494
495 pinctrl_gpio_keys: gpiokeygrp {
496 fsl,pins = <
497 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
498 MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
499 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */
500 >;
501 };
502
503 pinctrl_haptic: hapticgrp {
504 fsl,pins = <
505 MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */
506 >;
507 };
508
509 pinctrl_i2c1: i2c1grp {
510 fsl,pins = <
511 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
512 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
513 >;
514 };
515
516 pinctrl_i2c3: i2c3grp {
517 fsl,pins = <
518 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
519 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
520 >;
521 };
522
523 pinctrl_imu: imugrp {
524 fsl,pins = <
525 MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */
526 >;
527 };
528
529 pinctrl_pmic: pmicgrp {
530 fsl,pins = <
531 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */
532 >;
533 };
534
535 pinctrl_pwr_en: pwrengrp {
536 fsl,pins = <
537 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
538 >;
539 };
540
541 pinctrl_rtc: rtcgrp {
542 fsl,pins = <
543 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */
544 >;
545 };
546
547 pinctrl_typec: typecgrp {
548 fsl,pins = <
549 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
550 MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
551 >;
552 };
553
554 pinctrl_uart1: uart1grp {
555 fsl,pins = <
556 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
557 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
558 >;
559 };
560
561 pinctrl_uart2: uart2grp {
562 fsl,pins = <
563 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
564 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
565 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
566 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
567 >;
568 };
569
570 pinctrl_uart3: uart3grp {
571 fsl,pins = <
572 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
573 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
574 >;
575 };
576
577 pinctrl_uart4: uart4grp {
578 fsl,pins = <
579 MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
580 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
581 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
582 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
583 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
584 >;
585 };
586
587 pinctrl_usdhc1: usdhc1grp {
588 fsl,pins = <
589 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
590 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
591 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
592 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
593 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
594 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
595 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
596 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
597 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
598 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
599 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
600 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
601 >;
602 };
603
604 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
605 fsl,pins = <
606 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
607 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
608 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
609 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
610 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
611 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
612 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
613 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
614 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
615 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
616 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
617 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
618 >;
619 };
620
621 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
622 fsl,pins = <
623 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
624 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
625 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
626 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
627 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
628 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
629 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
630 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
631 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
632 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
633 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
634 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
635 >;
636 };
637
638 pinctrl_usdhc2_pwr: usdhc2grppwr {
639 fsl,pins = <
640 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
641 >;
642 };
643
644 pinctrl_usdhc2_gpio: usdhc2grpgpio {
645 fsl,pins = <
646 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */
647 >;
648 };
649
650 pinctrl_usdhc2: usdhc2grp {
651 fsl,pins = <
652 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
653 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
654 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
655 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
656 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
657 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
658 >;
659 };
660
661 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
662 fsl,pins = <
663 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
664 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
665 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
666 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
667 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
668 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
669 >;
670 };
671
672 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
673 fsl,pins = <
674 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
675 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
676 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
677 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
678 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
679 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
680 >;
681 };
682
683 pinctrl_wdog: wdoggrp {
684 fsl,pins = <
685 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
686 >;
687 };
688
689 pinctrl_wifi_pwr_en: wifipwrengrp {
690 fsl,pins = <
691 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06
692 >;
693 };
694
695 pinctrl_wwan: wwangrp {
696 fsl,pins = <
697 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */
698 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
699 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
700 >;
701 };
702};
703
704&pgc_gpu {
705 power-supply = <&buck3_reg>;
706};
707
708&pgc_vpu {
709 power-supply = <&buck4_reg>;
710};
711
712&pwm1 {
713 pinctrl-names = "default";
714 pinctrl-0 = <&pinctrl_bl>;
715 status = "okay";
716};
717
718&snvs_pwrkey {
719 status = "okay";
720};
721
722&uart1 { /* console */
723 pinctrl-names = "default";
724 pinctrl-0 = <&pinctrl_uart1>;
725 status = "okay";
726};
727
728&uart3 { /* GNSS */
729 pinctrl-names = "default";
730 pinctrl-0 = <&pinctrl_uart3>;
731 status = "okay";
732};
733
734&uart4 { /* BT */
735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
737 uart-has-rtscts;
738 status = "okay";
739};
740
741&usb3_phy0 {
742 status = "okay";
743};
744
745&usb3_phy1 {
746 vbus-supply = <&reg_5v_p>;
747 status = "okay";
748};
749
750&usb_dwc3_0 {
751 #address-cells = <1>;
752 #size-cells = <0>;
753 dr_mode = "otg";
754 status = "okay";
755
756 port@0 {
757 reg = <0>;
758
759 typec_hs: endpoint {
760 remote-endpoint = <&usb_con_hs>;
761 };
762 };
763
764 port@1 {
765 reg = <1>;
766
767 typec_ss: endpoint {
768 remote-endpoint = <&usb_con_ss>;
769 };
770 };
771};
772
773&usb_dwc3_1 {
774 dr_mode = "host";
775 status = "okay";
776};
777
778&usdhc1 {
779 pinctrl-names = "default", "state_100mhz", "state_200mhz";
780 pinctrl-0 = <&pinctrl_usdhc1>;
781 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
782 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
783 bus-width = <8>;
784 non-removable;
785 status = "okay";
786};
787
788&usdhc2 {
789 pinctrl-names = "default", "state_100mhz", "state_200mhz";
790 pinctrl-0 = <&pinctrl_usdhc2>;
791 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
792 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
793 bus-width = <4>;
794 vmmc-supply = <&reg_usdhc2_vmmc>;
795 power-supply = <&wifi_pwr_en>;
796 non-removable;
797 disable-wp;
798 cap-sdio-irq;
799 keep-power-in-suspend;
800 wakeup-source;
801 status = "okay";
802};
803
804&wdog1 {
805 pinctrl-names = "default";
806 pinctrl-0 = <&pinctrl_wdog>;
807 fsl,ext-reset-output;
808 status = "okay";
809};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 72ee59885678..d09b808eff87 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -8,6 +8,7 @@
8#include <dt-bindings/power/imx8mq-power.h> 8#include <dt-bindings/power/imx8mq-power.h>
9#include <dt-bindings/reset/imx8mq-reset.h> 9#include <dt-bindings/reset/imx8mq-reset.h>
10#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/gpio.h>
11#include "dt-bindings/input/input.h"
11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/thermal/thermal.h> 13#include <dt-bindings/thermal/thermal.h>
13#include "imx8mq-pinfunc.h" 14#include "imx8mq-pinfunc.h"
@@ -19,6 +20,11 @@
19 #size-cells = <2>; 20 #size-cells = <2>;
20 21
21 aliases { 22 aliases {
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
22 i2c0 = &i2c1; 28 i2c0 = &i2c1;
23 i2c1 = &i2c2; 29 i2c1 = &i2c2;
24 i2c2 = &i2c3; 30 i2c2 = &i2c3;
@@ -95,6 +101,8 @@
95 next-level-cache = <&A53_L2>; 101 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>; 102 operating-points-v2 = <&a53_opp_table>;
97 #cooling-cells = <2>; 103 #cooling-cells = <2>;
104 nvmem-cells = <&cpu_speed_grade>;
105 nvmem-cell-names = "speed_grade";
98 }; 106 };
99 107
100 A53_1: cpu@1 { 108 A53_1: cpu@1 {
@@ -145,14 +153,32 @@
145 opp-800000000 { 153 opp-800000000 {
146 opp-hz = /bits/ 64 <800000000>; 154 opp-hz = /bits/ 64 <800000000>;
147 opp-microvolt = <900000>; 155 opp-microvolt = <900000>;
156 /* Industrial only */
157 opp-supported-hw = <0xf>, <0x4>;
158 clock-latency-ns = <150000>;
159 };
160
161 opp-1000000000 {
162 opp-hz = /bits/ 64 <1000000000>;
163 opp-microvolt = <900000>;
164 /* Consumer only */
165 opp-supported-hw = <0xe>, <0x3>;
148 clock-latency-ns = <150000>; 166 clock-latency-ns = <150000>;
149 }; 167 };
150 168
151 opp-1300000000 { 169 opp-1300000000 {
152 opp-hz = /bits/ 64 <1300000000>; 170 opp-hz = /bits/ 64 <1300000000>;
153 opp-microvolt = <1000000>; 171 opp-microvolt = <1000000>;
172 opp-supported-hw = <0xc>, <0x7>;
173 clock-latency-ns = <150000>;
174 };
175
176 opp-1500000000 {
177 opp-hz = /bits/ 64 <1500000000>;
178 opp-microvolt = <1000000>;
179 /* Consumer only but rely on speed grading */
180 opp-supported-hw = <0x8>, <0x7>;
154 clock-latency-ns = <150000>; 181 clock-latency-ns = <150000>;
155 opp-suspend;
156 }; 182 };
157 }; 183 };
158 184
@@ -415,6 +441,10 @@
415 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 441 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
416 #address-cells = <1>; 442 #address-cells = <1>;
417 #size-cells = <1>; 443 #size-cells = <1>;
444
445 cpu_speed_grade: speed-grade@10 {
446 reg = <0x10 4>;
447 };
418 }; 448 };
419 449
420 anatop: syscon@30360000 { 450 anatop: syscon@30360000 {
@@ -437,6 +467,14 @@
437 clock-names = "snvs-rtc"; 467 clock-names = "snvs-rtc";
438 }; 468 };
439 469
470 snvs_pwrkey: snvs-powerkey {
471 compatible = "fsl,sec-v4.0-pwrkey";
472 regmap = <&snvs>;
473 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
474 linux,keycode = <KEY_POWER>;
475 wakeup-source;
476 status = "disabled";
477 };
440 }; 478 };
441 479
442 clk: clock-controller@30380000 { 480 clk: clock-controller@30380000 {
@@ -817,6 +855,25 @@
817 }; 855 };
818 }; 856 };
819 857
858 bus@32c00000 { /* AIPS4 */
859 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
860 #address-cells = <1>;
861 #size-cells = <1>;
862 ranges = <0x32c00000 0x32c00000 0x400000>;
863
864 irqsteer: interrupt-controller@32e2d000 {
865 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
866 reg = <0x32e2d000 0x1000>;
867 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
869 clock-names = "ipg";
870 fsl,channel = <0>;
871 fsl,num-irqs = <64>;
872 interrupt-controller;
873 #interrupt-cells = <1>;
874 };
875 };
876
820 gpu: gpu@38000000 { 877 gpu: gpu@38000000 {
821 compatible = "vivante,gc"; 878 compatible = "vivante,gc";
822 reg = <0x38000000 0x40000>; 879 reg = <0x38000000 0x40000>;
@@ -905,7 +962,6 @@
905 status = "disabled"; 962 status = "disabled";
906 }; 963 };
907 964
908
909 pcie0: pcie@33800000 { 965 pcie0: pcie@33800000 {
910 compatible = "fsl,imx8mq-pcie"; 966 compatible = "fsl,imx8mq-pcie";
911 reg = <0x33800000 0x400000>, 967 reg = <0x33800000 0x400000>,
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 0683ee2a48ae..05fa0b7f36bb 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -17,11 +17,19 @@
17 #size-cells = <2>; 17 #size-cells = <2>;
18 18
19 aliases { 19 aliases {
20 gpio0 = &lsio_gpio0;
21 gpio1 = &lsio_gpio1;
22 gpio2 = &lsio_gpio2;
23 gpio3 = &lsio_gpio3;
24 gpio4 = &lsio_gpio4;
25 gpio5 = &lsio_gpio5;
26 gpio6 = &lsio_gpio6;
27 gpio7 = &lsio_gpio7;
20 mmc0 = &usdhc1; 28 mmc0 = &usdhc1;
21 mmc1 = &usdhc2; 29 mmc1 = &usdhc2;
22 mmc2 = &usdhc3; 30 mmc2 = &usdhc3;
23 serial0 = &adma_lpuart0;
24 mu1 = &lsio_mu1; 31 mu1 = &lsio_mu1;
32 serial0 = &adma_lpuart0;
25 }; 33 };
26 34
27 cpus { 35 cpus {
@@ -141,6 +149,12 @@
141 compatible = "fsl,imx8qxp-iomuxc"; 149 compatible = "fsl,imx8qxp-iomuxc";
142 }; 150 };
143 151
152 ocotp: imx8qx-ocotp {
153 compatible = "fsl,imx8qxp-scu-ocotp";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 };
157
144 pd: imx8qx-pd { 158 pd: imx8qx-pd {
145 compatible = "fsl,imx8qxp-scu-pd"; 159 compatible = "fsl,imx8qxp-scu-pd";
146 #power-domain-cells = <1>; 160 #power-domain-cells = <1>;
@@ -149,6 +163,11 @@
149 rtc: rtc { 163 rtc: rtc {
150 compatible = "fsl,imx8qxp-sc-rtc"; 164 compatible = "fsl,imx8qxp-sc-rtc";
151 }; 165 };
166
167 watchdog {
168 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
169 timeout-sec = <60>;
170 };
152 }; 171 };
153 172
154 timer { 173 timer {
@@ -378,56 +397,25 @@
378 }; 397 };
379 }; 398 };
380 399
381 lsio_subsys: bus@5d000000 { 400 ddr_subsyss: bus@5c000000 {
382 compatible = "simple-bus"; 401 compatible = "simple-bus";
383 #address-cells = <1>; 402 #address-cells = <1>;
384 #size-cells = <1>; 403 #size-cells = <1>;
385 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 404 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
386
387 lsio_lpcg: clock-controller@5d400000 {
388 compatible = "fsl,imx8qxp-lpcg-lsio";
389 reg = <0x5d400000 0x400000>;
390 #clock-cells = <1>;
391 };
392 405
393 lsio_mu0: mailbox@5d1b0000 { 406 ddr-pmu@5c020000 {
394 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 407 compatible = "fsl,imx8-ddr-pmu";
395 reg = <0x5d1b0000 0x10000>; 408 reg = <0x5c020000 0x10000>;
396 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 409 interrupt-parent = <&gic>;
397 #mbox-cells = <2>; 410 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
398 status = "disabled";
399 };
400
401 lsio_mu1: mailbox@5d1c0000 {
402 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
403 reg = <0x5d1c0000 0x10000>;
404 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
405 #mbox-cells = <2>;
406 };
407
408 lsio_mu2: mailbox@5d1d0000 {
409 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
410 reg = <0x5d1d0000 0x10000>;
411 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
412 #mbox-cells = <2>;
413 status = "disabled";
414 };
415
416 lsio_mu3: mailbox@5d1e0000 {
417 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
418 reg = <0x5d1e0000 0x10000>;
419 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
420 #mbox-cells = <2>;
421 status = "disabled";
422 }; 411 };
412 };
423 413
424 lsio_mu4: mailbox@5d1f0000 { 414 lsio_subsys: bus@5d000000 {
425 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 415 compatible = "simple-bus";
426 reg = <0x5d1f0000 0x10000>; 416 #address-cells = <1>;
427 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 417 #size-cells = <1>;
428 #mbox-cells = <2>; 418 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
429 status = "disabled";
430 };
431 419
432 lsio_gpio0: gpio@5d080000 { 420 lsio_gpio0: gpio@5d080000 {
433 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 421 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
@@ -516,10 +504,58 @@
516 #interrupt-cells = <2>; 504 #interrupt-cells = <2>;
517 power-domains = <&pd IMX_SC_R_GPIO_7>; 505 power-domains = <&pd IMX_SC_R_GPIO_7>;
518 }; 506 };
519 };
520 507
521 watchdog { 508 lsio_mu0: mailbox@5d1b0000 {
522 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 509 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
523 timeout-sec = <60>; 510 reg = <0x5d1b0000 0x10000>;
511 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
512 #mbox-cells = <2>;
513 status = "disabled";
514 };
515
516 lsio_mu1: mailbox@5d1c0000 {
517 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
518 reg = <0x5d1c0000 0x10000>;
519 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
520 #mbox-cells = <2>;
521 };
522
523 lsio_mu2: mailbox@5d1d0000 {
524 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
525 reg = <0x5d1d0000 0x10000>;
526 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
527 #mbox-cells = <2>;
528 status = "disabled";
529 };
530
531 lsio_mu3: mailbox@5d1e0000 {
532 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
533 reg = <0x5d1e0000 0x10000>;
534 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
535 #mbox-cells = <2>;
536 status = "disabled";
537 };
538
539 lsio_mu4: mailbox@5d1f0000 {
540 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
541 reg = <0x5d1f0000 0x10000>;
542 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
543 #mbox-cells = <2>;
544 status = "disabled";
545 };
546
547 lsio_mu13: mailbox@5d280000 {
548 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
549 reg = <0x5d280000 0x10000>;
550 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
551 #mbox-cells = <2>;
552 power-domains = <&pd IMX_SC_R_MU_13A>;
553 };
554
555 lsio_lpcg: clock-controller@5d400000 {
556 compatible = "fsl,imx8qxp-lpcg-lsio";
557 reg = <0x5d400000 0x400000>;
558 #clock-cells = <1>;
559 };
524 }; 560 };
525}; 561};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 10:12:02 -0400