Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull second batch of rockchip clk updates from Heiko Stuebner:

Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
and some more clock-ids.

* tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: include downstream muxes into fractional dividers on rk3368
  clk: rockchip: set the clock ids for RK3228 HDMI
  clk: rockchip: set the clock ids for RK3228 VOP
  clk: rockchip: add the tsadc clocks found on rk3228 SoCs
  clk: rockchip: add the new clock ids for RK3228 HDMI
  clk: rockchip: add the new clock ids for RK3228 VOP
  clk: rockchip: add id of the tsadc clock found on rk3228 SoCs
  clk: rockchip: fix coding style for clk-cpu.c
  clk: rockchip: don't return NULL when registering mmc branch fails
  clk: rockchip: don't return NULL when registering inverter fails
  clk: rockchip: check grf when waiting pll lock
  clk: rockchip: disable alt_parent clk in err cases when registering cpuclk

7 files changed, 95 insertions, 61 deletions

diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index d07374f48caf..4e73ed5cab58 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -116,7 +116,7 @@ static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
 
                 pr_debug("%s: setting reg 0x%x to 0x%x\n",
                          __func__, clksel->reg, clksel->val);
-                writel(clksel->val , cpuclk->reg_base + clksel->reg);
+                writel(clksel->val, cpuclk->reg_base + clksel->reg);
         }
 }
 
@@ -290,14 +290,14 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
                 pr_err("%s: could not lookup parent clock %s\n",
                        __func__, parent_names[0]);
                 ret = -EINVAL;
-                goto free_cpuclk;
+                goto free_alt_parent;
         }
 
         ret = clk_notifier_register(clk, &cpuclk->clk_nb);
         if (ret) {
                 pr_err("%s: failed to register clock notifier for %s\n",
                                 __func__, name);
-                goto free_cpuclk;
+                goto free_alt_parent;
         }
 
         if (nrates > 0) {
@@ -326,6 +326,8 @@ free_rate_table:
         kfree(cpuclk->rate_table);
 unregister_notifier:
         clk_notifier_unregister(clk, &cpuclk->clk_nb);
+free_alt_parent:
+        clk_disable_unprepare(cpuclk->alt_parent);
 free_cpuclk:
         kfree(cpuclk);
         return ERR_PTR(ret);
diff --git a/drivers/clk/rockchip/clk-inverter.c b/drivers/clk/rockchip/clk-inverter.c
index 7cbf43beb3c6..dcb6e37f3da1 100644
--- a/drivers/clk/rockchip/clk-inverter.c
+++ b/drivers/clk/rockchip/clk-inverter.c
@@ -90,7 +90,7 @@ struct clk *rockchip_clk_register_inverter(const char *name,
 
         inv_clock = kmalloc(sizeof(*inv_clock), GFP_KERNEL);
         if (!inv_clock)
-                return NULL;
+                return ERR_PTR(-ENOMEM);
 
         init.name = name;
         init.num_parents = num_parents;
@@ -106,11 +106,7 @@ struct clk *rockchip_clk_register_inverter(const char *name,
 
         clk = clk_register(NULL, &inv_clock->hw);
         if (IS_ERR(clk))
-                goto err_free;
+                kfree(inv_clock);
 
         return clk;
-
-err_free:
-        kfree(inv_clock);
-        return NULL;
 }
diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
index 2685644826a0..e0dc7e83403a 100644
--- a/drivers/clk/rockchip/clk-mmc-phase.c
+++ b/drivers/clk/rockchip/clk-mmc-phase.c
@@ -150,7 +150,7 @@ struct clk *rockchip_clk_register_mmc(const char *name,
 
         mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
         if (!mmc_clock)
-                return NULL;
+                return ERR_PTR(-ENOMEM);
 
         init.name = name;
         init.num_parents = num_parents;
@@ -172,11 +172,7 @@ struct clk *rockchip_clk_register_mmc(const char *name,
 
         clk = clk_register(NULL, &mmc_clock->hw);
         if (IS_ERR(clk))
-                goto err_free;
+                kfree(mmc_clock);
 
         return clk;
-
-err_free:
-        kfree(mmc_clock);
-        return NULL;
 }
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index b7e66c9dd9f2..5de797e34d54 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -94,6 +94,11 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
         unsigned int val;
         int delay = 24000000, ret;
 
+        if (IS_ERR(grf)) {
+                pr_err("%s: grf regmap not available\n", __func__);
+                return PTR_ERR(grf);
+        }
+
         while (delay > 0) {
                 ret = regmap_read(grf, pll->lock_offset, &val);
                 if (ret) {
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index c515915850a1..7702d2855e9c 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -285,7 +285,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
                         RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
                         RK2928_CLKGATE_CON(3), 5, GFLAGS),
 
-        GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
+        GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
                         RK2928_CLKGATE_CON(3), 7, GFLAGS),
 
         COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
@@ -364,11 +364,11 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
                         RK2928_CLKGATE_CON(3), 1, GFLAGS),
         MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
                         RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
-        DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0,
+        DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
                         RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
         DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
                         RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
-        MUX(0, "dclk_vop", mux_dclk_vop_p, 0,
+        MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
                         RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
 
         FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
@@ -424,7 +424,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
         GATE(0, "sclk_otgphy1", "xin24m", 0,
                         RK2928_CLKGATE_CON(1), 6, GFLAGS),
 
-        COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,
+        COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
                         RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
                         RK2928_CLKGATE_CON(2), 8, GFLAGS),
 
@@ -505,7 +505,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
         GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
         GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
 
-        GATE(0, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
+        GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
         GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
 
         GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
@@ -513,13 +513,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
 
         GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
         GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
-        GATE(0, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
+        GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
         GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
         GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
         GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
         GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
         GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
-        GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
+        GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
         GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
         GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
 
@@ -584,7 +584,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
         GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
         GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
         GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
-        GATE(0, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
+        GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
         GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
         GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
         GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
@@ -592,7 +592,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
 
         GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
         GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
-        GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
+        GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
         GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
         GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
 
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index c2b0421f2076..a2bb12200465 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -243,6 +243,34 @@ static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
         RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
 };
 
+static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
+        MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
+            RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
+        MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
+            RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata =
+        MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
+            RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata =
+        MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
+            RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata =
+        MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
+            RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3368_uart3_fracmux __initdata =
+        MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
+            RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3368_uart4_fracmux __initdata =
+        MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
+            RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
+
 static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
         /*
          * Clock-Architecture Diagram 2
@@ -339,11 +367,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
         COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
                         RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
                         RK3368_CLKGATE_CON(6), 1, GFLAGS),
-        COMPOSITE_FRAC(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(28), 0,
-                        RK3368_CLKGATE_CON(6), 2, GFLAGS),
-        MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(27), 8, 2, MFLAGS),
+        COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
+                          RK3368_CLKSEL_CON(28), 0,
+                          RK3368_CLKGATE_CON(6), 2, GFLAGS,
+                          &rk3368_i2s_8ch_fracmux),
         COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
                         RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
                         RK3368_CLKGATE_CON(6), 0, GFLAGS),
@@ -352,21 +379,21 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
         COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
                         RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
                         RK3368_CLKGATE_CON(6), 4, GFLAGS),
-        COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(32), 0,
-                        RK3368_CLKGATE_CON(6), 5, GFLAGS),
-        COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(31), 8, 2, MFLAGS,
-                        RK3368_CLKGATE_CON(6), 6, GFLAGS),
+        COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
+                          RK3368_CLKSEL_CON(32), 0,
+                          RK3368_CLKGATE_CON(6), 5, GFLAGS,
+                          &rk3368_spdif_8ch_fracmux),
+        GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
+             RK3368_CLKGATE_CON(6), 6, GFLAGS),
         COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
                         RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
                         RK3368_CLKGATE_CON(5), 13, GFLAGS),
-        COMPOSITE_FRAC(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(54), 0,
-                        RK3368_CLKGATE_CON(5), 14, GFLAGS),
-        COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(53), 8, 2, MFLAGS,
-                        RK3368_CLKGATE_CON(5), 15, GFLAGS),
+        COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
+                          RK3368_CLKSEL_CON(54), 0,
+                          RK3368_CLKGATE_CON(5), 14, GFLAGS,
+                          &rk3368_i2s_2ch_fracmux),
+        GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
+             RK3368_CLKGATE_CON(5), 15, GFLAGS),
 
         COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
                         RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
@@ -562,38 +589,34 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
         COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
                         RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
                         RK3368_CLKGATE_CON(2), 0, GFLAGS),
-        COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(34), 0,
-                        RK3368_CLKGATE_CON(2), 1, GFLAGS),
-        MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(33), 8, 2, MFLAGS),
+        COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
+                          RK3368_CLKSEL_CON(34), 0,
+                          RK3368_CLKGATE_CON(2), 1, GFLAGS,
+                          &rk3368_uart0_fracmux),
 
         COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
                         RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
                         RK3368_CLKGATE_CON(2), 2, GFLAGS),
-        COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(36), 0,
-                        RK3368_CLKGATE_CON(2), 3, GFLAGS),
-        MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(35), 8, 2, MFLAGS),
+        COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
+                          RK3368_CLKSEL_CON(36), 0,
+                          RK3368_CLKGATE_CON(2), 3, GFLAGS,
+                          &rk3368_uart1_fracmux),
 
         COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
                         RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
                         RK3368_CLKGATE_CON(2), 6, GFLAGS),
-        COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(40), 0,
-                        RK3368_CLKGATE_CON(2), 7, GFLAGS),
-        MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(39), 8, 2, MFLAGS),
+        COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
+                          RK3368_CLKSEL_CON(40), 0,
+                          RK3368_CLKGATE_CON(2), 7, GFLAGS,
+                          &rk3368_uart3_fracmux),
 
         COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
                         RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
                         RK3368_CLKGATE_CON(2), 8, GFLAGS),
-        COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(42), 0,
-                        RK3368_CLKGATE_CON(2), 9, GFLAGS),
-        MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
-                        RK3368_CLKSEL_CON(41), 8, 2, MFLAGS),
+        COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
+                          RK3368_CLKSEL_CON(42), 0,
+                          RK3368_CLKGATE_CON(2), 9, GFLAGS,
+                          &rk3368_uart4_fracmux),
 
         COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
                         RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index a78dd891e24a..5d43ed9b05ad 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -29,6 +29,7 @@
 #define SCLK_SDMMC              68
 #define SCLK_SDIO               69
 #define SCLK_EMMC               71
+#define SCLK_TSADC              72
 #define SCLK_UART0              77
 #define SCLK_UART1              78
 #define SCLK_UART2              79
@@ -49,10 +50,17 @@
 #define SCLK_SDMMC_SAMPLE       118
 #define SCLK_SDIO_SAMPLE        119
 #define SCLK_EMMC_SAMPLE        121
+#define SCLK_VOP                122
+#define SCLK_HDMI_HDCP          123
+
+/* dclk gates */
+#define DCLK_VOP                190
+#define DCLK_HDMI_PHY           191
 
 /* aclk gates */
 #define ACLK_DMAC               194
 #define ACLK_PERI               210
+#define ACLK_VOP                211
 
 /* pclk gates */
 #define PCLK_GPIO0              320
@@ -68,11 +76,15 @@
 #define PCLK_UART0              341
 #define PCLK_UART1              342
 #define PCLK_UART2              343
+#define PCLK_TSADC              344
 #define PCLK_PWM                350
 #define PCLK_TIMER              353
 #define PCLK_PERI               363
+#define PCLK_HDMI_CTRL          364
+#define PCLK_HDMI_PHY           365
 
 /* hclk gates */
+#define HCLK_VOP                452
 #define HCLK_NANDC              453
 #define HCLK_SDMMC              456
 #define HCLK_SDIO               457