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authorOak Zeng <Oak.Zeng@amd.com>2018-03-08 16:44:47 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-03-14 16:16:35 -0400
commit3760f76cbebb455deaaa3e64ad5feb25222e65a9 (patch)
treec4e56858d9d404e3975de7382f83b36ac6359b47
parente36ec85998d2ca1bf09bbd9fcb2e2df1e23c8388 (diff)
drm/amdgpu: Move IH clientid defs to separate file
This is preparation for sharing client ID definitions between amdgpu and amdkfd Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h43
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c4
-rwxr-xr-xdrivers/gpu/drm/amd/amdgpu/vce_v4_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vega10_ih.c4
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c8
-rw-r--r--drivers/gpu/drm/amd/include/soc15_ih_clientid.h70
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c6
12 files changed, 98 insertions, 67 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index b8a7dba69595..0e01f115bbe5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -25,51 +25,12 @@
25#define __AMDGPU_IH_H__ 25#define __AMDGPU_IH_H__
26 26
27#include <linux/chash.h> 27#include <linux/chash.h>
28#include "soc15_ih_clientid.h"
28 29
29struct amdgpu_device; 30struct amdgpu_device;
30 /*
31 * vega10+ IH clients
32 */
33enum amdgpu_ih_clientid
34{
35 AMDGPU_IH_CLIENTID_IH = 0x00,
36 AMDGPU_IH_CLIENTID_ACP = 0x01,
37 AMDGPU_IH_CLIENTID_ATHUB = 0x02,
38 AMDGPU_IH_CLIENTID_BIF = 0x03,
39 AMDGPU_IH_CLIENTID_DCE = 0x04,
40 AMDGPU_IH_CLIENTID_ISP = 0x05,
41 AMDGPU_IH_CLIENTID_PCIE0 = 0x06,
42 AMDGPU_IH_CLIENTID_RLC = 0x07,
43 AMDGPU_IH_CLIENTID_SDMA0 = 0x08,
44 AMDGPU_IH_CLIENTID_SDMA1 = 0x09,
45 AMDGPU_IH_CLIENTID_SE0SH = 0x0a,
46 AMDGPU_IH_CLIENTID_SE1SH = 0x0b,
47 AMDGPU_IH_CLIENTID_SE2SH = 0x0c,
48 AMDGPU_IH_CLIENTID_SE3SH = 0x0d,
49 AMDGPU_IH_CLIENTID_SYSHUB = 0x0e,
50 AMDGPU_IH_CLIENTID_THM = 0x0f,
51 AMDGPU_IH_CLIENTID_UVD = 0x10,
52 AMDGPU_IH_CLIENTID_VCE0 = 0x11,
53 AMDGPU_IH_CLIENTID_VMC = 0x12,
54 AMDGPU_IH_CLIENTID_XDMA = 0x13,
55 AMDGPU_IH_CLIENTID_GRBM_CP = 0x14,
56 AMDGPU_IH_CLIENTID_ATS = 0x15,
57 AMDGPU_IH_CLIENTID_ROM_SMUIO = 0x16,
58 AMDGPU_IH_CLIENTID_DF = 0x17,
59 AMDGPU_IH_CLIENTID_VCE1 = 0x18,
60 AMDGPU_IH_CLIENTID_PWR = 0x19,
61 AMDGPU_IH_CLIENTID_UTCL2 = 0x1b,
62 AMDGPU_IH_CLIENTID_EA = 0x1c,
63 AMDGPU_IH_CLIENTID_UTCL2LOG = 0x1d,
64 AMDGPU_IH_CLIENTID_MP0 = 0x1e,
65 AMDGPU_IH_CLIENTID_MP1 = 0x1f,
66
67 AMDGPU_IH_CLIENTID_MAX,
68
69 AMDGPU_IH_CLIENTID_VCN = AMDGPU_IH_CLIENTID_UVD
70};
71 31
72#define AMDGPU_IH_CLIENTID_LEGACY 0 32#define AMDGPU_IH_CLIENTID_LEGACY 0
33#define AMDGPU_IH_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
73 34
74#define AMDGPU_PAGEFAULT_HASH_BITS 8 35#define AMDGPU_PAGEFAULT_HASH_BITS 8
75struct amdgpu_retryfault_hashtable { 36struct amdgpu_retryfault_hashtable {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d73bbb092202..d1d2c27156b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1261,23 +1261,23 @@ static int gfx_v9_0_sw_init(void *handle)
1261 adev->gfx.mec.num_queue_per_pipe = 8; 1261 adev->gfx.mec.num_queue_per_pipe = 8;
1262 1262
1263 /* KIQ event */ 1263 /* KIQ event */
1264 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq); 1264 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1265 if (r) 1265 if (r)
1266 return r; 1266 return r;
1267 1267
1268 /* EOP Event */ 1268 /* EOP Event */
1269 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq); 1269 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1270 if (r) 1270 if (r)
1271 return r; 1271 return r;
1272 1272
1273 /* Privileged reg */ 1273 /* Privileged reg */
1274 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184, 1274 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 184,
1275 &adev->gfx.priv_reg_irq); 1275 &adev->gfx.priv_reg_irq);
1276 if (r) 1276 if (r)
1277 return r; 1277 return r;
1278 1278
1279 /* Privileged inst */ 1279 /* Privileged inst */
1280 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185, 1280 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 185,
1281 &adev->gfx.priv_inst_irq); 1281 &adev->gfx.priv_inst_irq);
1282 if (r) 1282 if (r)
1283 return r; 1283 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ceab14f16795..a70cbc45c4c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -861,9 +861,9 @@ static int gmc_v9_0_sw_init(void *handle)
861 } 861 }
862 862
863 /* This interrupt is VMC page fault.*/ 863 /* This interrupt is VMC page fault.*/
864 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, 864 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 0,
865 &adev->gmc.vm_fault); 865 &adev->gmc.vm_fault);
866 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0, 866 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 0,
867 &adev->gmc.vm_fault); 867 &adev->gmc.vm_fault);
868 868
869 if (r) 869 if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 8b47484e169a..8fb933c62cf5 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -329,11 +329,11 @@ int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev)
329{ 329{
330 int r; 330 int r;
331 331
332 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); 332 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
333 if (r) 333 if (r)
334 return r; 334 return r;
335 335
336 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); 336 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
337 if (r) { 337 if (r) {
338 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); 338 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
339 return r; 339 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 215743df0957..939f92b295a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1172,13 +1172,13 @@ static int sdma_v4_0_sw_init(void *handle)
1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1173 1173
1174 /* SDMA trap event */ 1174 /* SDMA trap event */
1175 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224, 1175 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224,
1176 &adev->sdma.trap_irq); 1176 &adev->sdma.trap_irq);
1177 if (r) 1177 if (r)
1178 return r; 1178 return r;
1179 1179
1180 /* SDMA trap event */ 1180 /* SDMA trap event */
1181 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224, 1181 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224,
1182 &adev->sdma.trap_irq); 1182 &adev->sdma.trap_irq);
1183 if (r) 1183 if (r)
1184 return r; 1184 return r;
@@ -1333,7 +1333,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1333{ 1333{
1334 DRM_DEBUG("IH: SDMA trap\n"); 1334 DRM_DEBUG("IH: SDMA trap\n");
1335 switch (entry->client_id) { 1335 switch (entry->client_id) {
1336 case AMDGPU_IH_CLIENTID_SDMA0: 1336 case SOC15_IH_CLIENTID_SDMA0:
1337 switch (entry->ring_id) { 1337 switch (entry->ring_id) {
1338 case 0: 1338 case 0:
1339 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1339 amdgpu_fence_process(&adev->sdma.instance[0].ring);
@@ -1349,7 +1349,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1349 break; 1349 break;
1350 } 1350 }
1351 break; 1351 break;
1352 case AMDGPU_IH_CLIENTID_SDMA1: 1352 case SOC15_IH_CLIENTID_SDMA1:
1353 switch (entry->ring_id) { 1353 switch (entry->ring_id) {
1354 case 0: 1354 case 0:
1355 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1355 amdgpu_fence_process(&adev->sdma.instance[1].ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index e54cc3ca2303..eddc57f3b72a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -390,13 +390,13 @@ static int uvd_v7_0_sw_init(void *handle)
390 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 390 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
391 391
392 /* UVD TRAP */ 392 /* UVD TRAP */
393 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, 124, &adev->uvd.irq); 393 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
394 if (r) 394 if (r)
395 return r; 395 return r;
396 396
397 /* UVD ENC TRAP */ 397 /* UVD ENC TRAP */
398 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 398 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
399 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq); 399 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
400 if (r) 400 if (r)
401 return r; 401 return r;
402 } 402 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 2329b310ccf2..73fd48d6c756 100755
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -420,7 +420,7 @@ static int vce_v4_0_sw_init(void *handle)
420 unsigned size; 420 unsigned size;
421 int r, i; 421 int r, i;
422 422
423 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCE0, 167, &adev->vce.irq); 423 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCE0, 167, &adev->vce.irq);
424 if (r) 424 if (r)
425 return r; 425 return r;
426 426
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index fdf4ac9313cf..8c132673bc79 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -75,13 +75,13 @@ static int vcn_v1_0_sw_init(void *handle)
75 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 75 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
76 76
77 /* VCN DEC TRAP */ 77 /* VCN DEC TRAP */
78 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, 124, &adev->vcn.irq); 78 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 124, &adev->vcn.irq);
79 if (r) 79 if (r)
80 return r; 80 return r;
81 81
82 /* VCN ENC TRAP */ 82 /* VCN ENC TRAP */
83 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 83 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
84 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, i + 119, 84 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + 119,
85 &adev->vcn.irq); 85 &adev->vcn.irq);
86 if (r) 86 if (r)
87 return r; 87 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index cc8ce7e352a8..5ae5ed2e62d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -245,8 +245,8 @@ static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev)
245 * some faults get cleared. 245 * some faults get cleared.
246 */ 246 */
247 switch (dw0 & 0xff) { 247 switch (dw0 & 0xff) {
248 case AMDGPU_IH_CLIENTID_VMC: 248 case SOC15_IH_CLIENTID_VMC:
249 case AMDGPU_IH_CLIENTID_UTCL2: 249 case SOC15_IH_CLIENTID_UTCL2:
250 break; 250 break;
251 default: 251 default:
252 /* Not a VM fault */ 252 /* Not a VM fault */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f523b2476c1e..9e2f673cb6e1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1131,7 +1131,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1131 1131
1132 if (adev->asic_type == CHIP_VEGA10 || 1132 if (adev->asic_type == CHIP_VEGA10 ||
1133 adev->asic_type == CHIP_RAVEN) 1133 adev->asic_type == CHIP_RAVEN)
1134 client_id = AMDGPU_IH_CLIENTID_DCE; 1134 client_id = SOC15_IH_CLIENTID_DCE;
1135 1135
1136 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 1136 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1137 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 1137 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -1231,7 +1231,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1231 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 1231 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1232 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 1232 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1233 i++) { 1233 i++) {
1234 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq); 1234 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1235 1235
1236 if (r) { 1236 if (r) {
1237 DRM_ERROR("Failed to add crtc irq id!\n"); 1237 DRM_ERROR("Failed to add crtc irq id!\n");
@@ -1255,7 +1255,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1255 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 1255 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1256 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 1256 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1257 i++) { 1257 i++) {
1258 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 1258 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1259 if (r) { 1259 if (r) {
1260 DRM_ERROR("Failed to add page flip irq id!\n"); 1260 DRM_ERROR("Failed to add page flip irq id!\n");
1261 return r; 1261 return r;
@@ -1276,7 +1276,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1276 } 1276 }
1277 1277
1278 /* HPD */ 1278 /* HPD */
1279 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 1279 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1280 &adev->hpd_irq); 1280 &adev->hpd_irq);
1281 if (r) { 1281 if (r) {
1282 DRM_ERROR("Failed to add hpd irq id!\n"); 1282 DRM_ERROR("Failed to add hpd irq id!\n");
diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
new file mode 100644
index 000000000000..a12d4f27cfa4
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
@@ -0,0 +1,70 @@
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __SOC15_IH_CLIENTID_H__
25#define __SOC15_IH_CLIENTID_H__
26
27 /*
28 * vega10+ IH clients
29 */
30enum soc15_ih_clientid {
31 SOC15_IH_CLIENTID_IH = 0x00,
32 SOC15_IH_CLIENTID_ACP = 0x01,
33 SOC15_IH_CLIENTID_ATHUB = 0x02,
34 SOC15_IH_CLIENTID_BIF = 0x03,
35 SOC15_IH_CLIENTID_DCE = 0x04,
36 SOC15_IH_CLIENTID_ISP = 0x05,
37 SOC15_IH_CLIENTID_PCIE0 = 0x06,
38 SOC15_IH_CLIENTID_RLC = 0x07,
39 SOC15_IH_CLIENTID_SDMA0 = 0x08,
40 SOC15_IH_CLIENTID_SDMA1 = 0x09,
41 SOC15_IH_CLIENTID_SE0SH = 0x0a,
42 SOC15_IH_CLIENTID_SE1SH = 0x0b,
43 SOC15_IH_CLIENTID_SE2SH = 0x0c,
44 SOC15_IH_CLIENTID_SE3SH = 0x0d,
45 SOC15_IH_CLIENTID_SYSHUB = 0x0e,
46 SOC15_IH_CLIENTID_THM = 0x0f,
47 SOC15_IH_CLIENTID_UVD = 0x10,
48 SOC15_IH_CLIENTID_VCE0 = 0x11,
49 SOC15_IH_CLIENTID_VMC = 0x12,
50 SOC15_IH_CLIENTID_XDMA = 0x13,
51 SOC15_IH_CLIENTID_GRBM_CP = 0x14,
52 SOC15_IH_CLIENTID_ATS = 0x15,
53 SOC15_IH_CLIENTID_ROM_SMUIO = 0x16,
54 SOC15_IH_CLIENTID_DF = 0x17,
55 SOC15_IH_CLIENTID_VCE1 = 0x18,
56 SOC15_IH_CLIENTID_PWR = 0x19,
57 SOC15_IH_CLIENTID_UTCL2 = 0x1b,
58 SOC15_IH_CLIENTID_EA = 0x1c,
59 SOC15_IH_CLIENTID_UTCL2LOG = 0x1d,
60 SOC15_IH_CLIENTID_MP0 = 0x1e,
61 SOC15_IH_CLIENTID_MP1 = 0x1f,
62
63 SOC15_IH_CLIENTID_MAX,
64
65 SOC15_IH_CLIENTID_VCN = SOC15_IH_CLIENTID_UVD
66};
67
68#endif
69
70
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index f23861f2c685..2fcbb17b794d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4874,12 +4874,12 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
4874 hwmgr->thermal_controller.ucType == 4874 hwmgr->thermal_controller.ucType ==
4875 ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { 4875 ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
4876 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device, 4876 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
4877 0xf, /* AMDGPU_IH_CLIENTID_THM */ 4877 SOC15_IH_CLIENTID_THM,
4878 0, 0, irq_src[0].set, irq_src[0].handler, hwmgr), 4878 0, 0, irq_src[0].set, irq_src[0].handler, hwmgr),
4879 "Failed to register high thermal interrupt!", 4879 "Failed to register high thermal interrupt!",
4880 return -EINVAL); 4880 return -EINVAL);
4881 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device, 4881 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
4882 0xf, /* AMDGPU_IH_CLIENTID_THM */ 4882 SOC15_IH_CLIENTID_THM,
4883 1, 0, irq_src[1].set, irq_src[1].handler, hwmgr), 4883 1, 0, irq_src[1].set, irq_src[1].handler, hwmgr),
4884 "Failed to register low thermal interrupt!", 4884 "Failed to register low thermal interrupt!",
4885 return -EINVAL); 4885 return -EINVAL);
@@ -4887,7 +4887,7 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
4887 4887
4888 /* Register CTF(GPIO_19) interrupt */ 4888 /* Register CTF(GPIO_19) interrupt */
4889 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device, 4889 PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
4890 0x16, /* AMDGPU_IH_CLIENTID_ROM_SMUIO, */ 4890 SOC15_IH_CLIENTID_ROM_SMUIO,
4891 83, 0, irq_src[2].set, irq_src[2].handler, hwmgr), 4891 83, 0, irq_src[2].set, irq_src[2].handler, hwmgr),
4892 "Failed to register CTF thermal interrupt!", 4892 "Failed to register CTF thermal interrupt!",
4893 return -EINVAL); 4893 return -EINVAL);
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-24 05:29:20 -0400