net: hns3: Refine the MSIX allocation for PF

The offset of msix number for roce is different between different
revision id. We should get it from firmware, instead of a fix value.
This patch refines the msix allocation, make it compatible.

Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

3 files changed, 9 insertions, 4 deletions

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index 5cd22f9bbdec..cd0a4f228470 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -358,6 +358,8 @@ struct hclge_pf_res_cmd {
         __le16 buf_size;
         __le16 msixcap_localid_ba_nic;
         __le16 msixcap_localid_ba_rocee;
+#define HCLGE_MSIX_OFT_ROCEE_S          0
+#define HCLGE_MSIX_OFT_ROCEE_M          GENMASK(15, 0)
 #define HCLGE_PF_VEC_NUM_S              0
 #define HCLGE_PF_VEC_NUM_M              GENMASK(7, 0)
         __le16 pf_intr_vector_number;
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index a9b888f1544a..fc813b7f20e8 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -932,6 +932,9 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
         hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 
         if (hnae3_dev_roce_supported(hdev)) {
+                hdev->roce_base_msix_offset =
+                hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
+                                HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
                 hdev->num_roce_msi =
                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
@@ -939,7 +942,8 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
                 /* PF should have NIC vectors and Roce vectors,
                  * NIC vectors are queued before Roce vectors.
                  */
-                hdev->num_msi = hdev->num_roce_msi  + HCLGE_ROCE_VECTOR_OFFSET;
+                hdev->num_msi = hdev->num_roce_msi  +
+                                hdev->roce_base_msix_offset;
         } else {
                 hdev->num_msi =
                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
@@ -2037,7 +2041,7 @@ static int hclge_init_msi(struct hclge_dev *hdev)
         hdev->num_msi_left = vectors;
         hdev->base_msi_vector = pdev->irq;
         hdev->roce_base_vector = hdev->base_msi_vector +
-                                HCLGE_ROCE_VECTOR_OFFSET;
+                                hdev->roce_base_msix_offset;
 
         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
                                            sizeof(u16), GFP_KERNEL);
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
index dfa5c9456d22..1528fb3fa6be 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
@@ -16,8 +16,6 @@
 
 #define HCLGE_INVALID_VPORT 0xffff
 
-#define HCLGE_ROCE_VECTOR_OFFSET        96
-
 #define HCLGE_PF_CFG_BLOCK_SIZE         32
 #define HCLGE_PF_CFG_DESC_NUM \
         (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
@@ -509,6 +507,7 @@ struct hclge_dev {
         u16 num_msi;
         u16 num_msi_left;
         u16 num_msi_used;
+        u16 roce_base_msix_offset;
         u32 base_msi_vector;
         u16 *vector_status;
         int *vector_irq;