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authorRex Zhu <Rex.Zhu@amd.com>2017-09-20 05:19:58 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 15:14:33 -0400
commit37192704d9f55b0a64248c91a251fc6665f88045 (patch)
tree522ee0292292bb5e46b9d3d7603c462519e280d2
parenta9eca3a685b9fc3c9910eca4783ef07a2345b9e0 (diff)
drm/amd/powerplay: delete SMUM_WRITE_VFPF_INDIRECT_FIELD
repeated defining in hwmgr.h Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smumgr.h6
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c14
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c18
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c14
4 files changed, 23 insertions, 29 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 4433e0024cf9..b1b2104453c8 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -185,10 +185,4 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
185 SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ 185 SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
186 reg, field) 186 reg, field)
187 187
188
189#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
190 cgs_write_ind_register(device, port, ix##reg, \
191 SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
192 reg, field, fieldval))
193
194#endif 188#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 0b7cb3b0510e..ee89fd7c8342 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -66,7 +66,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
66 /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, 66 /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
67 RCU_UC_EVENTS, boot_seq_done, 0); */ 67 RCU_UC_EVENTS, boot_seq_done, 0); */
68 68
69 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 69 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
70 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 70 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
71 71
72 result = smu7_upload_smu_firmware_image(hwmgr); 72 result = smu7_upload_smu_firmware_image(hwmgr);
@@ -77,11 +77,11 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
77 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 77 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
78 ixSMU_STATUS, 0); 78 ixSMU_STATUS, 0);
79 79
80 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 80 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
81 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 81 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
82 82
83 /* De-assert reset */ 83 /* De-assert reset */
84 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 84 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
85 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 85 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
86 86
87 /* Wait for ROM firmware to initialize interrupt hendler */ 87 /* Wait for ROM firmware to initialize interrupt hendler */
@@ -89,7 +89,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
89 SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */ 89 SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
90 90
91 /* Set SMU Auto Start */ 91 /* Set SMU Auto Start */
92 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 92 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
93 SMU_INPUT_DATA, AUTO_START, 1); 93 SMU_INPUT_DATA, AUTO_START, 1);
94 94
95 /* Clear firmware interrupt enable flag */ 95 /* Clear firmware interrupt enable flag */
@@ -134,7 +134,7 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
134 ixFIRMWARE_FLAGS, 0); 134 ixFIRMWARE_FLAGS, 0);
135 135
136 /* Assert reset */ 136 /* Assert reset */
137 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 137 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
138 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 138 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
139 139
140 result = smu7_upload_smu_firmware_image(hwmgr); 140 result = smu7_upload_smu_firmware_image(hwmgr);
@@ -145,11 +145,11 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
145 smu7_program_jump_on_start(hwmgr); 145 smu7_program_jump_on_start(hwmgr);
146 146
147 /* Enable clock */ 147 /* Enable clock */
148 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 148 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
149 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 149 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
150 150
151 /* De-assert reset */ 151 /* De-assert reset */
152 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 152 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
153 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 153 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
154 154
155 /* Wait for firmware to initialize */ 155 /* Wait for firmware to initialize */
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index fd4ccd096985..eefa13ba4eaf 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -223,7 +223,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
223 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ 223 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
224 224
225 /* Assert reset */ 225 /* Assert reset */
226 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 226 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
227 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 227 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
228 228
229 result = smu7_upload_smu_firmware_image(hwmgr); 229 result = smu7_upload_smu_firmware_image(hwmgr);
@@ -233,11 +233,11 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
233 /* Clear status */ 233 /* Clear status */
234 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); 234 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
235 235
236 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 236 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
237 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 237 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
238 238
239 /* De-assert reset */ 239 /* De-assert reset */
240 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 240 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
241 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 241 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
242 242
243 243
@@ -258,10 +258,10 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
258 258
259 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); 259 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
260 260
261 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 261 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
262 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 262 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
263 263
264 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 264 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
265 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 265 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
266 266
267 /* Wait for firmware to initialize */ 267 /* Wait for firmware to initialize */
@@ -278,11 +278,11 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
278 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); 278 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
279 279
280 /* Clear firmware interrupt enable flag */ 280 /* Clear firmware interrupt enable flag */
281 /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ 281 /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
282 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 282 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
283 ixFIRMWARE_FLAGS, 0); 283 ixFIRMWARE_FLAGS, 0);
284 284
285 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 285 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
286 SMC_SYSCON_RESET_CNTL, 286 SMC_SYSCON_RESET_CNTL,
287 rst_reg, 1); 287 rst_reg, 1);
288 288
@@ -293,10 +293,10 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
293 /* Set smc instruct start point at 0x0 */ 293 /* Set smc instruct start point at 0x0 */
294 smu7_program_jump_on_start(hwmgr); 294 smu7_program_jump_on_start(hwmgr);
295 295
296 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 296 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
297 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 297 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
298 298
299 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 299 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
300 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 300 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
301 301
302 /* Wait for firmware to initialize */ 302 /* Wait for firmware to initialize */
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index 6a9b3cf3fdaa..7ffcadaa1a53 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -42,7 +42,7 @@ static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
42 int result; 42 int result;
43 43
44 /* Assert reset */ 44 /* Assert reset */
45 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 45 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
46 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 46 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
47 47
48 result = smu7_upload_smu_firmware_image(hwmgr); 48 result = smu7_upload_smu_firmware_image(hwmgr);
@@ -54,15 +54,15 @@ static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
54 ixSMU_STATUS, 0); 54 ixSMU_STATUS, 0);
55 55
56 /* Enable clock */ 56 /* Enable clock */
57 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 57 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
58 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 58 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
59 59
60 /* De-assert reset */ 60 /* De-assert reset */
61 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 61 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
62 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 62 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
63 63
64 /* Set SMU Auto Start */ 64 /* Set SMU Auto Start */
65 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 65 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
66 SMU_INPUT_DATA, AUTO_START, 1); 66 SMU_INPUT_DATA, AUTO_START, 1);
67 67
68 /* Clear firmware interrupt enable flag */ 68 /* Clear firmware interrupt enable flag */
@@ -109,7 +109,7 @@ static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
109 ixFIRMWARE_FLAGS, 0); 109 ixFIRMWARE_FLAGS, 0);
110 110
111 111
112 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 112 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
113 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 113 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
114 114
115 result = smu7_upload_smu_firmware_image(hwmgr); 115 result = smu7_upload_smu_firmware_image(hwmgr);
@@ -121,11 +121,11 @@ static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
121 smu7_program_jump_on_start(hwmgr); 121 smu7_program_jump_on_start(hwmgr);
122 122
123 123
124 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 124 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
125 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 125 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
126 126
127 /*De-assert reset*/ 127 /*De-assert reset*/
128 SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 128 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
129 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 129 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
130 130
131 /* Wait for firmware to initialize */ 131 /* Wait for firmware to initialize */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 12:28:37 -0400