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authorFlorian Fainelli <f.fainelli@gmail.com>2017-12-22 14:43:08 -0500
committerTejun Heo <tj@kernel.org>2018-01-02 11:38:29 -0500
commit36fffd6a1f19dcd935851fd6c724957727d2760e (patch)
tree06114cd4d6c2582b1b92af6cb1dfb401916048df
parentebb82e3c79d2a956366d0848304a53648bd6350b (diff)
ata: ahci_brcm: Avoid clobbering SATA_TOP_CTRL_BUS_CTRL
We are doing a blind write to SATA_TOP_CTRL_BUS_CTRL to set the system endian, but in doing so, we are also overwriting other bits, such as the SATA_SCB_BURST_SIZE and SATA_FIFO_SIZE bits, which impact performance. Do a read/modify/write so we keep the default values. While we are at it, we also greatly simplify the logic and just leave the NSP specific bit settings, instead of having a completely different sequence. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
-rw-r--r--drivers/ata/ahci_brcm.c25
1 files changed, 15 insertions, 10 deletions
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index 5936d1679bf3..ad3b8826ec79 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -70,6 +70,13 @@
70 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \ 70 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \
71 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT)) 71 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
72 72
73#define BUS_CTRL_ENDIAN_NSP_CONF \
74 (0x02 << DMADATA_ENDIAN_SHIFT | 0x02 << DMADESC_ENDIAN_SHIFT)
75
76#define BUS_CTRL_ENDIAN_CONF_MASK \
77 (0x3 << MMIO_ENDIAN_SHIFT | 0x3 << DMADESC_ENDIAN_SHIFT | \
78 0x3 << DMADATA_ENDIAN_SHIFT | 0x3 << PIODATA_ENDIAN_SHIFT)
79
73enum brcm_ahci_version { 80enum brcm_ahci_version {
74 BRCM_SATA_BCM7425 = 1, 81 BRCM_SATA_BCM7425 = 1,
75 BRCM_SATA_BCM7445, 82 BRCM_SATA_BCM7445,
@@ -250,18 +257,16 @@ static u32 brcm_ahci_get_portmask(struct platform_device *pdev,
250static void brcm_sata_init(struct brcm_ahci_priv *priv) 257static void brcm_sata_init(struct brcm_ahci_priv *priv)
251{ 258{
252 void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL; 259 void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL;
260 u32 data;
253 261
254 /* Configure endianness */ 262 /* Configure endianness */
255 if (priv->version == BRCM_SATA_NSP) { 263 data = brcm_sata_readreg(ctrl);
256 u32 data = brcm_sata_readreg(ctrl); 264 data &= ~BUS_CTRL_ENDIAN_CONF_MASK;
257 265 if (priv->version == BRCM_SATA_NSP)
258 data &= ~((0x03 << DMADATA_ENDIAN_SHIFT) | 266 data |= BUS_CTRL_ENDIAN_NSP_CONF;
259 (0x03 << DMADESC_ENDIAN_SHIFT)); 267 else
260 data |= (0x02 << DMADATA_ENDIAN_SHIFT) | 268 data |= BUS_CTRL_ENDIAN_CONF;
261 (0x02 << DMADESC_ENDIAN_SHIFT); 269 brcm_sata_writereg(data, ctrl);
262 brcm_sata_writereg(data, ctrl);
263 } else
264 brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF, ctrl);
265} 270}
266 271
267#ifdef CONFIG_PM_SLEEP 272#ifdef CONFIG_PM_SLEEP