aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAlexandre TORGUE <alexandre.torgue@st.com>2016-04-01 05:37:32 -0400
committerDavid S. Miller <davem@davemloft.net>2016-04-02 20:23:08 -0400
commit36ff7c1e94a5d43a0ea2d386b211087f77669017 (patch)
treefa8a01eb8d3ff0bffec869c773df207821b86899
parent477286b53f5576ddec0a4df0f3d0c4bd7a0ed165 (diff)
stmmac: enhance mmc counter management
For gmac3, the MMC addr map is: 0x100 - 0x2fc For gmac4, the MMC addr map is: 0x700 - 0x8fc So instead of adding 0x600 to the IO address when setup the mmc, the RMON base address is saved inside the private structure and then used to manage the counters. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/mmc.h4
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/mmc_core.c349
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac.h1
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c2
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_main.c8
5 files changed, 188 insertions, 176 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc.h b/drivers/net/ethernet/stmicro/stmmac/mmc.h
index 192c2491330b..38a1a5603293 100644
--- a/drivers/net/ethernet/stmicro/stmmac/mmc.h
+++ b/drivers/net/ethernet/stmicro/stmmac/mmc.h
@@ -35,6 +35,10 @@
35 * current value.*/ 35 * current value.*/
36#define MMC_CNTRL_PRESET 0x10 36#define MMC_CNTRL_PRESET 0x10
37#define MMC_CNTRL_FULL_HALF_PRESET 0x20 37#define MMC_CNTRL_FULL_HALF_PRESET 0x20
38
39#define MMC_GMAC4_OFFSET 0x700
40#define MMC_GMAC3_X_OFFSET 0x100
41
38struct stmmac_counters { 42struct stmmac_counters {
39 unsigned int mmc_tx_octetcount_gb; 43 unsigned int mmc_tx_octetcount_gb;
40 unsigned int mmc_tx_framecount_gb; 44 unsigned int mmc_tx_framecount_gb;
diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
index 3f20bb1fe570..ce9aa792857b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
@@ -28,12 +28,12 @@
28 28
29/* MAC Management Counters register offset */ 29/* MAC Management Counters register offset */
30 30
31#define MMC_CNTRL 0x00000100 /* MMC Control */ 31#define MMC_CNTRL 0x00 /* MMC Control */
32#define MMC_RX_INTR 0x00000104 /* MMC RX Interrupt */ 32#define MMC_RX_INTR 0x04 /* MMC RX Interrupt */
33#define MMC_TX_INTR 0x00000108 /* MMC TX Interrupt */ 33#define MMC_TX_INTR 0x08 /* MMC TX Interrupt */
34#define MMC_RX_INTR_MASK 0x0000010c /* MMC Interrupt Mask */ 34#define MMC_RX_INTR_MASK 0x0c /* MMC Interrupt Mask */
35#define MMC_TX_INTR_MASK 0x00000110 /* MMC Interrupt Mask */ 35#define MMC_TX_INTR_MASK 0x10 /* MMC Interrupt Mask */
36#define MMC_DEFAULT_MASK 0xffffffff 36#define MMC_DEFAULT_MASK 0xffffffff
37 37
38/* MMC TX counter registers */ 38/* MMC TX counter registers */
39 39
@@ -41,115 +41,115 @@
41 * _GB register stands for good and bad frames 41 * _GB register stands for good and bad frames
42 * _G is for good only. 42 * _G is for good only.
43 */ 43 */
44#define MMC_TX_OCTETCOUNT_GB 0x00000114 44#define MMC_TX_OCTETCOUNT_GB 0x14
45#define MMC_TX_FRAMECOUNT_GB 0x00000118 45#define MMC_TX_FRAMECOUNT_GB 0x18
46#define MMC_TX_BROADCASTFRAME_G 0x0000011c 46#define MMC_TX_BROADCASTFRAME_G 0x1c
47#define MMC_TX_MULTICASTFRAME_G 0x00000120 47#define MMC_TX_MULTICASTFRAME_G 0x20
48#define MMC_TX_64_OCTETS_GB 0x00000124 48#define MMC_TX_64_OCTETS_GB 0x24
49#define MMC_TX_65_TO_127_OCTETS_GB 0x00000128 49#define MMC_TX_65_TO_127_OCTETS_GB 0x28
50#define MMC_TX_128_TO_255_OCTETS_GB 0x0000012c 50#define MMC_TX_128_TO_255_OCTETS_GB 0x2c
51#define MMC_TX_256_TO_511_OCTETS_GB 0x00000130 51#define MMC_TX_256_TO_511_OCTETS_GB 0x30
52#define MMC_TX_512_TO_1023_OCTETS_GB 0x00000134 52#define MMC_TX_512_TO_1023_OCTETS_GB 0x34
53#define MMC_TX_1024_TO_MAX_OCTETS_GB 0x00000138 53#define MMC_TX_1024_TO_MAX_OCTETS_GB 0x38
54#define MMC_TX_UNICAST_GB 0x0000013c 54#define MMC_TX_UNICAST_GB 0x3c
55#define MMC_TX_MULTICAST_GB 0x00000140 55#define MMC_TX_MULTICAST_GB 0x40
56#define MMC_TX_BROADCAST_GB 0x00000144 56#define MMC_TX_BROADCAST_GB 0x44
57#define MMC_TX_UNDERFLOW_ERROR 0x00000148 57#define MMC_TX_UNDERFLOW_ERROR 0x48
58#define MMC_TX_SINGLECOL_G 0x0000014c 58#define MMC_TX_SINGLECOL_G 0x4c
59#define MMC_TX_MULTICOL_G 0x00000150 59#define MMC_TX_MULTICOL_G 0x50
60#define MMC_TX_DEFERRED 0x00000154 60#define MMC_TX_DEFERRED 0x54
61#define MMC_TX_LATECOL 0x00000158 61#define MMC_TX_LATECOL 0x58
62#define MMC_TX_EXESSCOL 0x0000015c 62#define MMC_TX_EXESSCOL 0x5c
63#define MMC_TX_CARRIER_ERROR 0x00000160 63#define MMC_TX_CARRIER_ERROR 0x60
64#define MMC_TX_OCTETCOUNT_G 0x00000164 64#define MMC_TX_OCTETCOUNT_G 0x64
65#define MMC_TX_FRAMECOUNT_G 0x00000168 65#define MMC_TX_FRAMECOUNT_G 0x68
66#define MMC_TX_EXCESSDEF 0x0000016c 66#define MMC_TX_EXCESSDEF 0x6c
67#define MMC_TX_PAUSE_FRAME 0x00000170 67#define MMC_TX_PAUSE_FRAME 0x70
68#define MMC_TX_VLAN_FRAME_G 0x00000174 68#define MMC_TX_VLAN_FRAME_G 0x74
69 69
70/* MMC RX counter registers */ 70/* MMC RX counter registers */
71#define MMC_RX_FRAMECOUNT_GB 0x00000180 71#define MMC_RX_FRAMECOUNT_GB 0x80
72#define MMC_RX_OCTETCOUNT_GB 0x00000184 72#define MMC_RX_OCTETCOUNT_GB 0x84
73#define MMC_RX_OCTETCOUNT_G 0x00000188 73#define MMC_RX_OCTETCOUNT_G 0x88
74#define MMC_RX_BROADCASTFRAME_G 0x0000018c 74#define MMC_RX_BROADCASTFRAME_G 0x8c
75#define MMC_RX_MULTICASTFRAME_G 0x00000190 75#define MMC_RX_MULTICASTFRAME_G 0x90
76#define MMC_RX_CRC_ERROR 0x00000194 76#define MMC_RX_CRC_ERROR 0x94
77#define MMC_RX_ALIGN_ERROR 0x00000198 77#define MMC_RX_ALIGN_ERROR 0x98
78#define MMC_RX_RUN_ERROR 0x0000019C 78#define MMC_RX_RUN_ERROR 0x9C
79#define MMC_RX_JABBER_ERROR 0x000001A0 79#define MMC_RX_JABBER_ERROR 0xA0
80#define MMC_RX_UNDERSIZE_G 0x000001A4 80#define MMC_RX_UNDERSIZE_G 0xA4
81#define MMC_RX_OVERSIZE_G 0x000001A8 81#define MMC_RX_OVERSIZE_G 0xA8
82#define MMC_RX_64_OCTETS_GB 0x000001AC 82#define MMC_RX_64_OCTETS_GB 0xAC
83#define MMC_RX_65_TO_127_OCTETS_GB 0x000001b0 83#define MMC_RX_65_TO_127_OCTETS_GB 0xb0
84#define MMC_RX_128_TO_255_OCTETS_GB 0x000001b4 84#define MMC_RX_128_TO_255_OCTETS_GB 0xb4
85#define MMC_RX_256_TO_511_OCTETS_GB 0x000001b8 85#define MMC_RX_256_TO_511_OCTETS_GB 0xb8
86#define MMC_RX_512_TO_1023_OCTETS_GB 0x000001bc 86#define MMC_RX_512_TO_1023_OCTETS_GB 0xbc
87#define MMC_RX_1024_TO_MAX_OCTETS_GB 0x000001c0 87#define MMC_RX_1024_TO_MAX_OCTETS_GB 0xc0
88#define MMC_RX_UNICAST_G 0x000001c4 88#define MMC_RX_UNICAST_G 0xc4
89#define MMC_RX_LENGTH_ERROR 0x000001c8 89#define MMC_RX_LENGTH_ERROR 0xc8
90#define MMC_RX_AUTOFRANGETYPE 0x000001cc 90#define MMC_RX_AUTOFRANGETYPE 0xcc
91#define MMC_RX_PAUSE_FRAMES 0x000001d0 91#define MMC_RX_PAUSE_FRAMES 0xd0
92#define MMC_RX_FIFO_OVERFLOW 0x000001d4 92#define MMC_RX_FIFO_OVERFLOW 0xd4
93#define MMC_RX_VLAN_FRAMES_GB 0x000001d8 93#define MMC_RX_VLAN_FRAMES_GB 0xd8
94#define MMC_RX_WATCHDOG_ERROR 0x000001dc 94#define MMC_RX_WATCHDOG_ERROR 0xdc
95/* IPC*/ 95/* IPC*/
96#define MMC_RX_IPC_INTR_MASK 0x00000200 96#define MMC_RX_IPC_INTR_MASK 0x100
97#define MMC_RX_IPC_INTR 0x00000208 97#define MMC_RX_IPC_INTR 0x108
98/* IPv4*/ 98/* IPv4*/
99#define MMC_RX_IPV4_GD 0x00000210 99#define MMC_RX_IPV4_GD 0x110
100#define MMC_RX_IPV4_HDERR 0x00000214 100#define MMC_RX_IPV4_HDERR 0x114
101#define MMC_RX_IPV4_NOPAY 0x00000218 101#define MMC_RX_IPV4_NOPAY 0x118
102#define MMC_RX_IPV4_FRAG 0x0000021C 102#define MMC_RX_IPV4_FRAG 0x11C
103#define MMC_RX_IPV4_UDSBL 0x00000220 103#define MMC_RX_IPV4_UDSBL 0x120
104 104
105#define MMC_RX_IPV4_GD_OCTETS 0x00000250 105#define MMC_RX_IPV4_GD_OCTETS 0x150
106#define MMC_RX_IPV4_HDERR_OCTETS 0x00000254 106#define MMC_RX_IPV4_HDERR_OCTETS 0x154
107#define MMC_RX_IPV4_NOPAY_OCTETS 0x00000258 107#define MMC_RX_IPV4_NOPAY_OCTETS 0x158
108#define MMC_RX_IPV4_FRAG_OCTETS 0x0000025c 108#define MMC_RX_IPV4_FRAG_OCTETS 0x15c
109#define MMC_RX_IPV4_UDSBL_OCTETS 0x00000260 109#define MMC_RX_IPV4_UDSBL_OCTETS 0x160
110 110
111/* IPV6*/ 111/* IPV6*/
112#define MMC_RX_IPV6_GD_OCTETS 0x00000264 112#define MMC_RX_IPV6_GD_OCTETS 0x164
113#define MMC_RX_IPV6_HDERR_OCTETS 0x00000268 113#define MMC_RX_IPV6_HDERR_OCTETS 0x168
114#define MMC_RX_IPV6_NOPAY_OCTETS 0x0000026c 114#define MMC_RX_IPV6_NOPAY_OCTETS 0x16c
115 115
116#define MMC_RX_IPV6_GD 0x00000224 116#define MMC_RX_IPV6_GD 0x124
117#define MMC_RX_IPV6_HDERR 0x00000228 117#define MMC_RX_IPV6_HDERR 0x128
118#define MMC_RX_IPV6_NOPAY 0x0000022c 118#define MMC_RX_IPV6_NOPAY 0x12c
119 119
120/* Protocols*/ 120/* Protocols*/
121#define MMC_RX_UDP_GD 0x00000230 121#define MMC_RX_UDP_GD 0x130
122#define MMC_RX_UDP_ERR 0x00000234 122#define MMC_RX_UDP_ERR 0x134
123#define MMC_RX_TCP_GD 0x00000238 123#define MMC_RX_TCP_GD 0x138
124#define MMC_RX_TCP_ERR 0x0000023c 124#define MMC_RX_TCP_ERR 0x13c
125#define MMC_RX_ICMP_GD 0x00000240 125#define MMC_RX_ICMP_GD 0x140
126#define MMC_RX_ICMP_ERR 0x00000244 126#define MMC_RX_ICMP_ERR 0x144
127 127
128#define MMC_RX_UDP_GD_OCTETS 0x00000270 128#define MMC_RX_UDP_GD_OCTETS 0x170
129#define MMC_RX_UDP_ERR_OCTETS 0x00000274 129#define MMC_RX_UDP_ERR_OCTETS 0x174
130#define MMC_RX_TCP_GD_OCTETS 0x00000278 130#define MMC_RX_TCP_GD_OCTETS 0x178
131#define MMC_RX_TCP_ERR_OCTETS 0x0000027c 131#define MMC_RX_TCP_ERR_OCTETS 0x17c
132#define MMC_RX_ICMP_GD_OCTETS 0x00000280 132#define MMC_RX_ICMP_GD_OCTETS 0x180
133#define MMC_RX_ICMP_ERR_OCTETS 0x00000284 133#define MMC_RX_ICMP_ERR_OCTETS 0x184
134 134
135void dwmac_mmc_ctrl(void __iomem *ioaddr, unsigned int mode) 135void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
136{ 136{
137 u32 value = readl(ioaddr + MMC_CNTRL); 137 u32 value = readl(mmcaddr + MMC_CNTRL);
138 138
139 value |= (mode & 0x3F); 139 value |= (mode & 0x3F);
140 140
141 writel(value, ioaddr + MMC_CNTRL); 141 writel(value, mmcaddr + MMC_CNTRL);
142 142
143 pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n", 143 pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n",
144 MMC_CNTRL, value); 144 MMC_CNTRL, value);
145} 145}
146 146
147/* To mask all all interrupts.*/ 147/* To mask all all interrupts.*/
148void dwmac_mmc_intr_all_mask(void __iomem *ioaddr) 148void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)
149{ 149{
150 writel(MMC_DEFAULT_MASK, ioaddr + MMC_RX_INTR_MASK); 150 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);
151 writel(MMC_DEFAULT_MASK, ioaddr + MMC_TX_INTR_MASK); 151 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);
152 writel(MMC_DEFAULT_MASK, ioaddr + MMC_RX_IPC_INTR_MASK); 152 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);
153} 153}
154 154
155/* This reads the MAC core counters (if actaully supported). 155/* This reads the MAC core counters (if actaully supported).
@@ -157,111 +157,116 @@ void dwmac_mmc_intr_all_mask(void __iomem *ioaddr)
157 * counter after a read. So all the field of the mmc struct 157 * counter after a read. So all the field of the mmc struct
158 * have to be incremented. 158 * have to be incremented.
159 */ 159 */
160void dwmac_mmc_read(void __iomem *ioaddr, struct stmmac_counters *mmc) 160void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
161{ 161{
162 mmc->mmc_tx_octetcount_gb += readl(ioaddr + MMC_TX_OCTETCOUNT_GB); 162 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB);
163 mmc->mmc_tx_framecount_gb += readl(ioaddr + MMC_TX_FRAMECOUNT_GB); 163 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB);
164 mmc->mmc_tx_broadcastframe_g += readl(ioaddr + MMC_TX_BROADCASTFRAME_G); 164 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr +
165 mmc->mmc_tx_multicastframe_g += readl(ioaddr + MMC_TX_MULTICASTFRAME_G); 165 MMC_TX_BROADCASTFRAME_G);
166 mmc->mmc_tx_64_octets_gb += readl(ioaddr + MMC_TX_64_OCTETS_GB); 166 mmc->mmc_tx_multicastframe_g += readl(mmcaddr +
167 MMC_TX_MULTICASTFRAME_G);
168 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB);
167 mmc->mmc_tx_65_to_127_octets_gb += 169 mmc->mmc_tx_65_to_127_octets_gb +=
168 readl(ioaddr + MMC_TX_65_TO_127_OCTETS_GB); 170 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB);
169 mmc->mmc_tx_128_to_255_octets_gb += 171 mmc->mmc_tx_128_to_255_octets_gb +=
170 readl(ioaddr + MMC_TX_128_TO_255_OCTETS_GB); 172 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB);
171 mmc->mmc_tx_256_to_511_octets_gb += 173 mmc->mmc_tx_256_to_511_octets_gb +=
172 readl(ioaddr + MMC_TX_256_TO_511_OCTETS_GB); 174 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB);
173 mmc->mmc_tx_512_to_1023_octets_gb += 175 mmc->mmc_tx_512_to_1023_octets_gb +=
174 readl(ioaddr + MMC_TX_512_TO_1023_OCTETS_GB); 176 readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB);
175 mmc->mmc_tx_1024_to_max_octets_gb += 177 mmc->mmc_tx_1024_to_max_octets_gb +=
176 readl(ioaddr + MMC_TX_1024_TO_MAX_OCTETS_GB); 178 readl(mmcaddr + MMC_TX_1024_TO_MAX_OCTETS_GB);
177 mmc->mmc_tx_unicast_gb += readl(ioaddr + MMC_TX_UNICAST_GB); 179 mmc->mmc_tx_unicast_gb += readl(mmcaddr + MMC_TX_UNICAST_GB);
178 mmc->mmc_tx_multicast_gb += readl(ioaddr + MMC_TX_MULTICAST_GB); 180 mmc->mmc_tx_multicast_gb += readl(mmcaddr + MMC_TX_MULTICAST_GB);
179 mmc->mmc_tx_broadcast_gb += readl(ioaddr + MMC_TX_BROADCAST_GB); 181 mmc->mmc_tx_broadcast_gb += readl(mmcaddr + MMC_TX_BROADCAST_GB);
180 mmc->mmc_tx_underflow_error += readl(ioaddr + MMC_TX_UNDERFLOW_ERROR); 182 mmc->mmc_tx_underflow_error += readl(mmcaddr + MMC_TX_UNDERFLOW_ERROR);
181 mmc->mmc_tx_singlecol_g += readl(ioaddr + MMC_TX_SINGLECOL_G); 183 mmc->mmc_tx_singlecol_g += readl(mmcaddr + MMC_TX_SINGLECOL_G);
182 mmc->mmc_tx_multicol_g += readl(ioaddr + MMC_TX_MULTICOL_G); 184 mmc->mmc_tx_multicol_g += readl(mmcaddr + MMC_TX_MULTICOL_G);
183 mmc->mmc_tx_deferred += readl(ioaddr + MMC_TX_DEFERRED); 185 mmc->mmc_tx_deferred += readl(mmcaddr + MMC_TX_DEFERRED);
184 mmc->mmc_tx_latecol += readl(ioaddr + MMC_TX_LATECOL); 186 mmc->mmc_tx_latecol += readl(mmcaddr + MMC_TX_LATECOL);
185 mmc->mmc_tx_exesscol += readl(ioaddr + MMC_TX_EXESSCOL); 187 mmc->mmc_tx_exesscol += readl(mmcaddr + MMC_TX_EXESSCOL);
186 mmc->mmc_tx_carrier_error += readl(ioaddr + MMC_TX_CARRIER_ERROR); 188 mmc->mmc_tx_carrier_error += readl(mmcaddr + MMC_TX_CARRIER_ERROR);
187 mmc->mmc_tx_octetcount_g += readl(ioaddr + MMC_TX_OCTETCOUNT_G); 189 mmc->mmc_tx_octetcount_g += readl(mmcaddr + MMC_TX_OCTETCOUNT_G);
188 mmc->mmc_tx_framecount_g += readl(ioaddr + MMC_TX_FRAMECOUNT_G); 190 mmc->mmc_tx_framecount_g += readl(mmcaddr + MMC_TX_FRAMECOUNT_G);
189 mmc->mmc_tx_excessdef += readl(ioaddr + MMC_TX_EXCESSDEF); 191 mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF);
190 mmc->mmc_tx_pause_frame += readl(ioaddr + MMC_TX_PAUSE_FRAME); 192 mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME);
191 mmc->mmc_tx_vlan_frame_g += readl(ioaddr + MMC_TX_VLAN_FRAME_G); 193 mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G);
192 194
193 /* MMC RX counter registers */ 195 /* MMC RX counter registers */
194 mmc->mmc_rx_framecount_gb += readl(ioaddr + MMC_RX_FRAMECOUNT_GB); 196 mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB);
195 mmc->mmc_rx_octetcount_gb += readl(ioaddr + MMC_RX_OCTETCOUNT_GB); 197 mmc->mmc_rx_octetcount_gb += readl(mmcaddr + MMC_RX_OCTETCOUNT_GB);
196 mmc->mmc_rx_octetcount_g += readl(ioaddr + MMC_RX_OCTETCOUNT_G); 198 mmc->mmc_rx_octetcount_g += readl(mmcaddr + MMC_RX_OCTETCOUNT_G);
197 mmc->mmc_rx_broadcastframe_g += readl(ioaddr + MMC_RX_BROADCASTFRAME_G); 199 mmc->mmc_rx_broadcastframe_g += readl(mmcaddr +
198 mmc->mmc_rx_multicastframe_g += readl(ioaddr + MMC_RX_MULTICASTFRAME_G); 200 MMC_RX_BROADCASTFRAME_G);
199 mmc->mmc_rx_crc_error += readl(ioaddr + MMC_RX_CRC_ERROR); 201 mmc->mmc_rx_multicastframe_g += readl(mmcaddr +
200 mmc->mmc_rx_align_error += readl(ioaddr + MMC_RX_ALIGN_ERROR); 202 MMC_RX_MULTICASTFRAME_G);
201 mmc->mmc_rx_run_error += readl(ioaddr + MMC_RX_RUN_ERROR); 203 mmc->mmc_rx_crc_error += readl(mmcaddr + MMC_RX_CRC_ERROR);
202 mmc->mmc_rx_jabber_error += readl(ioaddr + MMC_RX_JABBER_ERROR); 204 mmc->mmc_rx_align_error += readl(mmcaddr + MMC_RX_ALIGN_ERROR);
203 mmc->mmc_rx_undersize_g += readl(ioaddr + MMC_RX_UNDERSIZE_G); 205 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_RX_RUN_ERROR);
204 mmc->mmc_rx_oversize_g += readl(ioaddr + MMC_RX_OVERSIZE_G); 206 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_RX_JABBER_ERROR);
205 mmc->mmc_rx_64_octets_gb += readl(ioaddr + MMC_RX_64_OCTETS_GB); 207 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_RX_UNDERSIZE_G);
208 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_RX_OVERSIZE_G);
209 mmc->mmc_rx_64_octets_gb += readl(mmcaddr + MMC_RX_64_OCTETS_GB);
206 mmc->mmc_rx_65_to_127_octets_gb += 210 mmc->mmc_rx_65_to_127_octets_gb +=
207 readl(ioaddr + MMC_RX_65_TO_127_OCTETS_GB); 211 readl(mmcaddr + MMC_RX_65_TO_127_OCTETS_GB);
208 mmc->mmc_rx_128_to_255_octets_gb += 212 mmc->mmc_rx_128_to_255_octets_gb +=
209 readl(ioaddr + MMC_RX_128_TO_255_OCTETS_GB); 213 readl(mmcaddr + MMC_RX_128_TO_255_OCTETS_GB);
210 mmc->mmc_rx_256_to_511_octets_gb += 214 mmc->mmc_rx_256_to_511_octets_gb +=
211 readl(ioaddr + MMC_RX_256_TO_511_OCTETS_GB); 215 readl(mmcaddr + MMC_RX_256_TO_511_OCTETS_GB);
212 mmc->mmc_rx_512_to_1023_octets_gb += 216 mmc->mmc_rx_512_to_1023_octets_gb +=
213 readl(ioaddr + MMC_RX_512_TO_1023_OCTETS_GB); 217 readl(mmcaddr + MMC_RX_512_TO_1023_OCTETS_GB);
214 mmc->mmc_rx_1024_to_max_octets_gb += 218 mmc->mmc_rx_1024_to_max_octets_gb +=
215 readl(ioaddr + MMC_RX_1024_TO_MAX_OCTETS_GB); 219 readl(mmcaddr + MMC_RX_1024_TO_MAX_OCTETS_GB);
216 mmc->mmc_rx_unicast_g += readl(ioaddr + MMC_RX_UNICAST_G); 220 mmc->mmc_rx_unicast_g += readl(mmcaddr + MMC_RX_UNICAST_G);
217 mmc->mmc_rx_length_error += readl(ioaddr + MMC_RX_LENGTH_ERROR); 221 mmc->mmc_rx_length_error += readl(mmcaddr + MMC_RX_LENGTH_ERROR);
218 mmc->mmc_rx_autofrangetype += readl(ioaddr + MMC_RX_AUTOFRANGETYPE); 222 mmc->mmc_rx_autofrangetype += readl(mmcaddr + MMC_RX_AUTOFRANGETYPE);
219 mmc->mmc_rx_pause_frames += readl(ioaddr + MMC_RX_PAUSE_FRAMES); 223 mmc->mmc_rx_pause_frames += readl(mmcaddr + MMC_RX_PAUSE_FRAMES);
220 mmc->mmc_rx_fifo_overflow += readl(ioaddr + MMC_RX_FIFO_OVERFLOW); 224 mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW);
221 mmc->mmc_rx_vlan_frames_gb += readl(ioaddr + MMC_RX_VLAN_FRAMES_GB); 225 mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB);
222 mmc->mmc_rx_watchdog_error += readl(ioaddr + MMC_RX_WATCHDOG_ERROR); 226 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR);
223 /* IPC */ 227 /* IPC */
224 mmc->mmc_rx_ipc_intr_mask += readl(ioaddr + MMC_RX_IPC_INTR_MASK); 228 mmc->mmc_rx_ipc_intr_mask += readl(mmcaddr + MMC_RX_IPC_INTR_MASK);
225 mmc->mmc_rx_ipc_intr += readl(ioaddr + MMC_RX_IPC_INTR); 229 mmc->mmc_rx_ipc_intr += readl(mmcaddr + MMC_RX_IPC_INTR);
226 /* IPv4 */ 230 /* IPv4 */
227 mmc->mmc_rx_ipv4_gd += readl(ioaddr + MMC_RX_IPV4_GD); 231 mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD);
228 mmc->mmc_rx_ipv4_hderr += readl(ioaddr + MMC_RX_IPV4_HDERR); 232 mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR);
229 mmc->mmc_rx_ipv4_nopay += readl(ioaddr + MMC_RX_IPV4_NOPAY); 233 mmc->mmc_rx_ipv4_nopay += readl(mmcaddr + MMC_RX_IPV4_NOPAY);
230 mmc->mmc_rx_ipv4_frag += readl(ioaddr + MMC_RX_IPV4_FRAG); 234 mmc->mmc_rx_ipv4_frag += readl(mmcaddr + MMC_RX_IPV4_FRAG);
231 mmc->mmc_rx_ipv4_udsbl += readl(ioaddr + MMC_RX_IPV4_UDSBL); 235 mmc->mmc_rx_ipv4_udsbl += readl(mmcaddr + MMC_RX_IPV4_UDSBL);
232 236
233 mmc->mmc_rx_ipv4_gd_octets += readl(ioaddr + MMC_RX_IPV4_GD_OCTETS); 237 mmc->mmc_rx_ipv4_gd_octets += readl(mmcaddr + MMC_RX_IPV4_GD_OCTETS);
234 mmc->mmc_rx_ipv4_hderr_octets += 238 mmc->mmc_rx_ipv4_hderr_octets +=
235 readl(ioaddr + MMC_RX_IPV4_HDERR_OCTETS); 239 readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS);
236 mmc->mmc_rx_ipv4_nopay_octets += 240 mmc->mmc_rx_ipv4_nopay_octets +=
237 readl(ioaddr + MMC_RX_IPV4_NOPAY_OCTETS); 241 readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS);
238 mmc->mmc_rx_ipv4_frag_octets += readl(ioaddr + MMC_RX_IPV4_FRAG_OCTETS); 242 mmc->mmc_rx_ipv4_frag_octets += readl(mmcaddr +
243 MMC_RX_IPV4_FRAG_OCTETS);
239 mmc->mmc_rx_ipv4_udsbl_octets += 244 mmc->mmc_rx_ipv4_udsbl_octets +=
240 readl(ioaddr + MMC_RX_IPV4_UDSBL_OCTETS); 245 readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS);
241 246
242 /* IPV6 */ 247 /* IPV6 */
243 mmc->mmc_rx_ipv6_gd_octets += readl(ioaddr + MMC_RX_IPV6_GD_OCTETS); 248 mmc->mmc_rx_ipv6_gd_octets += readl(mmcaddr + MMC_RX_IPV6_GD_OCTETS);
244 mmc->mmc_rx_ipv6_hderr_octets += 249 mmc->mmc_rx_ipv6_hderr_octets +=
245 readl(ioaddr + MMC_RX_IPV6_HDERR_OCTETS); 250 readl(mmcaddr + MMC_RX_IPV6_HDERR_OCTETS);
246 mmc->mmc_rx_ipv6_nopay_octets += 251 mmc->mmc_rx_ipv6_nopay_octets +=
247 readl(ioaddr + MMC_RX_IPV6_NOPAY_OCTETS); 252 readl(mmcaddr + MMC_RX_IPV6_NOPAY_OCTETS);
248 253
249 mmc->mmc_rx_ipv6_gd += readl(ioaddr + MMC_RX_IPV6_GD); 254 mmc->mmc_rx_ipv6_gd += readl(mmcaddr + MMC_RX_IPV6_GD);
250 mmc->mmc_rx_ipv6_hderr += readl(ioaddr + MMC_RX_IPV6_HDERR); 255 mmc->mmc_rx_ipv6_hderr += readl(mmcaddr + MMC_RX_IPV6_HDERR);
251 mmc->mmc_rx_ipv6_nopay += readl(ioaddr + MMC_RX_IPV6_NOPAY); 256 mmc->mmc_rx_ipv6_nopay += readl(mmcaddr + MMC_RX_IPV6_NOPAY);
252 257
253 /* Protocols */ 258 /* Protocols */
254 mmc->mmc_rx_udp_gd += readl(ioaddr + MMC_RX_UDP_GD); 259 mmc->mmc_rx_udp_gd += readl(mmcaddr + MMC_RX_UDP_GD);
255 mmc->mmc_rx_udp_err += readl(ioaddr + MMC_RX_UDP_ERR); 260 mmc->mmc_rx_udp_err += readl(mmcaddr + MMC_RX_UDP_ERR);
256 mmc->mmc_rx_tcp_gd += readl(ioaddr + MMC_RX_TCP_GD); 261 mmc->mmc_rx_tcp_gd += readl(mmcaddr + MMC_RX_TCP_GD);
257 mmc->mmc_rx_tcp_err += readl(ioaddr + MMC_RX_TCP_ERR); 262 mmc->mmc_rx_tcp_err += readl(mmcaddr + MMC_RX_TCP_ERR);
258 mmc->mmc_rx_icmp_gd += readl(ioaddr + MMC_RX_ICMP_GD); 263 mmc->mmc_rx_icmp_gd += readl(mmcaddr + MMC_RX_ICMP_GD);
259 mmc->mmc_rx_icmp_err += readl(ioaddr + MMC_RX_ICMP_ERR); 264 mmc->mmc_rx_icmp_err += readl(mmcaddr + MMC_RX_ICMP_ERR);
260 265
261 mmc->mmc_rx_udp_gd_octets += readl(ioaddr + MMC_RX_UDP_GD_OCTETS); 266 mmc->mmc_rx_udp_gd_octets += readl(mmcaddr + MMC_RX_UDP_GD_OCTETS);
262 mmc->mmc_rx_udp_err_octets += readl(ioaddr + MMC_RX_UDP_ERR_OCTETS); 267 mmc->mmc_rx_udp_err_octets += readl(mmcaddr + MMC_RX_UDP_ERR_OCTETS);
263 mmc->mmc_rx_tcp_gd_octets += readl(ioaddr + MMC_RX_TCP_GD_OCTETS); 268 mmc->mmc_rx_tcp_gd_octets += readl(mmcaddr + MMC_RX_TCP_GD_OCTETS);
264 mmc->mmc_rx_tcp_err_octets += readl(ioaddr + MMC_RX_TCP_ERR_OCTETS); 269 mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS);
265 mmc->mmc_rx_icmp_gd_octets += readl(ioaddr + MMC_RX_ICMP_GD_OCTETS); 270 mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS);
266 mmc->mmc_rx_icmp_err_octets += readl(ioaddr + MMC_RX_ICMP_ERR_OCTETS); 271 mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS);
267} 272}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index 8bbab97895fe..26fb85531a61 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -128,6 +128,7 @@ struct stmmac_priv {
128 int use_riwt; 128 int use_riwt;
129 int irq_wake; 129 int irq_wake;
130 spinlock_t ptp_lock; 130 spinlock_t ptp_lock;
131 void __iomem *mmcaddr;
131 132
132#ifdef CONFIG_DEBUG_FS 133#ifdef CONFIG_DEBUG_FS
133 struct dentry *dbgfs_dir; 134 struct dentry *dbgfs_dir;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index 3c7928edfebb..fb2e7fc85ca7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -506,7 +506,7 @@ static void stmmac_get_ethtool_stats(struct net_device *dev,
506 else { 506 else {
507 /* If supported, for new GMAC chips expose the MMC counters */ 507 /* If supported, for new GMAC chips expose the MMC counters */
508 if (priv->dma_cap.rmon) { 508 if (priv->dma_cap.rmon) {
509 dwmac_mmc_read(priv->ioaddr, &priv->mmc); 509 dwmac_mmc_read(priv->mmcaddr, &priv->mmc);
510 510
511 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) { 511 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
512 char *p; 512 char *p;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 1186ac902bec..00e508498a81 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1450,12 +1450,14 @@ static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1450static void stmmac_mmc_setup(struct stmmac_priv *priv) 1450static void stmmac_mmc_setup(struct stmmac_priv *priv)
1451{ 1451{
1452 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1452 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1453 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1453 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1454 1454
1455 dwmac_mmc_intr_all_mask(priv->ioaddr); 1455 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1456
1457 dwmac_mmc_intr_all_mask(priv->mmcaddr);
1456 1458
1457 if (priv->dma_cap.rmon) { 1459 if (priv->dma_cap.rmon) {
1458 dwmac_mmc_ctrl(priv->ioaddr, mode); 1460 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1459 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1461 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1460 } else 1462 } else
1461 pr_info(" No MAC Management Counters available\n"); 1463 pr_info(" No MAC Management Counters available\n");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 10:57:54 -0400