Merge tag 'hisi-arm64-dt-for-4.16-v2' of git://github.com/hisilicon/linux-hisi into next/dt

ARM64: DT: Hisilicon SoC DT updates for 4.16

- Add SD card support for the hi3798cv200-poplar board
- Replace the PMU node with exact match for the hi3660 SoC
- Add cpu capacity-dmips-mhz information for the hi3660 SoC

* tag 'hisi-arm64-dt-for-4.16-v2' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information
  arm64: dts: hi3660: improve pmu description
  arm64: dts: hi3798cv200: add SD card support

Signed-off-by: Olof Johansson <olof@lixom.net>

3 files changed, 39 insertions, 9 deletions

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index ab0b95ba5ae5..63d4f9dca77f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -61,6 +61,7 @@
                         enable-method = "psci";
                         next-level-cache = <&A53_L2>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
+                        capacity-dmips-mhz = <592>;
                 };
 
                 cpu1: cpu@1 {
@@ -70,6 +71,7 @@
                         enable-method = "psci";
                         next-level-cache = <&A53_L2>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
+                        capacity-dmips-mhz = <592>;
                 };
 
                 cpu2: cpu@2 {
@@ -79,6 +81,7 @@
                         enable-method = "psci";
                         next-level-cache = <&A53_L2>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
+                        capacity-dmips-mhz = <592>;
                 };
 
                 cpu3: cpu@3 {
@@ -88,6 +91,7 @@
                         enable-method = "psci";
                         next-level-cache = <&A53_L2>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
+                        capacity-dmips-mhz = <592>;
                 };
 
                 cpu4: cpu@100 {
@@ -101,6 +105,7 @@
                                         &CPU_SLEEP
                                         &CLUSTER_SLEEP_1
                         >;
+                        capacity-dmips-mhz = <1024>;
                 };
 
                 cpu5: cpu@101 {
@@ -114,6 +119,7 @@
                                         &CPU_SLEEP
                                         &CLUSTER_SLEEP_1
                         >;
+                        capacity-dmips-mhz = <1024>;
                 };
 
                 cpu6: cpu@102 {
@@ -127,6 +133,7 @@
                                         &CPU_SLEEP
                                         &CLUSTER_SLEEP_1
                         >;
+                        capacity-dmips-mhz = <1024>;
                 };
 
                 cpu7: cpu@103 {
@@ -140,6 +147,7 @@
                                         &CPU_SLEEP
                                         &CLUSTER_SLEEP_1
                         >;
+                        capacity-dmips-mhz = <1024>;
                 };
 
                 idle-states {
@@ -203,21 +211,25 @@
                                          IRQ_TYPE_LEVEL_HIGH)>;
         };
 
-        pmu {
-                compatible = "arm,armv8-pmuv3";
+        a53-pmu {
+                compatible = "arm,cortex-a53-pmu";
                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                             <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
                 interrupt-affinity = <&cpu0>,
                                      <&cpu1>,
                                      <&cpu2>,
-                                     <&cpu3>,
-                                     <&cpu4>,
+                                     <&cpu3>;
+        };
+
+        a73-pmu {
+                compatible = "arm,cortex-a73-pmu";
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&cpu4>,
                                      <&cpu5>,
                                      <&cpu6>,
                                      <&cpu7>;
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
index a6fd13389f8d..4d5d644abb12 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
@@ -146,6 +146,12 @@
         status = "okay";
 };
 
+&sd0 {
+        bus-width = <4>;
+        cap-sd-highspeed;
+        status = "okay";
+};
+
 &spi0 {
         status = "okay";
         label = "LS-SPI0";
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 75865f8a862a..962bd79139e4 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -192,6 +192,18 @@
                         status = "disabled";
                 };
 
+                sd0: mmc@9820000 {
+                        compatible = "snps,dw-mshc";
+                        reg = <0x9820000 0x10000>;
+                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&crg HISTB_SDIO0_CIU_CLK>,
+                                 <&crg HISTB_SDIO0_BIU_CLK>;
+                        clock-names = "ciu", "biu";
+                        resets = <&crg 0x9c 4>;
+                        reset-names = "reset";
+                        status = "disabled";
+                };
+
                 emmc: mmc@9830000 {
                         compatible = "snps,dw-mshc";
                         reg = <0x9830000 0x10000>;