MIPS: Decode config3 register on Ingenic SoCs

XBurst misses a config2 register, so config3 decode was skipped in
decode_configs().

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: od@zcrc.me
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

1 files changed, 8 insertions, 0 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index fd77dbc29af9..a9c82338396a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1956,9 +1956,17 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
+
+        /*
+         * XBurst misses a config2 register, so config3 decode was skipped in
+         * decode_configs().
+         */
+        decode_config3(c);
+
         /* XBurst does not implement the CP0 counter. */
         c->options &= ~MIPS_CPU_COUNTER;
         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
+
         switch (c->processor_id & PRID_IMP_MASK) {
         case PRID_IMP_XBURST:
                 c->cputype = CPU_XBURST;