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authorZhi Wang <zhi.a.wang@intel.com>2017-09-30 05:42:20 -0400
committerZhenyu Wang <zhenyuw@linux.intel.com>2017-12-05 22:33:20 -0500
commit365ad5df9caa1a7ebc73b8d70ab94bbf6a74268a (patch)
treea5c73e00505a06676ec2182d5bcdbb2f7c35db98
parentadd7e4fc2420e35f200e4aa13764708e62690e2e (diff)
drm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()
Since many emulation logic needs to convert the offset of ring registers into ring id, we export it for other caller which might need it. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> (cherry picked from commit 62a6a53786fc4b4e7543cc63b704dbb3f7df4c0f)
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c21
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio.h2
2 files changed, 17 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 44cd5ff5e97d..55cbdb022924 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -137,17 +137,26 @@ static int new_mmio_info(struct intel_gvt *gvt,
137 return 0; 137 return 0;
138} 138}
139 139
140static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 140/**
141 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id
142 * @gvt: a GVT device
143 * @offset: register offset
144 *
145 * Returns:
146 * Ring ID on success, negative error code if failed.
147 */
148int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
149 unsigned int offset)
141{ 150{
142 enum intel_engine_id id; 151 enum intel_engine_id id;
143 struct intel_engine_cs *engine; 152 struct intel_engine_cs *engine;
144 153
145 reg &= ~GENMASK(11, 0); 154 offset &= ~GENMASK(11, 0);
146 for_each_engine(engine, gvt->dev_priv, id) { 155 for_each_engine(engine, gvt->dev_priv, id) {
147 if (engine->mmio_base == reg) 156 if (engine->mmio_base == offset)
148 return id; 157 return id;
149 } 158 }
150 return -1; 159 return -ENODEV;
151} 160}
152 161
153#define offset_to_fence_num(offset) \ 162#define offset_to_fence_num(offset) \
@@ -1409,7 +1418,7 @@ static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1409static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1418static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1410 void *p_data, unsigned int bytes) 1419 void *p_data, unsigned int bytes)
1411{ 1420{
1412 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1421 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1413 struct intel_vgpu_execlist *execlist; 1422 struct intel_vgpu_execlist *execlist;
1414 u32 data = *(u32 *)p_data; 1423 u32 data = *(u32 *)p_data;
1415 int ret = 0; 1424 int ret = 0;
@@ -1436,7 +1445,7 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1436 void *p_data, unsigned int bytes) 1445 void *p_data, unsigned int bytes)
1437{ 1446{
1438 u32 data = *(u32 *)p_data; 1447 u32 data = *(u32 *)p_data;
1439 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1448 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1440 bool enable_execlist; 1449 bool enable_execlist;
1441 1450
1442 write_vreg(vgpu, offset, p_data, bytes); 1451 write_vreg(vgpu, offset, p_data, bytes);
diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h
index 32cd64ddad26..dbc04ad2c7a1 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.h
+++ b/drivers/gpu/drm/i915/gvt/mmio.h
@@ -65,6 +65,8 @@ struct intel_gvt_mmio_info {
65 struct hlist_node node; 65 struct hlist_node node;
66}; 66};
67 67
68int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
69 unsigned int reg);
68unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt); 70unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
69bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device); 71bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);
70 72