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authorAlexandre Courbot <acourbot@nvidia.com>2017-02-16 01:50:27 -0500
committerBen Skeggs <bskeggs@redhat.com>2017-03-07 02:05:16 -0500
commit36510adde3d9c073a538e441c38515b7741d1732 (patch)
treee8060b33ce9910e0d86b1eea6c3f96db57540901
parent424321befd2102dc1609e3ae280a28eab61c522b (diff)
drm/nouveau/gp10x: enable secboot and GR
All the bricks are in place for secure boot to be enabled. This in turn makes GR usable so enable them all. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index cf76d6c657ba..f0a77c5fd16a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -2200,6 +2200,9 @@ nv132_chipset = {
2200 .ltc = gp100_ltc_new, 2200 .ltc = gp100_ltc_new,
2201 .mc = gp100_mc_new, 2201 .mc = gp100_mc_new,
2202 .mmu = gf100_mmu_new, 2202 .mmu = gf100_mmu_new,
2203 .secboot = gp102_secboot_new,
2204 .sec2 = gp102_sec2_new,
2205 .nvdec = gp102_nvdec_new,
2203 .pci = gp100_pci_new, 2206 .pci = gp100_pci_new,
2204 .pmu = gp102_pmu_new, 2207 .pmu = gp102_pmu_new,
2205 .timer = gk20a_timer_new, 2208 .timer = gk20a_timer_new,
@@ -2211,6 +2214,8 @@ nv132_chipset = {
2211 .disp = gp102_disp_new, 2214 .disp = gp102_disp_new,
2212 .dma = gf119_dma_new, 2215 .dma = gf119_dma_new,
2213 .fifo = gp100_fifo_new, 2216 .fifo = gp100_fifo_new,
2217 .gr = gp102_gr_new,
2218 .sw = gf100_sw_new,
2214}; 2219};
2215 2220
2216static const struct nvkm_device_chip 2221static const struct nvkm_device_chip
@@ -2229,6 +2234,9 @@ nv134_chipset = {
2229 .ltc = gp100_ltc_new, 2234 .ltc = gp100_ltc_new,
2230 .mc = gp100_mc_new, 2235 .mc = gp100_mc_new,
2231 .mmu = gf100_mmu_new, 2236 .mmu = gf100_mmu_new,
2237 .secboot = gp102_secboot_new,
2238 .sec2 = gp102_sec2_new,
2239 .nvdec = gp102_nvdec_new,
2232 .pci = gp100_pci_new, 2240 .pci = gp100_pci_new,
2233 .pmu = gp102_pmu_new, 2241 .pmu = gp102_pmu_new,
2234 .timer = gk20a_timer_new, 2242 .timer = gk20a_timer_new,
@@ -2240,6 +2248,8 @@ nv134_chipset = {
2240 .disp = gp102_disp_new, 2248 .disp = gp102_disp_new,
2241 .dma = gf119_dma_new, 2249 .dma = gf119_dma_new,
2242 .fifo = gp100_fifo_new, 2250 .fifo = gp100_fifo_new,
2251 .gr = gp102_gr_new,
2252 .sw = gf100_sw_new,
2243}; 2253};
2244 2254
2245static const struct nvkm_device_chip 2255static const struct nvkm_device_chip
@@ -2258,6 +2268,9 @@ nv136_chipset = {
2258 .ltc = gp100_ltc_new, 2268 .ltc = gp100_ltc_new,
2259 .mc = gp100_mc_new, 2269 .mc = gp100_mc_new,
2260 .mmu = gf100_mmu_new, 2270 .mmu = gf100_mmu_new,
2271 .secboot = gp102_secboot_new,
2272 .sec2 = gp102_sec2_new,
2273 .nvdec = gp102_nvdec_new,
2261 .pci = gp100_pci_new, 2274 .pci = gp100_pci_new,
2262 .pmu = gp102_pmu_new, 2275 .pmu = gp102_pmu_new,
2263 .timer = gk20a_timer_new, 2276 .timer = gk20a_timer_new,
@@ -2269,6 +2282,8 @@ nv136_chipset = {
2269 .disp = gp102_disp_new, 2282 .disp = gp102_disp_new,
2270 .dma = gf119_dma_new, 2283 .dma = gf119_dma_new,
2271 .fifo = gp100_fifo_new, 2284 .fifo = gp100_fifo_new,
2285 .gr = gp102_gr_new,
2286 .sw = gf100_sw_new,
2272}; 2287};
2273 2288
2274static int 2289static int