PCI: Cleanup register definition width and whitespace

Follow the file conventions of: - register offsets not indented - fields within a register indented one space - field masks use same width as register - register field values indented an additional space No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
author: Bjorn Helgaas <bhelgaas@google.com> 2019-02-04 15:50:14 -0500
committer: Bjorn Helgaas <bhelgaas@google.com> 2019-03-22 13:00:03 -0400
commit: 35d0a06dad2220d62042fd1a91a216d17744e724 (patch)
tree: fd14df36a545973a8f32b1eb3ce16b201818cf55
parent: 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff)
1 files changed, 65 insertions, 67 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 5c98133f2c94..f7d3e7831fa8 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
 /*
- *      pci_regs.h
- *
 *      PCI standard defines
 *      Copyright 1994, Drew Eckhardt
 *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
@@ -15,7 +13,7 @@
 *      PCI System Design Guide
 *
 *      For HyperTransport information, please consult the following manuals
- *      from http://www.hypertransport.org
+ *      from http://www.hypertransport.org :
 *
 *      The HyperTransport I/O Link Specification
 */
@@ -301,7 +299,7 @@
 #define  PCI_SID_ESR_FIC        0x20    /* First In Chassis Flag */
 #define PCI_SID_CHASSIS_NR      3       /* Chassis Number */
-/* Message Signalled Interrupts registers */
+/* Message Signalled Interrupt registers */
 #define PCI_MSI_FLAGS           2       /* Message Control */
 #define  PCI_MSI_FLAGS_ENABLE   0x0001  /* MSI feature enabled */
@@ -319,7 +317,7 @@
 #define PCI_MSI_MASK_64         16      /* Mask bits register for 64-bit devices */
 #define PCI_MSI_PENDING_64      20      /* Pending intrs for 64-bit devices */
-/* MSI-X registers */
+/* MSI-X registers (in MSI-X capability) */
 #define PCI_MSIX_FLAGS          2       /* Message Control */
 #define  PCI_MSIX_FLAGS_QSIZE   0x07FF  /* Table size */
 #define  PCI_MSIX_FLAGS_MASKALL 0x4000  /* Mask all vectors for this function */
@@ -333,13 +331,13 @@
 #define PCI_MSIX_FLAGS_BIRMASK  PCI_MSIX_PBA_BIR /* deprecated */
 #define PCI_CAP_MSIX_SIZEOF     12      /* size of MSIX registers */
-/* MSI-X Table entry format */
+/* MSI-X Table entry format (in memory mapped by a BAR) */
 #define PCI_MSIX_ENTRY_SIZE             16
-#define  PCI_MSIX_ENTRY_LOWER_ADDR      0
+#define PCI_MSIX_ENTRY_LOWER_ADDR       0  /* Message Address */
-#define  PCI_MSIX_ENTRY_UPPER_ADDR      4
+#define PCI_MSIX_ENTRY_UPPER_ADDR       4  /* Message Upper Address */
-#define  PCI_MSIX_ENTRY_DATA            8
+#define PCI_MSIX_ENTRY_DATA             8  /* Message Data */
-#define  PCI_MSIX_ENTRY_VECTOR_CTRL     12
+#define PCI_MSIX_ENTRY_VECTOR_CTRL      12 /* Vector Control */
-#define   PCI_MSIX_ENTRY_CTRL_MASKBIT   1
+#define  PCI_MSIX_ENTRY_CTRL_MASKBIT    0x00000001
 /* CompactPCI Hotswap Register */
@@ -465,19 +463,19 @@
 /* PCI Express capability registers */
 #define PCI_EXP_FLAGS           2       /* Capabilities register */
-#define PCI_EXP_FLAGS_VERS      0x000f  /* Capability version */
+#define  PCI_EXP_FLAGS_VERS     0x000f  /* Capability version */
-#define PCI_EXP_FLAGS_TYPE      0x00f0  /* Device/Port type */
+#define  PCI_EXP_FLAGS_TYPE     0x00f0  /* Device/Port type */
-#define  PCI_EXP_TYPE_ENDPOINT  0x0     /* Express Endpoint */
+#define   PCI_EXP_TYPE_ENDPOINT    0x0  /* Express Endpoint */
-#define  PCI_EXP_TYPE_LEG_END   0x1     /* Legacy Endpoint */
+#define   PCI_EXP_TYPE_LEG_END     0x1  /* Legacy Endpoint */
-#define  PCI_EXP_TYPE_ROOT_PORT 0x4     /* Root Port */
+#define   PCI_EXP_TYPE_ROOT_PORT   0x4  /* Root Port */
-#define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
+#define   PCI_EXP_TYPE_UPSTREAM    0x5  /* Upstream Port */
-#define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
+#define   PCI_EXP_TYPE_DOWNSTREAM  0x6  /* Downstream Port */
-#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCIe to PCI/PCI-X Bridge */
+#define   PCI_EXP_TYPE_PCI_BRIDGE  0x7  /* PCIe to PCI/PCI-X Bridge */
-#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8   /* PCI/PCI-X to PCIe Bridge */
+#define   PCI_EXP_TYPE_PCIE_BRIDGE 0x8  /* PCI/PCI-X to PCIe Bridge */
-#define  PCI_EXP_TYPE_RC_END    0x9     /* Root Complex Integrated Endpoint */
+#define   PCI_EXP_TYPE_RC_END      0x9  /* Root Complex Integrated Endpoint */
-#define  PCI_EXP_TYPE_RC_EC     0xa     /* Root Complex Event Collector */
+#define   PCI_EXP_TYPE_RC_EC       0xa  /* Root Complex Event Collector */
-#define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
+#define  PCI_EXP_FLAGS_SLOT     0x0100  /* Slot implemented */
-#define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
+#define  PCI_EXP_FLAGS_IRQ      0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP          4       /* Device capabilities */
 #define  PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
 #define  PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
@@ -616,8 +614,8 @@
 #define PCI_EXP_RTCAP           30      /* Root Capabilities */
 #define  PCI_EXP_RTCAP_CRSVIS   0x0001  /* CRS Software Visibility capability */
 #define PCI_EXP_RTSTA           32      /* Root Status */
-#define PCI_EXP_RTSTA_PME       0x00010000 /* PME status */
+#define  PCI_EXP_RTSTA_PME      0x00010000 /* PME status */
-#define PCI_EXP_RTSTA_PENDING   0x00020000 /* PME pending */
+#define  PCI_EXP_RTSTA_PENDING  0x00020000 /* PME pending */
 /*
 * The Device Capabilities 2, Device Status 2, Device Control 2,
 * Link Capabilities 2, Link Status 2, Link Control 2,
@@ -637,13 +635,13 @@
 #define  PCI_EXP_DEVCAP2_OBFF_MASK      0x000c0000 /* OBFF support mechanism */
 #define  PCI_EXP_DEVCAP2_OBFF_MSG       0x00040000 /* New message signaling */
 #define  PCI_EXP_DEVCAP2_OBFF_WAKE      0x00080000 /* Re-use WAKE# for OBFF */
-#define PCI_EXP_DEVCAP2_EE_PREFIX       0x00200000 /* End-End TLP Prefix */
+#define  PCI_EXP_DEVCAP2_EE_PREFIX      0x00200000 /* End-End TLP Prefix */
 #define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
 #define  PCI_EXP_DEVCTL2_COMP_TIMEOUT   0x000f  /* Completion Timeout Value */
 #define  PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010  /* Completion Timeout Disable */
 #define  PCI_EXP_DEVCTL2_ARI            0x0020  /* Alternative Routing-ID */
-#define PCI_EXP_DEVCTL2_ATOMIC_REQ      0x0040  /* Set Atomic requests */
+#define  PCI_EXP_DEVCTL2_ATOMIC_REQ     0x0040  /* Set Atomic requests */
-#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
+#define  PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
 #define  PCI_EXP_DEVCTL2_IDO_REQ_EN     0x0100  /* Allow IDO for requests */
 #define  PCI_EXP_DEVCTL2_IDO_CMP_EN     0x0200  /* Allow IDO for completions */
 #define  PCI_EXP_DEVCTL2_LTR_EN         0x0400  /* Enable LTR mechanism */
@@ -659,11 +657,11 @@
 #define  PCI_EXP_LNKCAP2_SLS_16_0GB     0x00000010 /* Supported Speed 16GT/s */
 #define  PCI_EXP_LNKCAP2_CROSSLINK      0x00000100 /* Crosslink supported */
 #define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
-#define PCI_EXP_LNKCTL2_TLS             0x000f
+#define  PCI_EXP_LNKCTL2_TLS            0x000f
-#define PCI_EXP_LNKCTL2_TLS_2_5GT       0x0001 /* Supported Speed 2.5GT/s */
+#define  PCI_EXP_LNKCTL2_TLS_2_5GT      0x0001 /* Supported Speed 2.5GT/s */
-#define PCI_EXP_LNKCTL2_TLS_5_0GT       0x0002 /* Supported Speed 5GT/s */
+#define  PCI_EXP_LNKCTL2_TLS_5_0GT      0x0002 /* Supported Speed 5GT/s */
-#define PCI_EXP_LNKCTL2_TLS_8_0GT       0x0003 /* Supported Speed 8GT/s */
+#define  PCI_EXP_LNKCTL2_TLS_8_0GT      0x0003 /* Supported Speed 8GT/s */
-#define PCI_EXP_LNKCTL2_TLS_16_0GT      0x0004 /* Supported Speed 16GT/s */
+#define  PCI_EXP_LNKCTL2_TLS_16_0GT     0x0004 /* Supported Speed 16GT/s */
 #define PCI_EXP_LNKSTA2         50      /* Link Status 2 */
 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2  52      /* v2 endpoints with link end here */
 #define PCI_EXP_SLTCAP2         52      /* Slot Capabilities 2 */
@@ -752,18 +750,18 @@
 #define  PCI_ERR_CAP_ECRC_CHKE  0x00000100      /* ECRC Check Enable */
 #define PCI_ERR_HEADER_LOG      28      /* Header Log Register (16 bytes) */
 #define PCI_ERR_ROOT_COMMAND    44      /* Root Error Command */
-#define PCI_ERR_ROOT_CMD_COR_EN         0x00000001 /* Correctable Err Reporting Enable */
+#define  PCI_ERR_ROOT_CMD_COR_EN        0x00000001 /* Correctable Err Reporting Enable */
-#define PCI_ERR_ROOT_CMD_NONFATAL_EN    0x00000002 /* Non-Fatal Err Reporting Enable */
+#define  PCI_ERR_ROOT_CMD_NONFATAL_EN   0x00000002 /* Non-Fatal Err Reporting Enable */
-#define PCI_ERR_ROOT_CMD_FATAL_EN       0x00000004 /* Fatal Err Reporting Enable */
+#define  PCI_ERR_ROOT_CMD_FATAL_EN      0x00000004 /* Fatal Err Reporting Enable */
 #define PCI_ERR_ROOT_STATUS     48
-#define PCI_ERR_ROOT_COR_RCV            0x00000001 /* ERR_COR Received */
+#define  PCI_ERR_ROOT_COR_RCV           0x00000001 /* ERR_COR Received */
-#define PCI_ERR_ROOT_MULTI_COR_RCV      0x00000002 /* Multiple ERR_COR */
+#define  PCI_ERR_ROOT_MULTI_COR_RCV     0x00000002 /* Multiple ERR_COR */
-#define PCI_ERR_ROOT_UNCOR_RCV          0x00000004 /* ERR_FATAL/NONFATAL */
+#define  PCI_ERR_ROOT_UNCOR_RCV         0x00000004 /* ERR_FATAL/NONFATAL */
-#define PCI_ERR_ROOT_MULTI_UNCOR_RCV    0x00000008 /* Multiple FATAL/NONFATAL */
+#define  PCI_ERR_ROOT_MULTI_UNCOR_RCV   0x00000008 /* Multiple FATAL/NONFATAL */
-#define PCI_ERR_ROOT_FIRST_FATAL        0x00000010 /* First UNC is Fatal */
+#define  PCI_ERR_ROOT_FIRST_FATAL       0x00000010 /* First UNC is Fatal */
-#define PCI_ERR_ROOT_NONFATAL_RCV       0x00000020 /* Non-Fatal Received */
+#define  PCI_ERR_ROOT_NONFATAL_RCV      0x00000020 /* Non-Fatal Received */
-#define PCI_ERR_ROOT_FATAL_RCV          0x00000040 /* Fatal Received */
+#define  PCI_ERR_ROOT_FATAL_RCV         0x00000040 /* Fatal Received */
-#define PCI_ERR_ROOT_AER_IRQ            0xf8000000 /* Advanced Error Interrupt Message Number */
+#define  PCI_ERR_ROOT_AER_IRQ           0xf8000000 /* Advanced Error Interrupt Message Number */
 #define PCI_ERR_ROOT_ERR_SRC    52      /* Error Source Identification */
 /* Virtual Channel */
@@ -875,12 +873,12 @@
 /* Page Request Interface */
 #define PCI_PRI_CTRL            0x04    /* PRI control register */
-#define  PCI_PRI_CTRL_ENABLE    0x01    /* Enable */
+#define  PCI_PRI_CTRL_ENABLE    0x0001  /* Enable */
-#define  PCI_PRI_CTRL_RESET     0x02    /* Reset */
+#define  PCI_PRI_CTRL_RESET     0x0002  /* Reset */
 #define PCI_PRI_STATUS          0x06    /* PRI status register */
-#define  PCI_PRI_STATUS_RF      0x001   /* Response Failure */
+#define  PCI_PRI_STATUS_RF      0x0001  /* Response Failure */
-#define  PCI_PRI_STATUS_UPRGI   0x002   /* Unexpected PRG index */
+#define  PCI_PRI_STATUS_UPRGI   0x0002  /* Unexpected PRG index */
-#define  PCI_PRI_STATUS_STOPPED 0x100   /* PRI Stopped */
+#define  PCI_PRI_STATUS_STOPPED 0x0100  /* PRI Stopped */
 #define  PCI_PRI_STATUS_PASID   0x8000  /* PRG Response PASID Required */
 #define PCI_PRI_MAX_REQ         0x08    /* PRI max reqs supported */
 #define PCI_PRI_ALLOC_REQ       0x0c    /* PRI max reqs allowed */
@@ -898,16 +896,16 @@
 /* Single Root I/O Virtualization */
 #define PCI_SRIOV_CAP           0x04    /* SR-IOV Capabilities */
-#define  PCI_SRIOV_CAP_VFM      0x01    /* VF Migration Capable */
+#define  PCI_SRIOV_CAP_VFM      0x00000001  /* VF Migration Capable */
 #define  PCI_SRIOV_CAP_INTR(x)  ((x) >> 21) /* Interrupt Message Number */
 #define PCI_SRIOV_CTRL          0x08    /* SR-IOV Control */
-#define  PCI_SRIOV_CTRL_VFE     0x01    /* VF Enable */
+#define  PCI_SRIOV_CTRL_VFE     0x0001  /* VF Enable */
-#define  PCI_SRIOV_CTRL_VFM     0x02    /* VF Migration Enable */
+#define  PCI_SRIOV_CTRL_VFM     0x0002  /* VF Migration Enable */
-#define  PCI_SRIOV_CTRL_INTR    0x04    /* VF Migration Interrupt Enable */
+#define  PCI_SRIOV_CTRL_INTR    0x0004  /* VF Migration Interrupt Enable */
-#define  PCI_SRIOV_CTRL_MSE     0x08    /* VF Memory Space Enable */
+#define  PCI_SRIOV_CTRL_MSE     0x0008  /* VF Memory Space Enable */
-#define  PCI_SRIOV_CTRL_ARI     0x10    /* ARI Capable Hierarchy */
+#define  PCI_SRIOV_CTRL_ARI     0x0010  /* ARI Capable Hierarchy */
 #define PCI_SRIOV_STATUS        0x0a    /* SR-IOV Status */
-#define  PCI_SRIOV_STATUS_VFM   0x01    /* VF Migration Status */
+#define  PCI_SRIOV_STATUS_VFM   0x0001  /* VF Migration Status */
 #define PCI_SRIOV_INITIAL_VF    0x0c    /* Initial VFs */
 #define PCI_SRIOV_TOTAL_VF      0x0e    /* Total VFs */
 #define PCI_SRIOV_NUM_VF        0x10    /* Number of VFs */
@@ -937,13 +935,13 @@
 /* Access Control Service */
 #define PCI_ACS_CAP             0x04    /* ACS Capability Register */
-#define  PCI_ACS_SV             0x01    /* Source Validation */
+#define  PCI_ACS_SV             0x0001  /* Source Validation */
-#define  PCI_ACS_TB             0x02    /* Translation Blocking */
+#define  PCI_ACS_TB             0x0002  /* Translation Blocking */
-#define  PCI_ACS_RR             0x04    /* P2P Request Redirect */
+#define  PCI_ACS_RR             0x0004  /* P2P Request Redirect */
-#define  PCI_ACS_CR             0x08    /* P2P Completion Redirect */
+#define  PCI_ACS_CR             0x0008  /* P2P Completion Redirect */
-#define  PCI_ACS_UF             0x10    /* Upstream Forwarding */
+#define  PCI_ACS_UF             0x0010  /* Upstream Forwarding */
-#define  PCI_ACS_EC             0x20    /* P2P Egress Control */
+#define  PCI_ACS_EC             0x0020  /* P2P Egress Control */
-#define  PCI_ACS_DT             0x40    /* Direct Translated P2P */
+#define  PCI_ACS_DT             0x0040  /* Direct Translated P2P */
 #define PCI_ACS_EGRESS_BITS     0x05    /* ACS Egress Control Vector Size */
 #define PCI_ACS_CTRL            0x06    /* ACS Control Register */
 #define PCI_ACS_EGRESS_CTL_V    0x08    /* ACS Egress Control Vector */
@@ -993,9 +991,9 @@
 #define  PCI_EXP_DPC_CAP_DL_ACTIVE      0x1000  /* ERR_COR signal on DL_Active supported */
 #define PCI_EXP_DPC_CTL                 6       /* DPC control */
-#define  PCI_EXP_DPC_CTL_EN_FATAL       0x0001  /* Enable trigger on ERR_FATAL message */
+#define  PCI_EXP_DPC_CTL_EN_FATAL       0x0001  /* Enable trigger on ERR_FATAL message */
-#define  PCI_EXP_DPC_CTL_EN_NONFATAL    0x0002  /* Enable trigger on ERR_NONFATAL message */
+#define  PCI_EXP_DPC_CTL_EN_NONFATAL    0x0002  /* Enable trigger on ERR_NONFATAL message */
-#define  PCI_EXP_DPC_CTL_INT_EN         0x0008  /* DPC Interrupt Enable */
+#define  PCI_EXP_DPC_CTL_INT_EN         0x0008  /* DPC Interrupt Enable */
 #define PCI_EXP_DPC_STATUS              8       /* DPC Status */
 #define  PCI_EXP_DPC_STATUS_TRIGGER         0x0001 /* Trigger Status */
author	Bjorn Helgaas <bhelgaas@google.com>	2019-02-04 15:50:14 -0500
committer	Bjorn Helgaas <bhelgaas@google.com>	2019-03-22 13:00:03 -0400
commit	35d0a06dad2220d62042fd1a91a216d17744e724 (patch)
tree	fd14df36a545973a8f32b1eb3ce16b201818cf55
parent	9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff)

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 5c98133f2c94..f7d3e7831fa8 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h
@@ -1,7 +1,5 @@
1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/*	2	/*
3	* pci_regs.h
4	*
5	* PCI standard defines	3	* PCI standard defines
6	* Copyright 1994, Drew Eckhardt	4	* Copyright 1994, Drew Eckhardt
7	* Copyright 1997--1999 Martin Mares <mj@ucw.cz>	5	* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
@@ -15,7 +13,7 @@
15	* PCI System Design Guide	13	* PCI System Design Guide
16	*	14	*
17	* For HyperTransport information, please consult the following manuals	15	* For HyperTransport information, please consult the following manuals
18	* from http://www.hypertransport.org	16	* from http://www.hypertransport.org :
19	*	17	*
20	* The HyperTransport I/O Link Specification	18	* The HyperTransport I/O Link Specification
21	*/	19	*/
@@ -301,7 +299,7 @@
301	#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */	299	#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
302	#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */	300	#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
303		301
304	/* Message Signalled Interrupts registers */	302	/* Message Signalled Interrupt registers */
305		303
306	#define PCI_MSI_FLAGS 2 /* Message Control */	304	#define PCI_MSI_FLAGS 2 /* Message Control */
307	#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */	305	#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
@@ -319,7 +317,7 @@
319	#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */	317	#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
320	#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */	318	#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
321		319
322	/* MSI-X registers */	320	/* MSI-X registers (in MSI-X capability) */
323	#define PCI_MSIX_FLAGS 2 /* Message Control */	321	#define PCI_MSIX_FLAGS 2 /* Message Control */
324	#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */	322	#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */
325	#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */	323	#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
@@ -333,13 +331,13 @@
333	#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */	331	#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */
334	#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */	332	#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
335		333
336	/* MSI-X Table entry format */	334	/* MSI-X Table entry format (in memory mapped by a BAR) */
337	#define PCI_MSIX_ENTRY_SIZE 16	335	#define PCI_MSIX_ENTRY_SIZE 16
338	#define PCI_MSIX_ENTRY_LOWER_ADDR 0	336	#define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */
339	#define PCI_MSIX_ENTRY_UPPER_ADDR 4	337	#define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */
340	#define PCI_MSIX_ENTRY_DATA 8	338	#define PCI_MSIX_ENTRY_DATA 8 /* Message Data */
341	#define PCI_MSIX_ENTRY_VECTOR_CTRL 12	339	#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */
342	#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1	340	#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
343		341
344	/* CompactPCI Hotswap Register */	342	/* CompactPCI Hotswap Register */
345		343
@@ -465,19 +463,19 @@
465	/* PCI Express capability registers */	463	/* PCI Express capability registers */
466		464
467	#define PCI_EXP_FLAGS 2 /* Capabilities register */	465	#define PCI_EXP_FLAGS 2 /* Capabilities register */
468	#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */	466	#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
469	#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */	467	#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
470	#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */	468	#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
471	#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */	469	#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
472	#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */	470	#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
473	#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */	471	#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
474	#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */	472	#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
475	#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */	473	#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
476	#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */	474	#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
477	#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */	475	#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
478	#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */	476	#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
479	#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */	477	#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
480	#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */	478	#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
481	#define PCI_EXP_DEVCAP 4 /* Device capabilities */	479	#define PCI_EXP_DEVCAP 4 /* Device capabilities */
482	#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */	480	#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
483	#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */	481	#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
@@ -616,8 +614,8 @@
616	#define PCI_EXP_RTCAP 30 /* Root Capabilities */	614	#define PCI_EXP_RTCAP 30 /* Root Capabilities */
617	#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */	615	#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
618	#define PCI_EXP_RTSTA 32 /* Root Status */	616	#define PCI_EXP_RTSTA 32 /* Root Status */
619	#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */	617	#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
620	#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */	618	#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
621	/*	619	/*
622	* The Device Capabilities 2, Device Status 2, Device Control 2,	620	* The Device Capabilities 2, Device Status 2, Device Control 2,
623	* Link Capabilities 2, Link Status 2, Link Control 2,	621	* Link Capabilities 2, Link Status 2, Link Control 2,
@@ -637,13 +635,13 @@
637	#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */	635	#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
638	#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */	636	#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
639	#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */	637	#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
640	#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */	638	#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
641	#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */	639	#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
642	#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */	640	#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
643	#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */	641	#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
644	#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */	642	#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
645	#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */	643	#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
646	#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */	644	#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
647	#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */	645	#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
648	#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */	646	#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
649	#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */	647	#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
@@ -659,11 +657,11 @@
659	#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */	657	#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
660	#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */	658	#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
661	#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */	659	#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
662	#define PCI_EXP_LNKCTL2_TLS 0x000f	660	#define PCI_EXP_LNKCTL2_TLS 0x000f
663	#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */	661	#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
664	#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */	662	#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
665	#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */	663	#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
666	#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */	664	#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
667	#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */	665	#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
668	#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */	666	#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
669	#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */	667	#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
@@ -752,18 +750,18 @@
752	#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */	750	#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
753	#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */	751	#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
754	#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */	752	#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
755	#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */	753	#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
756	#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */	754	#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
757	#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */	755	#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
758	#define PCI_ERR_ROOT_STATUS 48	756	#define PCI_ERR_ROOT_STATUS 48
759	#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */	757	#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
760	#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */	758	#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */
761	#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */	759	#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */
762	#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */	760	#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */
763	#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */	761	#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
764	#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */	762	#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
765	#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */	763	#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
766	#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */	764	#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
767	#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */	765	#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
768		766
769	/* Virtual Channel */	767	/* Virtual Channel */
@@ -875,12 +873,12 @@
875		873
876	/* Page Request Interface */	874	/* Page Request Interface */
877	#define PCI_PRI_CTRL 0x04 /* PRI control register */	875	#define PCI_PRI_CTRL 0x04 /* PRI control register */
878	#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */	876	#define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */
879	#define PCI_PRI_CTRL_RESET 0x02 /* Reset */	877	#define PCI_PRI_CTRL_RESET 0x0002 /* Reset */
880	#define PCI_PRI_STATUS 0x06 /* PRI status register */	878	#define PCI_PRI_STATUS 0x06 /* PRI status register */
881	#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */	879	#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */
882	#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */	880	#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */
883	#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */	881	#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */
884	#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */	882	#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */
885	#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */	883	#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
886	#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */	884	#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
@@ -898,16 +896,16 @@
898		896
899	/* Single Root I/O Virtualization */	897	/* Single Root I/O Virtualization */
900	#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */	898	#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
901	#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */	899	#define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */
902	#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */	900	#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
903	#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */	901	#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
904	#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */	902	#define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */
905	#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */	903	#define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */
906	#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */	904	#define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */
907	#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */	905	#define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */
908	#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */	906	#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
909	#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */	907	#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
910	#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */	908	#define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */
911	#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */	909	#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
912	#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */	910	#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
913	#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */	911	#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
@@ -937,13 +935,13 @@
937		935
938	/* Access Control Service */	936	/* Access Control Service */
939	#define PCI_ACS_CAP 0x04 /* ACS Capability Register */	937	#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
940	#define PCI_ACS_SV 0x01 /* Source Validation */	938	#define PCI_ACS_SV 0x0001 /* Source Validation */
941	#define PCI_ACS_TB 0x02 /* Translation Blocking */	939	#define PCI_ACS_TB 0x0002 /* Translation Blocking */
942	#define PCI_ACS_RR 0x04 /* P2P Request Redirect */	940	#define PCI_ACS_RR 0x0004 /* P2P Request Redirect */
943	#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */	941	#define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */
944	#define PCI_ACS_UF 0x10 /* Upstream Forwarding */	942	#define PCI_ACS_UF 0x0010 /* Upstream Forwarding */
945	#define PCI_ACS_EC 0x20 /* P2P Egress Control */	943	#define PCI_ACS_EC 0x0020 /* P2P Egress Control */
946	#define PCI_ACS_DT 0x40 /* Direct Translated P2P */	944	#define PCI_ACS_DT 0x0040 /* Direct Translated P2P */
947	#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */	945	#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
948	#define PCI_ACS_CTRL 0x06 /* ACS Control Register */	946	#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
949	#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */	947	#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
@@ -993,9 +991,9 @@
993	#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */	991	#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
994		992
995	#define PCI_EXP_DPC_CTL 6 /* DPC control */	993	#define PCI_EXP_DPC_CTL 6 /* DPC control */
996	#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */	994	#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
997	#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */	995	#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
998	#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */	996	#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
999		997
1000	#define PCI_EXP_DPC_STATUS 8 /* DPC Status */	998	#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
1001	#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */	999	#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */