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authorFlora Cui <Flora.Cui@amd.com>2016-12-15 03:26:58 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-12-20 19:43:30 -0500
commit3548f9a829738db1df2643c1db1a134d84b00fc4 (patch)
treefd9360e4381283b0be1ee60c874a0dfe51ff7dfd
parentf815b29cea0968df400f8c9f8b770ec02ec66906 (diff)
drm/amdgpu: update tile table for verde
Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c295
1 files changed, 293 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index aa4472343901..51bbd6e44dbb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -411,8 +411,299 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
411 break; 411 break;
412 } 412 }
413 413
414 if (adev->asic_type == CHIP_VERDE || 414 if (adev->asic_type == CHIP_VERDE) {
415 adev->asic_type == CHIP_OLAND || 415 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
416 switch (reg_offset) {
417 case 0:
418 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
419 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
420 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
422 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
423 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
424 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
425 NUM_BANKS(ADDR_SURF_16_BANK));
426 break;
427 case 1:
428 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
429 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
430 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
431 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
432 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
435 NUM_BANKS(ADDR_SURF_16_BANK));
436 break;
437 case 2:
438 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
439 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
440 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
441 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
442 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
443 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
444 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
445 NUM_BANKS(ADDR_SURF_16_BANK));
446 break;
447 case 3:
448 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
454 NUM_BANKS(ADDR_SURF_8_BANK) |
455 TILE_SPLIT(split_equal_to_row_size));
456 break;
457 case 4:
458 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
459 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
460 PIPE_CONFIG(ADDR_SURF_P4_8x16));
461 break;
462 case 5:
463 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
464 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
465 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
466 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
467 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
468 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
469 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
470 NUM_BANKS(ADDR_SURF_4_BANK));
471 break;
472 case 6:
473 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
474 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
475 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
476 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
477 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
480 NUM_BANKS(ADDR_SURF_4_BANK));
481 break;
482 case 7:
483 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
484 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
485 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
486 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
487 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
488 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
489 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
490 NUM_BANKS(ADDR_SURF_2_BANK));
491 break;
492 case 8:
493 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
494 break;
495 case 9:
496 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
497 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
498 PIPE_CONFIG(ADDR_SURF_P4_8x16));
499 break;
500 case 10:
501 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
502 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
503 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
504 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
505 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
508 NUM_BANKS(ADDR_SURF_16_BANK));
509 break;
510 case 11:
511 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
512 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
513 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
514 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
515 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
518 NUM_BANKS(ADDR_SURF_16_BANK));
519 break;
520 case 12:
521 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
522 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
523 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
528 NUM_BANKS(ADDR_SURF_16_BANK));
529 break;
530 case 13:
531 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
532 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
533 PIPE_CONFIG(ADDR_SURF_P4_8x16));
534 break;
535 case 14:
536 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
537 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
538 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
539 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
543 NUM_BANKS(ADDR_SURF_16_BANK));
544 break;
545 case 15:
546 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
547 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
548 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
549 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
550 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
553 NUM_BANKS(ADDR_SURF_16_BANK));
554 break;
555 case 16:
556 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
557 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
558 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
559 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
560 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
563 NUM_BANKS(ADDR_SURF_16_BANK));
564 break;
565 case 17:
566 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
568 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
572 NUM_BANKS(ADDR_SURF_16_BANK) |
573 TILE_SPLIT(split_equal_to_row_size));
574 break;
575 case 18:
576 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
577 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
578 PIPE_CONFIG(ADDR_SURF_P4_8x16));
579 break;
580 case 19:
581 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
582 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
583 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
584 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
587 NUM_BANKS(ADDR_SURF_16_BANK) |
588 TILE_SPLIT(split_equal_to_row_size));
589 break;
590 case 20:
591 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
592 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
593 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
597 NUM_BANKS(ADDR_SURF_16_BANK) |
598 TILE_SPLIT(split_equal_to_row_size));
599 break;
600 case 21:
601 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
602 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
603 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
604 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
608 NUM_BANKS(ADDR_SURF_8_BANK));
609 break;
610 case 22:
611 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
612 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
613 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
614 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
615 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
618 NUM_BANKS(ADDR_SURF_8_BANK));
619 break;
620 case 23:
621 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
623 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
628 NUM_BANKS(ADDR_SURF_4_BANK));
629 break;
630 case 24:
631 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
632 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
633 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
634 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
635 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
638 NUM_BANKS(ADDR_SURF_4_BANK));
639 break;
640 case 25:
641 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
643 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
645 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
648 NUM_BANKS(ADDR_SURF_2_BANK));
649 break;
650 case 26:
651 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
652 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
653 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
654 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
655 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
656 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
657 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
658 NUM_BANKS(ADDR_SURF_2_BANK));
659 break;
660 case 27:
661 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
662 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
663 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
664 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
668 NUM_BANKS(ADDR_SURF_2_BANK));
669 break;
670 case 28:
671 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
672 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
673 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
674 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
675 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
676 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
677 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
678 NUM_BANKS(ADDR_SURF_2_BANK));
679 break;
680 case 29:
681 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
683 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
684 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
688 NUM_BANKS(ADDR_SURF_2_BANK));
689 break;
690 case 30:
691 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
692 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
693 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
694 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
695 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
696 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
697 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
698 NUM_BANKS(ADDR_SURF_2_BANK));
699 break;
700 default:
701 continue;
702 }
703 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
704 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
705 }
706 } else if (adev->asic_type == CHIP_OLAND ||
416 adev->asic_type == CHIP_HAINAN) { 707 adev->asic_type == CHIP_HAINAN) {
417 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 708 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
418 switch (reg_offset) { 709 switch (reg_offset) {
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