diff options
author | Icenowy Zheng <icenowy@aosc.io> | 2017-12-22 07:22:33 -0500 |
---|---|---|
committer | Chen-Yu Tsai <wens@csie.org> | 2017-12-29 03:10:17 -0500 |
commit | 3525c7c3bd2b7b0b77bdb0ab46a7c5338e188a5a (patch) | |
tree | 3429afd4b7385d1470334b786ee161cd93e9b4f2 | |
parent | e952ca3c6b2ffdfbf9618e4bd3e9aad1ff3f5eb4 (diff) |
dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
The DE2 CCU is different on A83T and H3 -- the parent of the clocks on
A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed
when I develop the DE2 CCU driver.
Fix the binding by using different compatibles for A83T and H3, adding
notes for the PLL_DE usage on A83T, and change the binding example's
compatible from A83T to H3 (as it specifies the DE module clock).
Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-rw-r--r-- | Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index 631d27cd89d6..f2fa87c4765c 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt | |||
@@ -4,13 +4,14 @@ Allwinner Display Engine 2.0 Clock Control Binding | |||
4 | Required properties : | 4 | Required properties : |
5 | - compatible: must contain one of the following compatibles: | 5 | - compatible: must contain one of the following compatibles: |
6 | - "allwinner,sun8i-a83t-de2-clk" | 6 | - "allwinner,sun8i-a83t-de2-clk" |
7 | - "allwinner,sun8i-h3-de2-clk" | ||
7 | - "allwinner,sun8i-v3s-de2-clk" | 8 | - "allwinner,sun8i-v3s-de2-clk" |
8 | - "allwinner,sun50i-h5-de2-clk" | 9 | - "allwinner,sun50i-h5-de2-clk" |
9 | 10 | ||
10 | - reg: Must contain the registers base address and length | 11 | - reg: Must contain the registers base address and length |
11 | - clocks: phandle to the clocks feeding the display engine subsystem. | 12 | - clocks: phandle to the clocks feeding the display engine subsystem. |
12 | Three are needed: | 13 | Three are needed: |
13 | - "mod": the display engine module clock | 14 | - "mod": the display engine module clock (on A83T it's the DE PLL) |
14 | - "bus": the bus clock for the whole display engine subsystem | 15 | - "bus": the bus clock for the whole display engine subsystem |
15 | - clock-names: Must contain the clock names described just above | 16 | - clock-names: Must contain the clock names described just above |
16 | - resets: phandle to the reset control for the display engine subsystem. | 17 | - resets: phandle to the reset control for the display engine subsystem. |
@@ -19,7 +20,7 @@ Required properties : | |||
19 | 20 | ||
20 | Example: | 21 | Example: |
21 | de2_clocks: clock@1000000 { | 22 | de2_clocks: clock@1000000 { |
22 | compatible = "allwinner,sun8i-a83t-de2-clk"; | 23 | compatible = "allwinner,sun8i-h3-de2-clk"; |
23 | reg = <0x01000000 0x100000>; | 24 | reg = <0x01000000 0x100000>; |
24 | clocks = <&ccu CLK_BUS_DE>, | 25 | clocks = <&ccu CLK_BUS_DE>, |
25 | <&ccu CLK_DE>; | 26 | <&ccu CLK_DE>; |