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authorLinus Torvalds <torvalds@linux-foundation.org>2015-11-09 19:32:13 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-11-09 19:32:13 -0500
commit3510ca19a82ba4c6a17af79c1f0448622a406efa (patch)
tree79b9e734100e40f379e9b4c3c50d261c3cdc2fa8
parente4da7e9a54649d6877ac23828ff93ce7191eae2c (diff)
parentafaa7c542cc9c4d8a99ba252a8ea5e8bc7c897e2 (diff)
Merge tag 'xtensa-20151108' of git://github.com/czankel/xtensa-linux
Pull xtensa updates from Chris Zankel: - fix remaining issues with noMMU cores - fix build for cores w/o cache or zero overhead loop options - fix boot of secondary cores in SMP configuration - add support for DMA to high memory pages - add dma_to_phys and phys_to_dma functions. * tag 'xtensa-20151108' of git://github.com/czankel/xtensa-linux: xtensa: implement dma_to_phys and phys_to_dma xtensa: support DMA to high memory Revert "xtensa: cache inquiry and unaligned cache handling functions" xtensa: drop unused sections and remapped reset handlers xtensa: fix secondary core boot in SMP xtensa: add FORCE_MAX_ZONEORDER to Kconfig xtensa: nommu: provide defconfig for de212 on kc705 xtensa: nommu: xtfpga: add kc705 DTS xtensa: add de212 core variant xtensa: nommu: select HAVE_FUTEX_CMPXCHG xtensa: nommu: fix default memory start address xtensa: nommu: provide correct KIO addresses xtensa: nommu: fix USER_RING definition xtensa: xtfpga: fix integer overflow in TASK_SIZE xtensa: fix build for configs without cache options xtensa: fixes for configs without loop option
Diffstat
-rw-r--r--arch/xtensa/Kconfig17
-rw-r--r--arch/xtensa/boot/boot-elf/boot.lds.S13
-rw-r--r--arch/xtensa/boot/boot-elf/bootstrap.S28
-rw-r--r--arch/xtensa/boot/dts/kc705_nommu.dts17
-rw-r--r--arch/xtensa/configs/nommu_kc705_defconfig131
-rw-r--r--arch/xtensa/include/asm/asmmacro.h7
-rw-r--r--arch/xtensa/include/asm/cacheasm.h26
-rw-r--r--arch/xtensa/include/asm/cacheflush.h106
-rw-r--r--arch/xtensa/include/asm/dma-mapping.h10
-rw-r--r--arch/xtensa/include/asm/initialize_mmu.h13
-rw-r--r--arch/xtensa/include/asm/io.h9
-rw-r--r--arch/xtensa/include/asm/pgtable.h4
-rw-r--r--arch/xtensa/include/asm/vectors.h28
-rw-r--r--arch/xtensa/kernel/Makefile1
-rw-r--r--arch/xtensa/kernel/entry.S8
-rw-r--r--arch/xtensa/kernel/head.S2
-rw-r--r--arch/xtensa/kernel/mxhead.S23
-rw-r--r--arch/xtensa/kernel/pci-dma.c45
-rw-r--r--arch/xtensa/kernel/setup.c11
-rw-r--r--arch/xtensa/kernel/vectors.S4
-rw-r--r--arch/xtensa/kernel/vmlinux.lds.S37
-rw-r--r--arch/xtensa/lib/usercopy.S6
-rw-r--r--arch/xtensa/platforms/iss/setup.c2
-rw-r--r--arch/xtensa/platforms/xt2000/setup.c2
-rw-r--r--arch/xtensa/platforms/xtfpga/include/platform/hardware.h6
-rw-r--r--arch/xtensa/platforms/xtfpga/setup.c2
-rw-r--r--arch/xtensa/variants/de212/include/variant/core.h594
-rw-r--r--arch/xtensa/variants/de212/include/variant/tie-asm.h170
-rw-r--r--arch/xtensa/variants/de212/include/variant/tie.h136
29 files changed, 1210 insertions, 248 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 3bd3504a6cc7..82044f732323 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -17,6 +17,7 @@ config XTENSA
17 select HAVE_DMA_API_DEBUG 17 select HAVE_DMA_API_DEBUG
18 select HAVE_DMA_ATTRS 18 select HAVE_DMA_ATTRS
19 select HAVE_FUNCTION_TRACER 19 select HAVE_FUNCTION_TRACER
20 select HAVE_FUTEX_CMPXCHG if !MMU
20 select HAVE_IRQ_TIME_ACCOUNTING 21 select HAVE_IRQ_TIME_ACCOUNTING
21 select HAVE_OPROFILE 22 select HAVE_OPROFILE
22 select HAVE_PERF_EVENTS 23 select HAVE_PERF_EVENTS
@@ -397,6 +398,20 @@ config SIMDISK1_FILENAME
397 398
398source "mm/Kconfig" 399source "mm/Kconfig"
399 400
401config FORCE_MAX_ZONEORDER
402 int "Maximum zone order"
403 default "11"
404 help
405 The kernel memory allocator divides physically contiguous memory
406 blocks into "zones", where each zone is a power of two number of
407 pages. This option selects the largest power of two that the kernel
408 keeps in the memory allocator. If you need to allocate very large
409 blocks of physically contiguous memory, then you may need to
410 increase this value.
411
412 This config option is actually maximum order plus one. For example,
413 a value of 11 means that the largest free memory block is 2^10 pages.
414
400source "drivers/pcmcia/Kconfig" 415source "drivers/pcmcia/Kconfig"
401 416
402source "drivers/pci/hotplug/Kconfig" 417source "drivers/pci/hotplug/Kconfig"
@@ -408,7 +423,7 @@ config DEFAULT_MEM_START
408 hex "Physical address of the default memory area start" 423 hex "Physical address of the default memory area start"
409 depends on PLATFORM_WANT_DEFAULT_MEM 424 depends on PLATFORM_WANT_DEFAULT_MEM
410 default 0x00000000 if MMU 425 default 0x00000000 if MMU
411 default 0x40000000 if !MMU 426 default 0x60000000 if !MMU
412 help 427 help
413 This is a fallback start address of the default memory area, it is 428 This is a fallback start address of the default memory area, it is
414 used when no physical memory size is passed through DTB or through 429 used when no physical memory size is passed through DTB or through
diff --git a/arch/xtensa/boot/boot-elf/boot.lds.S b/arch/xtensa/boot/boot-elf/boot.lds.S
index 958b33af96b7..e54f2c9df63a 100644
--- a/arch/xtensa/boot/boot-elf/boot.lds.S
+++ b/arch/xtensa/boot/boot-elf/boot.lds.S
@@ -40,17 +40,4 @@ SECTIONS
40 *(.bss) 40 *(.bss)
41 __bss_end = .; 41 __bss_end = .;
42 } 42 }
43
44#ifdef CONFIG_MMU
45 /*
46 * This is a remapped copy of the Reset Vector Code.
47 * It keeps gdb in sync with the PC after switching
48 * to the temporary mapping used while setting up
49 * the V2 MMU mappings for Linux.
50 */
51 .ResetVector.remapped_text 0x46000000 (INFO):
52 {
53 *(.ResetVector.remapped_text)
54 }
55#endif
56} 43}
diff --git a/arch/xtensa/boot/boot-elf/bootstrap.S b/arch/xtensa/boot/boot-elf/bootstrap.S
index 9341a5750694..e6bf313613cf 100644
--- a/arch/xtensa/boot/boot-elf/bootstrap.S
+++ b/arch/xtensa/boot/boot-elf/bootstrap.S
@@ -58,8 +58,6 @@ _SetupMMU:
58 wsr a0, ps 58 wsr a0, ps
59 rsync 59 rsync
60 60
61 Offset = _SetupMMU - _ResetVector
62
63#ifndef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 61#ifndef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
64 initialize_mmu 62 initialize_mmu
65#endif 63#endif
@@ -74,29 +72,3 @@ reset:
74 movi a3, 0 72 movi a3, 0
75 movi a4, 0 73 movi a4, 0
76 jx a0 74 jx a0
77
78#ifdef CONFIG_MMU
79 .align 4
80
81 .section .ResetVector.remapped_text, "x"
82 .global _RemappedResetVector
83
84 /* Do org before literals */
85 .org 0
86
87_RemappedResetVector:
88 .begin no-absolute-literals
89 .literal_position
90
91 _j _RemappedSetupMMU
92
93 /* Position Remapped code at the same location as the original code */
94 . = _RemappedResetVector + Offset
95
96_RemappedSetupMMU:
97#ifndef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
98 initialize_mmu
99#endif
100
101 .end no-absolute-literals
102#endif
diff --git a/arch/xtensa/boot/dts/kc705_nommu.dts b/arch/xtensa/boot/dts/kc705_nommu.dts
new file mode 100644
index 000000000000..65f3d741b964
--- /dev/null
+++ b/arch/xtensa/boot/dts/kc705_nommu.dts
@@ -0,0 +1,17 @@
1/dts-v1/;
2/include/ "xtfpga.dtsi"
3/include/ "xtfpga-flash-128m.dtsi"
4
5/ {
6 compatible = "cdns,xtensa-kc705";
7 chosen {
8 bootargs = "earlycon=uart8250,mmio32,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
9 };
10 memory@0 {
11 device_type = "memory";
12 reg = <0x60000000 0x10000000>;
13 };
14 soc {
15 ranges = <0x00000000 0x90000000 0x10000000>;
16 };
17};
diff --git a/arch/xtensa/configs/nommu_kc705_defconfig b/arch/xtensa/configs/nommu_kc705_defconfig
new file mode 100644
index 000000000000..337d5ba2d285
--- /dev/null
+++ b/arch/xtensa/configs/nommu_kc705_defconfig
@@ -0,0 +1,131 @@
1CONFIG_SYSVIPC=y
2CONFIG_POSIX_MQUEUE=y
3CONFIG_FHANDLE=y
4CONFIG_IRQ_DOMAIN_DEBUG=y
5CONFIG_NO_HZ_IDLE=y
6CONFIG_HIGH_RES_TIMERS=y
7CONFIG_IRQ_TIME_ACCOUNTING=y
8CONFIG_BSD_PROCESS_ACCT=y
9CONFIG_CGROUP_DEBUG=y
10CONFIG_CGROUP_FREEZER=y
11CONFIG_CGROUP_DEVICE=y
12CONFIG_CPUSETS=y
13CONFIG_CGROUP_CPUACCT=y
14CONFIG_MEMCG=y
15CONFIG_NAMESPACES=y
16CONFIG_SCHED_AUTOGROUP=y
17CONFIG_RELAY=y
18CONFIG_BLK_DEV_INITRD=y
19# CONFIG_RD_BZIP2 is not set
20# CONFIG_RD_LZMA is not set
21# CONFIG_RD_XZ is not set
22# CONFIG_RD_LZO is not set
23# CONFIG_RD_LZ4 is not set
24CONFIG_EXPERT=y
25CONFIG_SYSCTL_SYSCALL=y
26CONFIG_KALLSYMS_ALL=y
27CONFIG_PERF_EVENTS=y
28CONFIG_MODULES=y
29CONFIG_MODULE_UNLOAD=y
30# CONFIG_IOSCHED_DEADLINE is not set
31# CONFIG_IOSCHED_CFQ is not set
32CONFIG_XTENSA_VARIANT_CUSTOM=y
33CONFIG_XTENSA_VARIANT_CUSTOM_NAME="de212"
34# CONFIG_XTENSA_VARIANT_MMU is not set
35CONFIG_XTENSA_UNALIGNED_USER=y
36CONFIG_PREEMPT=y
37# CONFIG_PCI is not set
38CONFIG_XTENSA_PLATFORM_XTFPGA=y
39CONFIG_CMDLINE_BOOL=y
40CONFIG_CMDLINE="earlycon=uart8250,mmio32,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"
41CONFIG_USE_OF=y
42CONFIG_BUILTIN_DTB="kc705_nommu"
43CONFIG_DEFAULT_MEM_SIZE=0x10000000
44CONFIG_BINFMT_FLAT=y
45CONFIG_NET=y
46CONFIG_PACKET=y
47CONFIG_UNIX=y
48CONFIG_INET=y
49CONFIG_IP_MULTICAST=y
50CONFIG_IP_PNP=y
51CONFIG_IP_PNP_DHCP=y
52CONFIG_IP_PNP_BOOTP=y
53CONFIG_IP_PNP_RARP=y
54# CONFIG_IPV6 is not set
55CONFIG_NETFILTER=y
56# CONFIG_WIRELESS is not set
57CONFIG_DEVTMPFS=y
58CONFIG_DEVTMPFS_MOUNT=y
59# CONFIG_STANDALONE is not set
60CONFIG_MTD=y
61CONFIG_MTD_CFI=y
62CONFIG_MTD_JEDECPROBE=y
63CONFIG_MTD_CFI_INTELEXT=y
64CONFIG_MTD_CFI_AMDSTD=y
65CONFIG_MTD_CFI_STAA=y
66CONFIG_BLK_DEV_LOOP=y
67CONFIG_BLK_DEV_RAM=y
68CONFIG_SCSI=y
69CONFIG_BLK_DEV_SD=y
70CONFIG_NETDEVICES=y
71# CONFIG_NET_VENDOR_ARC is not set
72# CONFIG_NET_VENDOR_BROADCOM is not set
73# CONFIG_NET_VENDOR_INTEL is not set
74# CONFIG_NET_VENDOR_MARVELL is not set
75# CONFIG_NET_VENDOR_MICREL is not set
76# CONFIG_NET_VENDOR_NATSEMI is not set
77# CONFIG_NET_VENDOR_SEEQ is not set
78# CONFIG_NET_VENDOR_STMICRO is not set
79# CONFIG_NET_VENDOR_VIA is not set
80# CONFIG_NET_VENDOR_WIZNET is not set
81CONFIG_MARVELL_PHY=y
82# CONFIG_WLAN is not set
83# CONFIG_INPUT_MOUSEDEV is not set
84# CONFIG_INPUT_KEYBOARD is not set
85# CONFIG_INPUT_MOUSE is not set
86# CONFIG_SERIO is not set
87CONFIG_SERIAL_8250=y
88# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
89CONFIG_SERIAL_8250_CONSOLE=y
90CONFIG_SERIAL_OF_PLATFORM=y
91CONFIG_HW_RANDOM=y
92# CONFIG_HWMON is not set
93CONFIG_WATCHDOG=y
94CONFIG_WATCHDOG_NOWAYOUT=y
95CONFIG_SOFT_WATCHDOG=y
96# CONFIG_VGA_CONSOLE is not set
97# CONFIG_USB_SUPPORT is not set
98CONFIG_EXT3_FS=y
99CONFIG_EXT4_FS=y
100CONFIG_FANOTIFY=y
101CONFIG_VFAT_FS=y
102CONFIG_JFFS2_FS=y
103CONFIG_NFS_FS=y
104CONFIG_NFS_V4=y
105CONFIG_NFS_SWAP=y
106CONFIG_ROOT_NFS=y
107CONFIG_SUNRPC_DEBUG=y
108CONFIG_NLS_CODEPAGE_437=y
109CONFIG_NLS_ISO8859_1=y
110CONFIG_PRINTK_TIME=y
111CONFIG_DYNAMIC_DEBUG=y
112CONFIG_DEBUG_INFO=y
113# CONFIG_FRAME_POINTER is not set
114CONFIG_MAGIC_SYSRQ=y
115CONFIG_DEBUG_VM=y
116CONFIG_DEBUG_NOMMU_REGIONS=y
117CONFIG_DEBUG_SHIRQ=y
118CONFIG_LOCKUP_DETECTOR=y
119CONFIG_SCHEDSTATS=y
120CONFIG_TIMER_STATS=y
121CONFIG_DEBUG_RT_MUTEXES=y
122CONFIG_DEBUG_SPINLOCK=y
123CONFIG_DEBUG_MUTEXES=y
124CONFIG_DEBUG_ATOMIC_SLEEP=y
125CONFIG_STACKTRACE=y
126# CONFIG_RCU_CPU_STALL_INFO is not set
127CONFIG_RCU_TRACE=y
128# CONFIG_FTRACE is not set
129# CONFIG_LD_NO_RELAX is not set
130# CONFIG_CRYPTO_ECHAINIV is not set
131CONFIG_CRYPTO_ANSI_CPRNG=y
diff --git a/arch/xtensa/include/asm/asmmacro.h b/arch/xtensa/include/asm/asmmacro.h
index 755320f6e0bc..746dcc8b5abc 100644
--- a/arch/xtensa/include/asm/asmmacro.h
+++ b/arch/xtensa/include/asm/asmmacro.h
@@ -35,9 +35,10 @@
35 * __loop as 35 * __loop as
36 * restart loop. 'as' register must not have been modified! 36 * restart loop. 'as' register must not have been modified!
37 * 37 *
38 * __endla ar, at, incr 38 * __endla ar, as, incr
39 * ar start address (modified) 39 * ar start address (modified)
40 * as scratch register used by macro 40 * as scratch register used by __loops/__loopi macros or
41 * end address used by __loopt macro
41 * inc increment 42 * inc increment
42 */ 43 */
43 44
@@ -97,7 +98,7 @@
97 .endm 98 .endm
98 99
99/* 100/*
100 * loop from ar to ax 101 * loop from ar to as
101 */ 102 */
102 103
103 .macro __loopt ar, as, at, incr_log2 104 .macro __loopt ar, as, at, incr_log2
diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h
index 60e18773ecb8..e0f9e1109c83 100644
--- a/arch/xtensa/include/asm/cacheasm.h
+++ b/arch/xtensa/include/asm/cacheasm.h
@@ -73,7 +73,9 @@
73 73
74 .macro ___unlock_dcache_all ar at 74 .macro ___unlock_dcache_all ar at
75 75
76#if XCHAL_DCACHE_SIZE
76 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 77 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
78#endif
77 79
78 .endm 80 .endm
79 81
@@ -90,30 +92,38 @@
90 92
91 .macro ___flush_invalidate_dcache_all ar at 93 .macro ___flush_invalidate_dcache_all ar at
92 94
95#if XCHAL_DCACHE_SIZE
93 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 96 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
97#endif
94 98
95 .endm 99 .endm
96 100
97 101
98 .macro ___flush_dcache_all ar at 102 .macro ___flush_dcache_all ar at
99 103
104#if XCHAL_DCACHE_SIZE
100 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 105 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
106#endif
101 107
102 .endm 108 .endm
103 109
104 110
105 .macro ___invalidate_dcache_all ar at 111 .macro ___invalidate_dcache_all ar at
106 112
113#if XCHAL_DCACHE_SIZE
107 __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ 114 __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
108 XCHAL_DCACHE_LINEWIDTH 115 XCHAL_DCACHE_LINEWIDTH
116#endif
109 117
110 .endm 118 .endm
111 119
112 120
113 .macro ___invalidate_icache_all ar at 121 .macro ___invalidate_icache_all ar at
114 122
123#if XCHAL_ICACHE_SIZE
115 __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ 124 __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
116 XCHAL_ICACHE_LINEWIDTH 125 XCHAL_ICACHE_LINEWIDTH
126#endif
117 127
118 .endm 128 .endm
119 129
@@ -121,28 +131,36 @@
121 131
122 .macro ___flush_invalidate_dcache_range ar as at 132 .macro ___flush_invalidate_dcache_range ar as at
123 133
134#if XCHAL_DCACHE_SIZE
124 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH 135 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
136#endif
125 137
126 .endm 138 .endm
127 139
128 140
129 .macro ___flush_dcache_range ar as at 141 .macro ___flush_dcache_range ar as at
130 142
143#if XCHAL_DCACHE_SIZE
131 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH 144 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
145#endif
132 146
133 .endm 147 .endm
134 148
135 149
136 .macro ___invalidate_dcache_range ar as at 150 .macro ___invalidate_dcache_range ar as at
137 151
152#if XCHAL_DCACHE_SIZE
138 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH 153 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
154#endif
139 155
140 .endm 156 .endm
141 157
142 158
143 .macro ___invalidate_icache_range ar as at 159 .macro ___invalidate_icache_range ar as at
144 160
161#if XCHAL_ICACHE_SIZE
145 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH 162 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
163#endif
146 164
147 .endm 165 .endm
148 166
@@ -150,27 +168,35 @@
150 168
151 .macro ___flush_invalidate_dcache_page ar as 169 .macro ___flush_invalidate_dcache_page ar as
152 170
171#if XCHAL_DCACHE_SIZE
153 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 172 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
173#endif
154 174
155 .endm 175 .endm
156 176
157 177
158 .macro ___flush_dcache_page ar as 178 .macro ___flush_dcache_page ar as
159 179
180#if XCHAL_DCACHE_SIZE
160 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 181 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
182#endif
161 183
162 .endm 184 .endm
163 185
164 186
165 .macro ___invalidate_dcache_page ar as 187 .macro ___invalidate_dcache_page ar as
166 188
189#if XCHAL_DCACHE_SIZE
167 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 190 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
191#endif
168 192
169 .endm 193 .endm
170 194
171 195
172 .macro ___invalidate_icache_page ar as 196 .macro ___invalidate_icache_page ar as
173 197
198#if XCHAL_ICACHE_SIZE
174 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 199 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
200#endif
175 201
176 .endm 202 .endm
diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index 5f67ace97b32..397d6a1a4224 100644
--- a/arch/xtensa/include/asm/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
@@ -55,9 +55,14 @@ extern void __flush_dcache_range(unsigned long, unsigned long);
55extern void __flush_invalidate_dcache_page(unsigned long); 55extern void __flush_invalidate_dcache_page(unsigned long);
56extern void __flush_invalidate_dcache_range(unsigned long, unsigned long); 56extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
57#else 57#else
58# define __flush_dcache_range(p,s) do { } while(0) 58static inline void __flush_dcache_page(unsigned long va)
59# define __flush_dcache_page(p) do { } while(0) 59{
60# define __flush_invalidate_dcache_page(p) __invalidate_dcache_page(p) 60}
61static inline void __flush_dcache_range(unsigned long va, unsigned long sz)
62{
63}
64# define __flush_invalidate_dcache_all() __invalidate_dcache_all()
65# define __flush_invalidate_dcache_page(p) __invalidate_dcache_page(p)
61# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s) 66# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s)
62#endif 67#endif
63 68
@@ -174,99 +179,4 @@ extern void copy_from_user_page(struct vm_area_struct*, struct page*,
174 179
175#endif 180#endif
176 181
177#define XTENSA_CACHEBLK_LOG2 29
178#define XTENSA_CACHEBLK_SIZE (1 << XTENSA_CACHEBLK_LOG2)
179#define XTENSA_CACHEBLK_MASK (7 << XTENSA_CACHEBLK_LOG2)
180
181#if XCHAL_HAVE_CACHEATTR
182static inline u32 xtensa_get_cacheattr(void)
183{
184 u32 r;
185 asm volatile(" rsr %0, cacheattr" : "=a"(r));
186 return r;
187}
188
189static inline u32 xtensa_get_dtlb1(u32 addr)
190{
191 u32 r = addr & XTENSA_CACHEBLK_MASK;
192 return r | ((xtensa_get_cacheattr() >> (r >> (XTENSA_CACHEBLK_LOG2-2)))
193 & 0xF);
194}
195#else
196static inline u32 xtensa_get_dtlb1(u32 addr)
197{
198 u32 r;
199 asm volatile(" rdtlb1 %0, %1" : "=a"(r) : "a"(addr));
200 asm volatile(" dsync");
201 return r;
202}
203
204static inline u32 xtensa_get_cacheattr(void)
205{
206 u32 r = 0;
207 u32 a = 0;
208 do {
209 a -= XTENSA_CACHEBLK_SIZE;
210 r = (r << 4) | (xtensa_get_dtlb1(a) & 0xF);
211 } while (a);
212 return r;
213}
214#endif
215
216static inline int xtensa_need_flush_dma_source(u32 addr)
217{
218 return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) >= 4;
219}
220
221static inline int xtensa_need_invalidate_dma_destination(u32 addr)
222{
223 return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) != 2;
224}
225
226static inline void flush_dcache_unaligned(u32 addr, u32 size)
227{
228 u32 cnt;
229 if (size) {
230 cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
231 + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
232 while (cnt--) {
233 asm volatile(" dhwb %0, 0" : : "a"(addr));
234 addr += XCHAL_DCACHE_LINESIZE;
235 }
236 asm volatile(" dsync");
237 }
238}
239
240static inline void invalidate_dcache_unaligned(u32 addr, u32 size)
241{
242 int cnt;
243 if (size) {
244 asm volatile(" dhwbi %0, 0 ;" : : "a"(addr));
245 cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
246 - XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
247 while (cnt-- > 0) {
248 asm volatile(" dhi %0, %1" : : "a"(addr),
249 "n"(XCHAL_DCACHE_LINESIZE));
250 addr += XCHAL_DCACHE_LINESIZE;
251 }
252 asm volatile(" dhwbi %0, %1" : : "a"(addr),
253 "n"(XCHAL_DCACHE_LINESIZE));
254 asm volatile(" dsync");
255 }
256}
257
258static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size)
259{
260 u32 cnt;
261 if (size) {
262 cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
263 + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
264 while (cnt--) {
265 asm volatile(" dhwbi %0, 0" : : "a"(addr));
266 addr += XCHAL_DCACHE_LINESIZE;
267 }
268 asm volatile(" dsync");
269 }
270}
271
272#endif /* _XTENSA_CACHEFLUSH_H */ 182#endif /* _XTENSA_CACHEFLUSH_H */
diff --git a/arch/xtensa/include/asm/dma-mapping.h b/arch/xtensa/include/asm/dma-mapping.h
index 4427f38b634e..66c9ba261e30 100644
--- a/arch/xtensa/include/asm/dma-mapping.h
+++ b/arch/xtensa/include/asm/dma-mapping.h
@@ -35,4 +35,14 @@ static inline struct dma_map_ops *get_dma_ops(struct device *dev)
35void dma_cache_sync(struct device *dev, void *vaddr, size_t size, 35void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
36 enum dma_data_direction direction); 36 enum dma_data_direction direction);
37 37
38static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
39{
40 return (dma_addr_t)paddr;
41}
42
43static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
44{
45 return (phys_addr_t)daddr;
46}
47
38#endif /* _XTENSA_DMA_MAPPING_H */ 48#endif /* _XTENSA_DMA_MAPPING_H */
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h
index e256f2270ec9..7a1e075969a3 100644
--- a/arch/xtensa/include/asm/initialize_mmu.h
+++ b/arch/xtensa/include/asm/initialize_mmu.h
@@ -161,7 +161,8 @@
161#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && 161#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
162 XCHAL_HAVE_SPANNING_WAY */ 162 XCHAL_HAVE_SPANNING_WAY */
163 163
164#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS 164#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \
165 (XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE)
165 /* Enable data and instruction cache in the DEFAULT_MEMORY region 166 /* Enable data and instruction cache in the DEFAULT_MEMORY region
166 * if the processor has DTLB and ITLB. 167 * if the processor has DTLB and ITLB.
167 */ 168 */
@@ -175,14 +176,18 @@
1751: 1761:
176 sub a9, a9, a8 177 sub a9, a9, a8
1772: 1782:
179#if XCHAL_DCACHE_SIZE
178 rdtlb1 a3, a5 180 rdtlb1 a3, a5
179 ritlb1 a4, a5
180 and a3, a3, a6 181 and a3, a3, a6
181 and a4, a4, a6
182 or a3, a3, a7 182 or a3, a3, a7
183 or a4, a4, a7
184 wdtlb a3, a5 183 wdtlb a3, a5
184#endif
185#if XCHAL_ICACHE_SIZE
186 ritlb1 a4, a5
187 and a4, a4, a6
188 or a4, a4, a7
185 witlb a4, a5 189 witlb a4, a5
190#endif
186 add a5, a5, a8 191 add a5, a5, a8
187 bltu a8, a9, 1b 192 bltu a8, a9, 1b
188 193
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 867840f5400f..74fed0b4e2c2 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -25,15 +25,6 @@
25 25
26#ifdef CONFIG_MMU 26#ifdef CONFIG_MMU
27 27
28#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
29extern unsigned long xtensa_kio_paddr;
30
31static inline unsigned long xtensa_get_kio_paddr(void)
32{
33 return xtensa_kio_paddr;
34}
35#endif
36
37/* 28/*
38 * Return the virtual address for the specified bus memory. 29 * Return the virtual address for the specified bus memory.
39 * Note that we currently don't support any address outside the KIO segment. 30 * Note that we currently don't support any address outside the KIO segment.
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h
index a5e929a10c20..fb02fdc5ecee 100644
--- a/arch/xtensa/include/asm/pgtable.h
+++ b/arch/xtensa/include/asm/pgtable.h
@@ -18,7 +18,11 @@
18 * We only use two ring levels, user and kernel space. 18 * We only use two ring levels, user and kernel space.
19 */ 19 */
20 20
21#ifdef CONFIG_MMU
21#define USER_RING 1 /* user ring level */ 22#define USER_RING 1 /* user ring level */
23#else
24#define USER_RING 0
25#endif
22#define KERNEL_RING 0 /* kernel ring level */ 26#define KERNEL_RING 0 /* kernel ring level */
23 27
24/* 28/*
diff --git a/arch/xtensa/include/asm/vectors.h b/arch/xtensa/include/asm/vectors.h
index a46c53f36113..288c776736d3 100644
--- a/arch/xtensa/include/asm/vectors.h
+++ b/arch/xtensa/include/asm/vectors.h
@@ -21,13 +21,26 @@
21#include <variant/core.h> 21#include <variant/core.h>
22#include <platform/hardware.h> 22#include <platform/hardware.h>
23 23
24#if XCHAL_HAVE_PTP_MMU
24#define XCHAL_KIO_CACHED_VADDR 0xe0000000 25#define XCHAL_KIO_CACHED_VADDR 0xe0000000
25#define XCHAL_KIO_BYPASS_VADDR 0xf0000000 26#define XCHAL_KIO_BYPASS_VADDR 0xf0000000
26#define XCHAL_KIO_DEFAULT_PADDR 0xf0000000 27#define XCHAL_KIO_DEFAULT_PADDR 0xf0000000
28#else
29#define XCHAL_KIO_BYPASS_VADDR XCHAL_KIO_PADDR
30#define XCHAL_KIO_DEFAULT_PADDR 0x90000000
31#endif
27#define XCHAL_KIO_SIZE 0x10000000 32#define XCHAL_KIO_SIZE 0x10000000
28 33
29#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF) 34#if (!XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY) && defined(CONFIG_OF)
30#define XCHAL_KIO_PADDR xtensa_get_kio_paddr() 35#define XCHAL_KIO_PADDR xtensa_get_kio_paddr()
36#ifndef __ASSEMBLY__
37extern unsigned long xtensa_kio_paddr;
38
39static inline unsigned long xtensa_get_kio_paddr(void)
40{
41 return xtensa_kio_paddr;
42}
43#endif
31#else 44#else
32#define XCHAL_KIO_PADDR XCHAL_KIO_DEFAULT_PADDR 45#define XCHAL_KIO_PADDR XCHAL_KIO_DEFAULT_PADDR
33#endif 46#endif
@@ -48,6 +61,9 @@
48 #define LOAD_MEMORY_ADDRESS 0xD0003000 61 #define LOAD_MEMORY_ADDRESS 0xD0003000
49#endif 62#endif
50 63
64#define RESET_VECTOR1_VADDR (VIRTUAL_MEMORY_ADDRESS + \
65 XCHAL_RESET_VECTOR1_PADDR)
66
51#else /* !defined(CONFIG_MMU) */ 67#else /* !defined(CONFIG_MMU) */
52 /* MMU Not being used - Virtual == Physical */ 68 /* MMU Not being used - Virtual == Physical */
53 69
@@ -60,6 +76,8 @@
60 /* Loaded just above possibly live vectors */ 76 /* Loaded just above possibly live vectors */
61 #define LOAD_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x3000) 77 #define LOAD_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x3000)
62 78
79#define RESET_VECTOR1_VADDR (XCHAL_RESET_VECTOR1_VADDR)
80
63#endif /* CONFIG_MMU */ 81#endif /* CONFIG_MMU */
64 82
65#define XC_VADDR(offset) (VIRTUAL_MEMORY_ADDRESS + offset) 83#define XC_VADDR(offset) (VIRTUAL_MEMORY_ADDRESS + offset)
@@ -67,14 +85,6 @@
67/* Used to set VECBASE register */ 85/* Used to set VECBASE register */
68#define VECBASE_RESET_VADDR VIRTUAL_MEMORY_ADDRESS 86#define VECBASE_RESET_VADDR VIRTUAL_MEMORY_ADDRESS
69 87
70#define RESET_VECTOR_VECOFS (XCHAL_RESET_VECTOR_VADDR - \
71 VECBASE_RESET_VADDR)
72#define RESET_VECTOR_VADDR XC_VADDR(RESET_VECTOR_VECOFS)
73
74#define RESET_VECTOR1_VECOFS (XCHAL_RESET_VECTOR1_VADDR - \
75 VECBASE_RESET_VADDR)
76#define RESET_VECTOR1_VADDR XC_VADDR(RESET_VECTOR1_VECOFS)
77
78#if defined(XCHAL_HAVE_VECBASE) && XCHAL_HAVE_VECBASE 88#if defined(XCHAL_HAVE_VECBASE) && XCHAL_HAVE_VECBASE
79 89
80#define USER_VECTOR_VADDR XC_VADDR(XCHAL_USER_VECOFS) 90#define USER_VECTOR_VADDR XC_VADDR(XCHAL_USER_VECOFS)
diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile
index 50137bc9e150..4db730290d2d 100644
--- a/arch/xtensa/kernel/Makefile
+++ b/arch/xtensa/kernel/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SMP) += smp.o mxhead.o
16obj-$(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) += perf_event.o 16obj-$(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) += perf_event.o
17 17
18AFLAGS_head.o += -mtext-section-literals 18AFLAGS_head.o += -mtext-section-literals
19AFLAGS_mxhead.o += -mtext-section-literals
19 20
20# In the Xtensa architecture, assembly generates literals which must always 21# In the Xtensa architecture, assembly generates literals which must always
21# precede the L32R instruction with a relative offset less than 256 kB. 22# precede the L32R instruction with a relative offset less than 256 kB.
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index 504130357597..db5c1765b413 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -367,8 +367,10 @@ common_exception:
367 s32i a2, a1, PT_SYSCALL 367 s32i a2, a1, PT_SYSCALL
368 movi a2, 0 368 movi a2, 0
369 s32i a3, a1, PT_EXCVADDR 369 s32i a3, a1, PT_EXCVADDR
370#if XCHAL_HAVE_LOOPS
370 xsr a2, lcount 371 xsr a2, lcount
371 s32i a2, a1, PT_LCOUNT 372 s32i a2, a1, PT_LCOUNT
373#endif
372 374
373 /* It is now save to restore the EXC_TABLE_FIXUP variable. */ 375 /* It is now save to restore the EXC_TABLE_FIXUP variable. */
374 376
@@ -429,11 +431,12 @@ common_exception:
429 rsync # PS.WOE => rsync => overflow 431 rsync # PS.WOE => rsync => overflow
430 432
431 /* Save lbeg, lend */ 433 /* Save lbeg, lend */
432 434#if XCHAL_HAVE_LOOPS
433 rsr a4, lbeg 435 rsr a4, lbeg
434 rsr a3, lend 436 rsr a3, lend
435 s32i a4, a1, PT_LBEG 437 s32i a4, a1, PT_LBEG
436 s32i a3, a1, PT_LEND 438 s32i a3, a1, PT_LEND
439#endif
437 440
438 /* Save SCOMPARE1 */ 441 /* Save SCOMPARE1 */
439 442
@@ -724,13 +727,14 @@ common_exception_exit:
724 wsr a3, sar 727 wsr a3, sar
725 728
726 /* Restore LBEG, LEND, LCOUNT */ 729 /* Restore LBEG, LEND, LCOUNT */
727 730#if XCHAL_HAVE_LOOPS
728 l32i a2, a1, PT_LBEG 731 l32i a2, a1, PT_LBEG
729 l32i a3, a1, PT_LEND 732 l32i a3, a1, PT_LEND
730 wsr a2, lbeg 733 wsr a2, lbeg
731 l32i a2, a1, PT_LCOUNT 734 l32i a2, a1, PT_LCOUNT
732 wsr a3, lend 735 wsr a3, lend
733 wsr a2, lcount 736 wsr a2, lcount
737#endif
734 738
735 /* We control single stepping through the ICOUNTLEVEL register. */ 739 /* We control single stepping through the ICOUNTLEVEL register. */
736 740
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index 15a461e2a0ed..9ed55649ac8e 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -249,7 +249,7 @@ ENTRY(_startup)
249 249
250 __loopt a2, a3, a4, 2 250 __loopt a2, a3, a4, 2
251 s32i a0, a2, 0 251 s32i a0, a2, 0
252 __endla a2, a4, 4 252 __endla a2, a3, 4
253 253
254#if XCHAL_DCACHE_IS_WRITEBACK 254#if XCHAL_DCACHE_IS_WRITEBACK
255 255
diff --git a/arch/xtensa/kernel/mxhead.S b/arch/xtensa/kernel/mxhead.S
index 77a161a112c5..9f3843742726 100644
--- a/arch/xtensa/kernel/mxhead.S
+++ b/arch/xtensa/kernel/mxhead.S
@@ -48,8 +48,6 @@ _SetupOCD:
48 rsync 48 rsync
49 49
50_SetupMMU: 50_SetupMMU:
51 Offset = _SetupMMU - _SecondaryResetVector
52
53#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 51#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
54 initialize_mmu 52 initialize_mmu
55#endif 53#endif
@@ -62,24 +60,3 @@ _SetupMMU:
62 jx a3 60 jx a3
63 61
64 .end no-absolute-literals 62 .end no-absolute-literals
65
66
67 .section .SecondaryResetVector.remapped_text, "ax"
68 .global _RemappedSecondaryResetVector
69
70 .org 0 # Need to do org before literals
71
72_RemappedSecondaryResetVector:
73 .begin no-absolute-literals
74 .literal_position
75
76 _j _RemappedSetupMMU
77 . = _RemappedSecondaryResetVector + Offset
78
79_RemappedSetupMMU:
80
81#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
82 initialize_mmu
83#endif
84
85 .end no-absolute-literals
diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c
index fb75ebf1463a..cd66698348ca 100644
--- a/arch/xtensa/kernel/pci-dma.c
+++ b/arch/xtensa/kernel/pci-dma.c
@@ -15,14 +15,15 @@
15 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> 15 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
16 */ 16 */
17 17
18#include <linux/types.h>
19#include <linux/mm.h>
20#include <linux/string.h>
21#include <linux/pci.h>
22#include <linux/gfp.h> 18#include <linux/gfp.h>
19#include <linux/highmem.h>
20#include <linux/mm.h>
23#include <linux/module.h> 21#include <linux/module.h>
24#include <asm/io.h> 22#include <linux/pci.h>
23#include <linux/string.h>
24#include <linux/types.h>
25#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
26#include <asm/io.h>
26 27
27void dma_cache_sync(struct device *dev, void *vaddr, size_t size, 28void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
28 enum dma_data_direction dir) 29 enum dma_data_direction dir)
@@ -47,17 +48,36 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
47} 48}
48EXPORT_SYMBOL(dma_cache_sync); 49EXPORT_SYMBOL(dma_cache_sync);
49 50
51static void do_cache_op(dma_addr_t dma_handle, size_t size,
52 void (*fn)(unsigned long, unsigned long))
53{
54 unsigned long off = dma_handle & (PAGE_SIZE - 1);
55 unsigned long pfn = PFN_DOWN(dma_handle);
56 struct page *page = pfn_to_page(pfn);
57
58 if (!PageHighMem(page))
59 fn((unsigned long)bus_to_virt(dma_handle), size);
60 else
61 while (size > 0) {
62 size_t sz = min_t(size_t, size, PAGE_SIZE - off);
63 void *vaddr = kmap_atomic(page);
64
65 fn((unsigned long)vaddr + off, sz);
66 kunmap_atomic(vaddr);
67 off = 0;
68 ++page;
69 size -= sz;
70 }
71}
72
50static void xtensa_sync_single_for_cpu(struct device *dev, 73static void xtensa_sync_single_for_cpu(struct device *dev,
51 dma_addr_t dma_handle, size_t size, 74 dma_addr_t dma_handle, size_t size,
52 enum dma_data_direction dir) 75 enum dma_data_direction dir)
53{ 76{
54 void *vaddr;
55
56 switch (dir) { 77 switch (dir) {
57 case DMA_BIDIRECTIONAL: 78 case DMA_BIDIRECTIONAL:
58 case DMA_FROM_DEVICE: 79 case DMA_FROM_DEVICE:
59 vaddr = bus_to_virt(dma_handle); 80 do_cache_op(dma_handle, size, __invalidate_dcache_range);
60 __invalidate_dcache_range((unsigned long)vaddr, size);
61 break; 81 break;
62 82
63 case DMA_NONE: 83 case DMA_NONE:
@@ -73,13 +93,11 @@ static void xtensa_sync_single_for_device(struct device *dev,
73 dma_addr_t dma_handle, size_t size, 93 dma_addr_t dma_handle, size_t size,
74 enum dma_data_direction dir) 94 enum dma_data_direction dir)
75{ 95{
76 void *vaddr;
77
78 switch (dir) { 96 switch (dir) {
79 case DMA_BIDIRECTIONAL: 97 case DMA_BIDIRECTIONAL:
80 case DMA_TO_DEVICE: 98 case DMA_TO_DEVICE:
81 vaddr = bus_to_virt(dma_handle); 99 if (XCHAL_DCACHE_IS_WRITEBACK)
82 __flush_dcache_range((unsigned long)vaddr, size); 100 do_cache_op(dma_handle, size, __flush_dcache_range);
83 break; 101 break;
84 102
85 case DMA_NONE: 103 case DMA_NONE:
@@ -171,7 +189,6 @@ static dma_addr_t xtensa_map_page(struct device *dev, struct page *page,
171{ 189{
172 dma_addr_t dma_handle = page_to_phys(page) + offset; 190 dma_addr_t dma_handle = page_to_phys(page) + offset;
173 191
174 BUG_ON(PageHighMem(page));
175 xtensa_sync_single_for_device(dev, dma_handle, size, dir); 192 xtensa_sync_single_for_device(dev, dma_handle, size, dir);
176 return dma_handle; 193 return dma_handle;
177} 194}
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 28fc57ef5b86..9735691f37f1 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -190,7 +190,7 @@ static int __init parse_bootparam(const bp_tag_t* tag)
190#ifdef CONFIG_OF 190#ifdef CONFIG_OF
191bool __initdata dt_memory_scan = false; 191bool __initdata dt_memory_scan = false;
192 192
193#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY 193#if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
194unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR; 194unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
195EXPORT_SYMBOL(xtensa_kio_paddr); 195EXPORT_SYMBOL(xtensa_kio_paddr);
196 196
@@ -334,7 +334,10 @@ extern char _Level5InterruptVector_text_end;
334extern char _Level6InterruptVector_text_start; 334extern char _Level6InterruptVector_text_start;
335extern char _Level6InterruptVector_text_end; 335extern char _Level6InterruptVector_text_end;
336#endif 336#endif
337 337#ifdef CONFIG_SMP
338extern char _SecondaryResetVector_text_start;
339extern char _SecondaryResetVector_text_end;
340#endif
338 341
339 342
340#ifdef CONFIG_S32C1I_SELFTEST 343#ifdef CONFIG_S32C1I_SELFTEST
@@ -506,6 +509,10 @@ void __init setup_arch(char **cmdline_p)
506 __pa(&_Level6InterruptVector_text_end), 0); 509 __pa(&_Level6InterruptVector_text_end), 0);
507#endif 510#endif
508 511
512#ifdef CONFIG_SMP
513 mem_reserve(__pa(&_SecondaryResetVector_text_start),
514 __pa(&_SecondaryResetVector_text_end), 0);
515#endif
509 parse_early_param(); 516 parse_early_param();
510 bootmem_init(); 517 bootmem_init();
511 518
diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S
index abcdb527f18a..fc25318e75ad 100644
--- a/arch/xtensa/kernel/vectors.S
+++ b/arch/xtensa/kernel/vectors.S
@@ -478,6 +478,9 @@ _DoubleExceptionVector_handle_exception:
478 478
479ENDPROC(_DoubleExceptionVector) 479ENDPROC(_DoubleExceptionVector)
480 480
481 .end literal_prefix
482
483 .text
481/* 484/*
482 * Fixup handler for TLB miss in double exception handler for window owerflow. 485 * Fixup handler for TLB miss in double exception handler for window owerflow.
483 * We get here with windowbase set to the window that was being spilled and 486 * We get here with windowbase set to the window that was being spilled and
@@ -587,7 +590,6 @@ ENTRY(window_overflow_restore_a0_fixup)
587 590
588ENDPROC(window_overflow_restore_a0_fixup) 591ENDPROC(window_overflow_restore_a0_fixup)
589 592
590 .end literal_prefix
591/* 593/*
592 * Debug interrupt vector 594 * Debug interrupt vector
593 * 595 *
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index fc1bc2ba8d5d..c417cbe4ec87 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -166,8 +166,6 @@ SECTIONS
166 RELOCATE_ENTRY(_DebugInterruptVector_text, 166 RELOCATE_ENTRY(_DebugInterruptVector_text,
167 .DebugInterruptVector.text); 167 .DebugInterruptVector.text);
168#if defined(CONFIG_SMP) 168#if defined(CONFIG_SMP)
169 RELOCATE_ENTRY(_SecondaryResetVector_literal,
170 .SecondaryResetVector.literal);
171 RELOCATE_ENTRY(_SecondaryResetVector_text, 169 RELOCATE_ENTRY(_SecondaryResetVector_text,
172 .SecondaryResetVector.text); 170 .SecondaryResetVector.text);
173#endif 171#endif
@@ -282,17 +280,11 @@ SECTIONS
282 280
283#if defined(CONFIG_SMP) 281#if defined(CONFIG_SMP)
284 282
285 SECTION_VECTOR (_SecondaryResetVector_literal,
286 .SecondaryResetVector.literal,
287 RESET_VECTOR1_VADDR - 4,
288 SIZEOF(.DoubleExceptionVector.text),
289 .DoubleExceptionVector.text)
290
291 SECTION_VECTOR (_SecondaryResetVector_text, 283 SECTION_VECTOR (_SecondaryResetVector_text,
292 .SecondaryResetVector.text, 284 .SecondaryResetVector.text,
293 RESET_VECTOR1_VADDR, 285 RESET_VECTOR1_VADDR,
294 4, 286 SIZEOF(.DoubleExceptionVector.text),
295 .SecondaryResetVector.literal) 287 .DoubleExceptionVector.text)
296 288
297 . = LOADADDR(.SecondaryResetVector.text)+SIZEOF(.SecondaryResetVector.text); 289 . = LOADADDR(.SecondaryResetVector.text)+SIZEOF(.SecondaryResetVector.text);
298 290
@@ -306,31 +298,6 @@ SECTIONS
306 298
307 _end = .; 299 _end = .;
308 300
309 /* only used by the boot loader */
310
311 . = ALIGN(0x10);
312 .bootstrap : { *(.bootstrap.literal .bootstrap.text .bootstrap.data) }
313
314 .ResetVector.text RESET_VECTOR_VADDR :
315 {
316 *(.ResetVector.text)
317 }
318
319
320 /*
321 * This is a remapped copy of the Secondary Reset Vector Code.
322 * It keeps gdb in sync with the PC after switching
323 * to the temporary mapping used while setting up
324 * the V2 MMU mappings for Linux.
325 *
326 * Only debug information about this section is put in the kernel image.
327 */
328 .SecondaryResetVector.remapped_text 0x46000000 (INFO):
329 {
330 *(.SecondaryResetVector.remapped_text)
331 }
332
333
334 .xt.lit : { *(.xt.lit) } 301 .xt.lit : { *(.xt.lit) }
335 .xt.prop : { *(.xt.prop) } 302 .xt.prop : { *(.xt.prop) }
336 303
diff --git a/arch/xtensa/lib/usercopy.S b/arch/xtensa/lib/usercopy.S
index ace1892a875e..7ea4dd68893e 100644
--- a/arch/xtensa/lib/usercopy.S
+++ b/arch/xtensa/lib/usercopy.S
@@ -222,8 +222,8 @@ __xtensa_copy_user:
222 loopnez a7, .Loop2done 222 loopnez a7, .Loop2done
223#else /* !XCHAL_HAVE_LOOPS */ 223#else /* !XCHAL_HAVE_LOOPS */
224 beqz a7, .Loop2done 224 beqz a7, .Loop2done
225 slli a10, a7, 4 225 slli a12, a7, 4
226 add a10, a10, a3 # a10 = end of last 16B source chunk 226 add a12, a12, a3 # a12 = end of last 16B source chunk
227#endif /* !XCHAL_HAVE_LOOPS */ 227#endif /* !XCHAL_HAVE_LOOPS */
228.Loop2: 228.Loop2:
229 EX(l32i, a7, a3, 4, l_fixup) 229 EX(l32i, a7, a3, 4, l_fixup)
@@ -241,7 +241,7 @@ __xtensa_copy_user:
241 EX(s32i, a9, a5, 12, s_fixup) 241 EX(s32i, a9, a5, 12, s_fixup)
242 addi a5, a5, 16 242 addi a5, a5, 16
243#if !XCHAL_HAVE_LOOPS 243#if !XCHAL_HAVE_LOOPS
244 blt a3, a10, .Loop2 244 blt a3, a12, .Loop2
245#endif /* !XCHAL_HAVE_LOOPS */ 245#endif /* !XCHAL_HAVE_LOOPS */
246.Loop2done: 246.Loop2done:
247 bbci.l a4, 3, .L12 247 bbci.l a4, 3, .L12
diff --git a/arch/xtensa/platforms/iss/setup.c b/arch/xtensa/platforms/iss/setup.c
index da7d18240866..391820539f0a 100644
--- a/arch/xtensa/platforms/iss/setup.c
+++ b/arch/xtensa/platforms/iss/setup.c
@@ -61,7 +61,9 @@ void platform_restart(void)
61#if XCHAL_NUM_IBREAK > 0 61#if XCHAL_NUM_IBREAK > 0
62 "wsr a2, ibreakenable\n\t" 62 "wsr a2, ibreakenable\n\t"
63#endif 63#endif
64#if XCHAL_HAVE_LOOPS
64 "wsr a2, lcount\n\t" 65 "wsr a2, lcount\n\t"
66#endif
65 "movi a2, 0x1f\n\t" 67 "movi a2, 0x1f\n\t"
66 "wsr a2, ps\n\t" 68 "wsr a2, ps\n\t"
67 "isync\n\t" 69 "isync\n\t"
diff --git a/arch/xtensa/platforms/xt2000/setup.c b/arch/xtensa/platforms/xt2000/setup.c
index b90555cb8089..87678961a8c8 100644
--- a/arch/xtensa/platforms/xt2000/setup.c
+++ b/arch/xtensa/platforms/xt2000/setup.c
@@ -72,7 +72,9 @@ void platform_restart(void)
72#if XCHAL_NUM_IBREAK > 0 72#if XCHAL_NUM_IBREAK > 0
73 "wsr a2, ibreakenable\n\t" 73 "wsr a2, ibreakenable\n\t"
74#endif 74#endif
75#if XCHAL_HAVE_LOOPS
75 "wsr a2, lcount\n\t" 76 "wsr a2, lcount\n\t"
77#endif
76 "movi a2, 0x1f\n\t" 78 "movi a2, 0x1f\n\t"
77 "wsr a2, ps\n\t" 79 "wsr a2, ps\n\t"
78 "isync\n\t" 80 "isync\n\t"
diff --git a/arch/xtensa/platforms/xtfpga/include/platform/hardware.h b/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
index 0a55bb9c5420..dbeea2b440a1 100644
--- a/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
+++ b/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
@@ -12,13 +12,15 @@
12 * This file contains the hardware configuration of the XTAVNET boards. 12 * This file contains the hardware configuration of the XTAVNET boards.
13 */ 13 */
14 14
15#include <asm/types.h>
16
15#ifndef __XTENSA_XTAVNET_HARDWARE_H 17#ifndef __XTENSA_XTAVNET_HARDWARE_H
16#define __XTENSA_XTAVNET_HARDWARE_H 18#define __XTENSA_XTAVNET_HARDWARE_H
17 19
18/* Memory configuration. */ 20/* Memory configuration. */
19 21
20#define PLATFORM_DEFAULT_MEM_START CONFIG_DEFAULT_MEM_START 22#define PLATFORM_DEFAULT_MEM_START __XTENSA_UL(CONFIG_DEFAULT_MEM_START)
21#define PLATFORM_DEFAULT_MEM_SIZE CONFIG_DEFAULT_MEM_SIZE 23#define PLATFORM_DEFAULT_MEM_SIZE __XTENSA_UL(CONFIG_DEFAULT_MEM_SIZE)
22 24
23/* Interrupt configuration. */ 25/* Interrupt configuration. */
24 26
diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index b4cf70e535ab..e9f65f79cf2e 100644
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -63,7 +63,9 @@ void platform_restart(void)
63#if XCHAL_NUM_IBREAK > 0 63#if XCHAL_NUM_IBREAK > 0
64 "wsr a2, ibreakenable\n\t" 64 "wsr a2, ibreakenable\n\t"
65#endif 65#endif
66#if XCHAL_HAVE_LOOPS
66 "wsr a2, lcount\n\t" 67 "wsr a2, lcount\n\t"
68#endif
67 "movi a2, 0x1f\n\t" 69 "movi a2, 0x1f\n\t"
68 "wsr a2, ps\n\t" 70 "wsr a2, ps\n\t"
69 "isync\n\t" 71 "isync\n\t"
diff --git a/arch/xtensa/variants/de212/include/variant/core.h b/arch/xtensa/variants/de212/include/variant/core.h
new file mode 100644
index 000000000000..59e91e47ef3c
--- /dev/null
+++ b/arch/xtensa/variants/de212/include/variant/core.h
@@ -0,0 +1,594 @@
1/*
2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3 * processor CORE configuration
4 *
5 * See <xtensa/config/core.h>, which includes this file, for more details.
6 */
7
8/* Xtensa processor core configuration information.
9
10 Copyright (c) 1999-2015 Tensilica Inc.
11
12 Permission is hereby granted, free of charge, to any person obtaining
13 a copy of this software and associated documentation files (the
14 "Software"), to deal in the Software without restriction, including
15 without limitation the rights to use, copy, modify, merge, publish,
16 distribute, sublicense, and/or sell copies of the Software, and to
17 permit persons to whom the Software is furnished to do so, subject to
18 the following conditions:
19
20 The above copyright notice and this permission notice shall be included
21 in all copies or substantial portions of the Software.
22
23 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
26 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
27 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
28 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
29 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
30
31#ifndef _XTENSA_CORE_CONFIGURATION_H
32#define _XTENSA_CORE_CONFIGURATION_H
33
34
35/****************************************************************************
36 Parameters Useful for Any Code, USER or PRIVILEGED
37 ****************************************************************************/
38
39/*
40 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
41 * configured, and a value of 0 otherwise. These macros are always defined.
42 */
43
44
45/*----------------------------------------------------------------------
46 ISA
47 ----------------------------------------------------------------------*/
48
49#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
50#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
51#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
52#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
53#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
54#define XCHAL_HAVE_DEBUG 1 /* debug option */
55#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
58#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
59#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
60#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
61#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
62#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
63#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
64#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
65#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
66#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
67#define XCHAL_HAVE_L32R 1 /* L32R instruction */
68#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
69#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
70#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
71#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
72#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
73#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
74#define XCHAL_HAVE_ABS 1 /* ABS instruction */
75/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
76/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
77#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
78#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
79#define XCHAL_HAVE_SPECULATION 0 /* speculation */
80#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
81#define XCHAL_NUM_CONTEXTS 1 /* */
82#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
83#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
84#define XCHAL_HAVE_PRID 1 /* processor ID register */
85#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
86#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
87#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
88#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
89#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
90#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
91#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
92#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
93#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
94#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
95#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
96#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
97
98#define XCHAL_HAVE_FUSION 0 /* Fusion*/
99#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
100#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
101#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
102#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
103#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
104#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
105#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
106#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
107#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
108#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
109#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
110#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
111#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
112#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
113#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
114#define XCHAL_HAVE_HIFI_MINI 0
115
116
117#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
118#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
119#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
120#define XCHAL_HAVE_FP 0 /* single prec floating point */
121#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
122#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
123#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
124#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
125#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
126#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
127#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
128#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
129#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
130#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
131#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
132
133#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
134#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
135#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
136#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
137#define XCHAL_HAVE_PDX4 0 /* PDX4 */
138#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
139#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
140#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
141#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
142#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
143#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
144#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
145#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
146#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
147#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
148#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
149#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
150#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
151#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
152#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
153#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
154
155
156/*----------------------------------------------------------------------
157 MISC
158 ----------------------------------------------------------------------*/
159
160#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
161#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
162#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
163#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
164#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
165 (1 = 5-stage, 2 = 7-stage) */
166#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */
167#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */
168/* In T1050, applies to selected core load and store instructions (see ISA): */
169#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
170#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
171#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
172#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
173
174#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
175
176#define XCHAL_CORE_ID "de212" /* alphanum core name
177 (CoreID) set in the Xtensa
178 Processor Generator */
179
180#define XCHAL_BUILD_UNIQUE_ID 0x0005A985 /* 22-bit sw build ID */
181
182/*
183 * These definitions describe the hardware targeted by this software.
184 */
185#define XCHAL_HW_CONFIGID0 0xC283DFFE /* ConfigID hi 32 bits*/
186#define XCHAL_HW_CONFIGID1 0x1C85A985 /* ConfigID lo 32 bits*/
187#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
188#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
189#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
190#define XCHAL_HW_VERSION 260002 /* major*100+minor */
191#define XCHAL_HW_REL_LX6 1
192#define XCHAL_HW_REL_LX6_0 1
193#define XCHAL_HW_REL_LX6_0_2 1
194#define XCHAL_HW_CONFIGID_RELIABLE 1
195/* If software targets a *range* of hardware versions, these are the bounds: */
196#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
197#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
198#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
199#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
200#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
201#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
202
203
204/*----------------------------------------------------------------------
205 CACHE
206 ----------------------------------------------------------------------*/
207
208#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
209#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
210#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
211#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
212
213#define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */
214#define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */
215
216#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
217#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
218
219#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
220#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
221#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
222#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
223#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
224#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
225#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
226#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
227#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
228#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
229
230
231
232
233/****************************************************************************
234 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
235 ****************************************************************************/
236
237
238#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
239
240/*----------------------------------------------------------------------
241 CACHE
242 ----------------------------------------------------------------------*/
243
244#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
245
246/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
247
248/* Number of cache sets in log2(lines per way): */
249#define XCHAL_ICACHE_SETWIDTH 7
250#define XCHAL_DCACHE_SETWIDTH 7
251
252/* Cache set associativity (number of ways): */
253#define XCHAL_ICACHE_WAYS 2
254#define XCHAL_DCACHE_WAYS 2
255
256/* Cache features: */
257#define XCHAL_ICACHE_LINE_LOCKABLE 1
258#define XCHAL_DCACHE_LINE_LOCKABLE 1
259#define XCHAL_ICACHE_ECC_PARITY 0
260#define XCHAL_DCACHE_ECC_PARITY 0
261
262/* Cache access size in bytes (affects operation of SICW instruction): */
263#define XCHAL_ICACHE_ACCESS_SIZE 4
264#define XCHAL_DCACHE_ACCESS_SIZE 4
265
266#define XCHAL_DCACHE_BANKS 1 /* number of banks */
267
268/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
269#define XCHAL_CA_BITS 4
270
271/* Whether MEMCTL register has anything useful */
272#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
273 XCHAL_DCACHE_IS_COHERENT || \
274 XCHAL_HAVE_ICACHE_DYN_WAYS || \
275 XCHAL_HAVE_DCACHE_DYN_WAYS) && \
276 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
277
278
279/*----------------------------------------------------------------------
280 INTERNAL I/D RAM/ROMs and XLMI
281 ----------------------------------------------------------------------*/
282
283#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
284#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
285#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
286#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
287#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
288#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
289
290/* Instruction RAM 0: */
291#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
292#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
293#define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */
294#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
295
296/* Data RAM 0: */
297#define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */
298#define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */
299#define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */
300#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
301#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
302
303/* XLMI Port 0: */
304#define XCHAL_XLMI0_VADDR 0x3FFC0000 /* virtual address */
305#define XCHAL_XLMI0_PADDR 0x3FFC0000 /* physical address */
306#define XCHAL_XLMI0_SIZE 131072 /* size in bytes */
307#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
308
309#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
310
311
312/*----------------------------------------------------------------------
313 INTERRUPTS and TIMERS
314 ----------------------------------------------------------------------*/
315
316#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
317#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
318#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
319#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
320#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
321#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
322#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
323#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
324#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
325 (not including level zero) */
326#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
327 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
328
329/* Masks of interrupts at each interrupt level: */
330#define XCHAL_INTLEVEL1_MASK 0x001F80FF
331#define XCHAL_INTLEVEL2_MASK 0x00000100
332#define XCHAL_INTLEVEL3_MASK 0x00200E00
333#define XCHAL_INTLEVEL4_MASK 0x00001000
334#define XCHAL_INTLEVEL5_MASK 0x00002000
335#define XCHAL_INTLEVEL6_MASK 0x00000000
336#define XCHAL_INTLEVEL7_MASK 0x00004000
337
338/* Masks of interrupts at each range 1..n of interrupt levels: */
339#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
340#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
341#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
342#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
343#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
344#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
345#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
346
347/* Level of each interrupt: */
348#define XCHAL_INT0_LEVEL 1
349#define XCHAL_INT1_LEVEL 1
350#define XCHAL_INT2_LEVEL 1
351#define XCHAL_INT3_LEVEL 1
352#define XCHAL_INT4_LEVEL 1
353#define XCHAL_INT5_LEVEL 1
354#define XCHAL_INT6_LEVEL 1
355#define XCHAL_INT7_LEVEL 1
356#define XCHAL_INT8_LEVEL 2
357#define XCHAL_INT9_LEVEL 3
358#define XCHAL_INT10_LEVEL 3
359#define XCHAL_INT11_LEVEL 3
360#define XCHAL_INT12_LEVEL 4
361#define XCHAL_INT13_LEVEL 5
362#define XCHAL_INT14_LEVEL 7
363#define XCHAL_INT15_LEVEL 1
364#define XCHAL_INT16_LEVEL 1
365#define XCHAL_INT17_LEVEL 1
366#define XCHAL_INT18_LEVEL 1
367#define XCHAL_INT19_LEVEL 1
368#define XCHAL_INT20_LEVEL 1
369#define XCHAL_INT21_LEVEL 3
370#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
371#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
372#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
373 EXCSAVE/EPS/EPC_n, RFI n) */
374
375/* Type of each interrupt: */
376#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
377#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
378#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
379#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
380#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
381#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
382#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
383#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
384#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
385#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
386#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
387#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
388#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
389#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
390#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
391#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
392#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
393#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
394#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
395#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
396#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
397#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
398
399/* Masks of interrupts for each type of interrupt: */
400#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
401#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
402#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
403#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
404#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
405#define XCHAL_INTTYPE_MASK_NMI 0x00004000
406#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
407#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
408
409/* Interrupt numbers assigned to specific interrupt sources: */
410#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
411#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
412#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
413#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
414#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
415
416/* Interrupt numbers for levels at which only one interrupt is configured: */
417#define XCHAL_INTLEVEL2_NUM 8
418#define XCHAL_INTLEVEL4_NUM 12
419#define XCHAL_INTLEVEL5_NUM 13
420#define XCHAL_INTLEVEL7_NUM 14
421/* (There are many interrupts each at level(s) 1, 3.) */
422
423
424/*
425 * External interrupt mapping.
426 * These macros describe how Xtensa processor interrupt numbers
427 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
428 * map to external BInterrupt<n> pins, for those interrupts
429 * configured as external (level-triggered, edge-triggered, or NMI).
430 * See the Xtensa processor databook for more details.
431 */
432
433/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
434#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
435#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
436#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
437#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
438#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
439#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
440#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
441#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
442#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
443#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
444#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
445#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
446#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
447#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
448#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
449#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
450#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
451/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
452#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
453#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
454#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
455#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
456#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
457#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
458#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
459#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
460#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
461#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
462#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
463#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
464#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
465#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
466#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
467#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
468#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
469
470
471/*----------------------------------------------------------------------
472 EXCEPTIONS and VECTORS
473 ----------------------------------------------------------------------*/
474
475#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
476 number: 1 == XEA1 (old)
477 2 == XEA2 (new)
478 0 == XEAX (extern) or TX */
479#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
480#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
481#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
482#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
483#define XCHAL_HAVE_HALT 0 /* halt architecture option */
484#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
485#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
486#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
487#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
488#define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */
489#define XCHAL_VECBASE_RESET_PADDR 0x60000000
490#define XCHAL_RESET_VECBASE_OVERLAP 0
491
492#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
493#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
494#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
495#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
496#define XCHAL_RESET_VECTOR_VADDR 0x50000000
497#define XCHAL_RESET_VECTOR_PADDR 0x50000000
498#define XCHAL_USER_VECOFS 0x00000340
499#define XCHAL_USER_VECTOR_VADDR 0x60000340
500#define XCHAL_USER_VECTOR_PADDR 0x60000340
501#define XCHAL_KERNEL_VECOFS 0x00000300
502#define XCHAL_KERNEL_VECTOR_VADDR 0x60000300
503#define XCHAL_KERNEL_VECTOR_PADDR 0x60000300
504#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
505#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x600003C0
506#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x600003C0
507#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
508#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
509#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
510#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
511#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
512#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
513#define XCHAL_WINDOW_VECTORS_VADDR 0x60000000
514#define XCHAL_WINDOW_VECTORS_PADDR 0x60000000
515#define XCHAL_INTLEVEL2_VECOFS 0x00000180
516#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x60000180
517#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x60000180
518#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
519#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x600001C0
520#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x600001C0
521#define XCHAL_INTLEVEL4_VECOFS 0x00000200
522#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x60000200
523#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x60000200
524#define XCHAL_INTLEVEL5_VECOFS 0x00000240
525#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x60000240
526#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x60000240
527#define XCHAL_INTLEVEL6_VECOFS 0x00000280
528#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x60000280
529#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x60000280
530#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
531#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
532#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
533#define XCHAL_NMI_VECOFS 0x000002C0
534#define XCHAL_NMI_VECTOR_VADDR 0x600002C0
535#define XCHAL_NMI_VECTOR_PADDR 0x600002C0
536#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
537#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
538#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
539
540
541/*----------------------------------------------------------------------
542 DEBUG MODULE
543 ----------------------------------------------------------------------*/
544
545/* Misc */
546#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
547#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
548#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
549
550/* On-Chip Debug (OCD) */
551#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
552#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
553#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
554#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
555#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
556
557/* TRAX (in core) */
558#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
559#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */
560#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
561#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
562#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
563
564/* Perf counters */
565#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
566
567
568/*----------------------------------------------------------------------
569 MMU
570 ----------------------------------------------------------------------*/
571
572/* See core-matmap.h header file for more details. */
573
574#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
575#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
576#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
577#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
578#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
579#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
580#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
581#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
582 [autorefill] and protection)
583 usable for an MMU-based OS */
584/* If none of the above last 4 are set, it's a custom TLB configuration. */
585
586#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
587#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
588#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
589
590#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
591
592
593#endif /* _XTENSA_CORE_CONFIGURATION_H */
594
diff --git a/arch/xtensa/variants/de212/include/variant/tie-asm.h b/arch/xtensa/variants/de212/include/variant/tie-asm.h
new file mode 100644
index 000000000000..77755354f571
--- /dev/null
+++ b/arch/xtensa/variants/de212/include/variant/tie-asm.h
@@ -0,0 +1,170 @@
1/*
2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
3 *
4 * NOTE: This header file is not meant to be included directly.
5 */
6
7/* This header file contains assembly-language definitions (assembly
8 macros, etc.) for this specific Xtensa processor's TIE extensions
9 and options. It is customized to this Xtensa processor configuration.
10
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice shall be included
22 in all copies or substantial portions of the Software.
23
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
31
32#ifndef _XTENSA_CORE_TIE_ASM_H
33#define _XTENSA_CORE_TIE_ASM_H
34
35/* Selection parameter values for save-area save/restore macros: */
36/* Option vs. TIE: */
37#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
38#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
39#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
40/* Whether used automatically by compiler: */
41#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
42#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
43#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
44/* ABI handling across function calls: */
45#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
46#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
47#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
48#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
49/* Misc */
50#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
51#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
52 | ((ccuse) & XTHAL_SAS_ANYCC) \
53 | ((abi) & XTHAL_SAS_ANYABI) )
54
55
56 /*
57 * Macro to store all non-coprocessor (extra) custom TIE and optional state
58 * (not including zero-overhead loop registers).
59 * Required parameters:
60 * ptr Save area pointer address register (clobbered)
61 * (register must contain a 4 byte aligned address).
62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63 * registers are clobbered, the remaining are unused).
64 * Optional parameters:
65 * continue If macro invoked as part of a larger store sequence, set to 1
66 * if this is not the first in the sequence. Defaults to 0.
67 * ofs Offset from start of larger sequence (from value of first ptr
68 * in sequence) at which to store. Defaults to next available space
69 * (or 0 if <continue> is 0).
70 * select Select what category(ies) of registers to store, as a bitmask
71 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
72 * alloc Select what category(ies) of registers to allocate; if any
73 * category is selected here that is not in <select>, space for
74 * the corresponding registers is skipped without doing any store.
75 */
76 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
77 xchal_sa_start \continue, \ofs
78 // Optional caller-saved registers used by default by the compiler:
79 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
80 xchal_sa_align \ptr, 0, 1016, 4, 4
81 rsr.ACCLO \at1 // MAC16 option
82 s32i \at1, \ptr, .Lxchal_ofs_+0
83 rsr.ACCHI \at1 // MAC16 option
84 s32i \at1, \ptr, .Lxchal_ofs_+4
85 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
86 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
87 xchal_sa_align \ptr, 0, 1016, 4, 4
88 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
89 .endif
90 // Optional caller-saved registers not used by default by the compiler:
91 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
92 xchal_sa_align \ptr, 0, 1004, 4, 4
93 rsr.SCOMPARE1 \at1 // conditional store option
94 s32i \at1, \ptr, .Lxchal_ofs_+0
95 rsr.M0 \at1 // MAC16 option
96 s32i \at1, \ptr, .Lxchal_ofs_+4
97 rsr.M1 \at1 // MAC16 option
98 s32i \at1, \ptr, .Lxchal_ofs_+8
99 rsr.M2 \at1 // MAC16 option
100 s32i \at1, \ptr, .Lxchal_ofs_+12
101 rsr.M3 \at1 // MAC16 option
102 s32i \at1, \ptr, .Lxchal_ofs_+16
103 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
104 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
105 xchal_sa_align \ptr, 0, 1004, 4, 4
106 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
107 .endif
108 .endm // xchal_ncp_store
109
110 /*
111 * Macro to load all non-coprocessor (extra) custom TIE and optional state
112 * (not including zero-overhead loop registers).
113 * Required parameters:
114 * ptr Save area pointer address register (clobbered)
115 * (register must contain a 4 byte aligned address).
116 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
117 * registers are clobbered, the remaining are unused).
118 * Optional parameters:
119 * continue If macro invoked as part of a larger load sequence, set to 1
120 * if this is not the first in the sequence. Defaults to 0.
121 * ofs Offset from start of larger sequence (from value of first ptr
122 * in sequence) at which to load. Defaults to next available space
123 * (or 0 if <continue> is 0).
124 * select Select what category(ies) of registers to load, as a bitmask
125 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
126 * alloc Select what category(ies) of registers to allocate; if any
127 * category is selected here that is not in <select>, space for
128 * the corresponding registers is skipped without doing any load.
129 */
130 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
131 xchal_sa_start \continue, \ofs
132 // Optional caller-saved registers used by default by the compiler:
133 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
134 xchal_sa_align \ptr, 0, 1016, 4, 4
135 l32i \at1, \ptr, .Lxchal_ofs_+0
136 wsr.ACCLO \at1 // MAC16 option
137 l32i \at1, \ptr, .Lxchal_ofs_+4
138 wsr.ACCHI \at1 // MAC16 option
139 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
140 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
141 xchal_sa_align \ptr, 0, 1016, 4, 4
142 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
143 .endif
144 // Optional caller-saved registers not used by default by the compiler:
145 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
146 xchal_sa_align \ptr, 0, 1004, 4, 4
147 l32i \at1, \ptr, .Lxchal_ofs_+0
148 wsr.SCOMPARE1 \at1 // conditional store option
149 l32i \at1, \ptr, .Lxchal_ofs_+4
150 wsr.M0 \at1 // MAC16 option
151 l32i \at1, \ptr, .Lxchal_ofs_+8
152 wsr.M1 \at1 // MAC16 option
153 l32i \at1, \ptr, .Lxchal_ofs_+12
154 wsr.M2 \at1 // MAC16 option
155 l32i \at1, \ptr, .Lxchal_ofs_+16
156 wsr.M3 \at1 // MAC16 option
157 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
158 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
159 xchal_sa_align \ptr, 0, 1004, 4, 4
160 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
161 .endif
162 .endm // xchal_ncp_load
163
164
165#define XCHAL_NCP_NUM_ATMPS 1
166
167#define XCHAL_SA_NUM_ATMPS 1
168
169#endif /*_XTENSA_CORE_TIE_ASM_H*/
170
diff --git a/arch/xtensa/variants/de212/include/variant/tie.h b/arch/xtensa/variants/de212/include/variant/tie.h
new file mode 100644
index 000000000000..b8a061a3fa10
--- /dev/null
+++ b/arch/xtensa/variants/de212/include/variant/tie.h
@@ -0,0 +1,136 @@
1/*
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
3 *
4 * NOTE: This header file is not meant to be included directly.
5 */
6
7/* This header file describes this specific Xtensa processor's TIE extensions
8 that extend basic Xtensa core functionality. It is customized to this
9 Xtensa processor configuration.
10
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice shall be included
22 in all copies or substantial portions of the Software.
23
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
31
32#ifndef _XTENSA_CORE_TIE_H
33#define _XTENSA_CORE_TIE_H
34
35#define XCHAL_CP_NUM 0 /* number of coprocessors */
36#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
37#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
38#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
39
40/* Save area for non-coprocessor optional and custom (TIE) state: */
41#define XCHAL_NCP_SA_SIZE 28
42#define XCHAL_NCP_SA_ALIGN 4
43
44/* Total save area for optional and custom state (NCP + CPn): */
45#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
46#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
47
48/*
49 * Detailed contents of save areas.
50 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
51 * before expanding the XCHAL_xxx_SA_LIST() macros.
52 *
53 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
54 * dbnum,base,regnum,bitsz,gapsz,reset,x...)
55 *
56 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
57 * ccused = set if used by compiler without special options or code
58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
60 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
61 * name = lowercase reg name (no quotes)
62 * galign = group byte alignment (power of 2) (galign >= align)
63 * align = register byte alignment (power of 2)
64 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
65 * (not including any pad bytes required to galign this or next reg)
66 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
67 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
68 * regnum = reg index in regfile, or special/TIE-user reg number
69 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
70 * gapsz = intervening bits, if bitsz bits not stored contiguously
71 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
72 * reset = register reset value (or 0 if undefined at reset)
73 * x = reserved for future use (0 until then)
74 *
75 * To filter out certain registers, e.g. to expand only the non-global
76 * registers used by the compiler, you can do something like this:
77 *
78 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
79 * #define SELCC0(p...)
80 * #define SELCC1(abikind,p...) SELAK##abikind(p)
81 * #define SELAK0(p...) REG(p)
82 * #define SELAK1(p...) REG(p)
83 * #define SELAK2(p...)
84 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
85 * ...what you want to expand...
86 */
87
88#define XCHAL_NCP_SA_NUM 7
89#define XCHAL_NCP_SA_LIST(s) \
90 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
91 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
92 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
93 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
95 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
97
98#define XCHAL_CP0_SA_NUM 0
99#define XCHAL_CP0_SA_LIST(s) /* empty */
100
101#define XCHAL_CP1_SA_NUM 0
102#define XCHAL_CP1_SA_LIST(s) /* empty */
103
104#define XCHAL_CP2_SA_NUM 0
105#define XCHAL_CP2_SA_LIST(s) /* empty */
106
107#define XCHAL_CP3_SA_NUM 0
108#define XCHAL_CP3_SA_LIST(s) /* empty */
109
110#define XCHAL_CP4_SA_NUM 0
111#define XCHAL_CP4_SA_LIST(s) /* empty */
112
113#define XCHAL_CP5_SA_NUM 0
114#define XCHAL_CP5_SA_LIST(s) /* empty */
115
116#define XCHAL_CP6_SA_NUM 0
117#define XCHAL_CP6_SA_LIST(s) /* empty */
118
119#define XCHAL_CP7_SA_NUM 0
120#define XCHAL_CP7_SA_LIST(s) /* empty */
121
122/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
123#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
124/* Byte length of instruction from its first byte, per FLIX. */
125#define XCHAL_BYTE0_FORMAT_LENGTHS \
126 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
127 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
128 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
129 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
130 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
131 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
132 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
133 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
134
135#endif /*_XTENSA_CORE_TIE_H*/
136
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