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authorAlex Deucher <alexander.deucher@amd.com>2018-11-29 19:35:14 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-12-07 17:24:14 -0500
commit34c08da2097abe99cdc4757194f10a0c51148ce3 (patch)
treeaedb5137ec9b36e0d011bf326f85a37a64f23fc4
parentc6296f5a658974169261ed8fe75887e7552174af (diff)
drm/amdgpu/powerplay: check MC firmware for FFC support
Check if the MC firmware supports FFC and tell the SMC so mclk switching is handled properly. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 6bfbfd37ed92..d94c7d03bf24 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4222,9 +4222,17 @@ static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
4222 if (tmp & (1 << 23)) { 4222 if (tmp & (1 << 23)) {
4223 data->mem_latency_high = MEM_LATENCY_HIGH; 4223 data->mem_latency_high = MEM_LATENCY_HIGH;
4224 data->mem_latency_low = MEM_LATENCY_LOW; 4224 data->mem_latency_low = MEM_LATENCY_LOW;
4225 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4226 (hwmgr->chip_id == CHIP_POLARIS11) ||
4227 (hwmgr->chip_id == CHIP_POLARIS12))
4228 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC);
4225 } else { 4229 } else {
4226 data->mem_latency_high = 330; 4230 data->mem_latency_high = 330;
4227 data->mem_latency_low = 330; 4231 data->mem_latency_low = 330;
4232 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4233 (hwmgr->chip_id == CHIP_POLARIS11) ||
4234 (hwmgr->chip_id == CHIP_POLARIS12))
4235 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC);
4228 } 4236 }
4229 4237
4230 return 0; 4238 return 0;