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authorJan Beulich <JBeulich@suse.com>2016-06-27 02:35:12 -0400
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2016-07-08 19:05:30 -0400
commit3451ab3ebf92b12801878d8b5c94845afd4219f0 (patch)
tree60b304f2539da187b430ae0539e2657b6487e646
parentb55a0262a4fb4a9754f8a3319df0a6d2fe4c4c58 (diff)
intel_idle: re-work bxt_idle_state_table_update() and its helper
Since irtl_ns_units[] has itself zero entries, make sure the caller recognized those cases along with the MSR read returning zero, as zero is not a valid value for exit_latency and target_residency. Signed-off-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
-rw-r--r--drivers/idle/intel_idle.c29
1 files changed, 14 insertions, 15 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 170ab8e01075..5300f2545e2a 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -1187,6 +1187,9 @@ static unsigned long long irtl_2_usec(unsigned long long irtl)
1187{ 1187{
1188 unsigned long long ns; 1188 unsigned long long ns;
1189 1189
1190 if (!irtl)
1191 return 0;
1192
1190 ns = irtl_ns_units[(irtl >> 10) & 0x3]; 1193 ns = irtl_ns_units[(irtl >> 10) & 0x3];
1191 1194
1192 return div64_u64((irtl & 0x3FF) * ns, 1000); 1195 return div64_u64((irtl & 0x3FF) * ns, 1000);
@@ -1200,43 +1203,39 @@ static unsigned long long irtl_2_usec(unsigned long long irtl)
1200static void bxt_idle_state_table_update(void) 1203static void bxt_idle_state_table_update(void)
1201{ 1204{
1202 unsigned long long msr; 1205 unsigned long long msr;
1206 unsigned int usec;
1203 1207
1204 rdmsrl(MSR_PKGC6_IRTL, msr); 1208 rdmsrl(MSR_PKGC6_IRTL, msr);
1205 if (msr) { 1209 usec = irtl_2_usec(msr);
1206 unsigned int usec = irtl_2_usec(msr); 1210 if (usec) {
1207
1208 bxt_cstates[2].exit_latency = usec; 1211 bxt_cstates[2].exit_latency = usec;
1209 bxt_cstates[2].target_residency = usec; 1212 bxt_cstates[2].target_residency = usec;
1210 } 1213 }
1211 1214
1212 rdmsrl(MSR_PKGC7_IRTL, msr); 1215 rdmsrl(MSR_PKGC7_IRTL, msr);
1213 if (msr) { 1216 usec = irtl_2_usec(msr);
1214 unsigned int usec = irtl_2_usec(msr); 1217 if (usec) {
1215
1216 bxt_cstates[3].exit_latency = usec; 1218 bxt_cstates[3].exit_latency = usec;
1217 bxt_cstates[3].target_residency = usec; 1219 bxt_cstates[3].target_residency = usec;
1218 } 1220 }
1219 1221
1220 rdmsrl(MSR_PKGC8_IRTL, msr); 1222 rdmsrl(MSR_PKGC8_IRTL, msr);
1221 if (msr) { 1223 usec = irtl_2_usec(msr);
1222 unsigned int usec = irtl_2_usec(msr); 1224 if (usec) {
1223
1224 bxt_cstates[4].exit_latency = usec; 1225 bxt_cstates[4].exit_latency = usec;
1225 bxt_cstates[4].target_residency = usec; 1226 bxt_cstates[4].target_residency = usec;
1226 } 1227 }
1227 1228
1228 rdmsrl(MSR_PKGC9_IRTL, msr); 1229 rdmsrl(MSR_PKGC9_IRTL, msr);
1229 if (msr) { 1230 usec = irtl_2_usec(msr);
1230 unsigned int usec = irtl_2_usec(msr); 1231 if (usec) {
1231
1232 bxt_cstates[5].exit_latency = usec; 1232 bxt_cstates[5].exit_latency = usec;
1233 bxt_cstates[5].target_residency = usec; 1233 bxt_cstates[5].target_residency = usec;
1234 } 1234 }
1235 1235
1236 rdmsrl(MSR_PKGC10_IRTL, msr); 1236 rdmsrl(MSR_PKGC10_IRTL, msr);
1237 if (msr) { 1237 usec = irtl_2_usec(msr);
1238 unsigned int usec = irtl_2_usec(msr); 1238 if (usec) {
1239
1240 bxt_cstates[6].exit_latency = usec; 1239 bxt_cstates[6].exit_latency = usec;
1241 bxt_cstates[6].target_residency = usec; 1240 bxt_cstates[6].target_residency = usec;
1242 } 1241 }