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authorTadeusz Struk <tadeusz.struk@intel.com>2016-03-08 13:37:15 -0500
committerHerbert Xu <herbert@gondor.apana.org.au>2016-03-11 08:22:18 -0500
commit34074205bb9f04b416efb3cbedcd90f418c86200 (patch)
tree46e4c74721a01fe79e327220eed4ad037ad38c5c
parentb62917a2622ebcb03a500ef20da47be80d8c8951 (diff)
crypto: qat - remove redundant arbiter configuration
The default arbiter configuration for ring weights and response ordering is exactly what we want so we don't need to configure anything more. This will also fix the problem where number of bundles is different between different devices. Reported-by: Ahsan Atta <ahsan.atta@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-rw-r--r--drivers/crypto/qat/qat_common/adf_hw_arbiter.c19
1 files changed, 0 insertions, 19 deletions
diff --git a/drivers/crypto/qat/qat_common/adf_hw_arbiter.c b/drivers/crypto/qat/qat_common/adf_hw_arbiter.c
index f267d9e42e0b..d7dd18d9bef8 100644
--- a/drivers/crypto/qat/qat_common/adf_hw_arbiter.c
+++ b/drivers/crypto/qat/qat_common/adf_hw_arbiter.c
@@ -49,7 +49,6 @@
49#include "adf_transport_internal.h" 49#include "adf_transport_internal.h"
50 50
51#define ADF_ARB_NUM 4 51#define ADF_ARB_NUM 4
52#define ADF_ARB_REQ_RING_NUM 8
53#define ADF_ARB_REG_SIZE 0x4 52#define ADF_ARB_REG_SIZE 0x4
54#define ADF_ARB_WTR_SIZE 0x20 53#define ADF_ARB_WTR_SIZE 0x20
55#define ADF_ARB_OFFSET 0x30000 54#define ADF_ARB_OFFSET 0x30000
@@ -64,15 +63,6 @@
64 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \ 63 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
65 (ADF_ARB_REG_SLOT * index), value) 64 (ADF_ARB_REG_SLOT * index), value)
66 65
67#define WRITE_CSR_ARB_RESPORDERING(csr_addr, index, value) \
68 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
69 ADF_ARB_RO_EN_OFFSET) + (ADF_ARB_REG_SIZE * index), value)
70
71#define WRITE_CSR_ARB_WEIGHT(csr_addr, arb, index, value) \
72 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
73 ADF_ARB_WTR_OFFSET) + (ADF_ARB_WTR_SIZE * arb) + \
74 (ADF_ARB_REG_SIZE * index), value)
75
76#define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \ 66#define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \
77 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \ 67 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
78 (ADF_ARB_REG_SIZE * index), value) 68 (ADF_ARB_REG_SIZE * index), value)
@@ -99,15 +89,6 @@ int adf_init_arb(struct adf_accel_dev *accel_dev)
99 for (arb = 0; arb < ADF_ARB_NUM; arb++) 89 for (arb = 0; arb < ADF_ARB_NUM; arb++)
100 WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg); 90 WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg);
101 91
102 /* Setup service weighting */
103 for (arb = 0; arb < ADF_ARB_NUM; arb++)
104 for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
105 WRITE_CSR_ARB_WEIGHT(csr, arb, i, 0xFFFFFFFF);
106
107 /* Setup ring response ordering */
108 for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
109 WRITE_CSR_ARB_RESPORDERING(csr, i, 0xFFFFFFFF);
110
111 /* Setup worker queue registers */ 92 /* Setup worker queue registers */
112 for (i = 0; i < hw_data->num_engines; i++) 93 for (i = 0; i < hw_data->num_engines; i++)
113 WRITE_CSR_ARB_WQCFG(csr, i, i); 94 WRITE_CSR_ARB_WQCFG(csr, i, i);