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authorBard Liao <bardliao@realtek.com>2015-04-30 06:18:42 -0400
committerMark Brown <broonie@kernel.org>2015-05-01 12:33:47 -0400
commit33de3d54b8b6fc53b9bace4772a70915ca96ecea (patch)
tree03b0a58f6276dfeb8703c546b99450057ceb616e
parente0b5d90669139cd3e7c2592ac2eff47c57318e94 (diff)
ASoC: rt5645: remove RT5645_I2S_BCLK_MS1 control
RT5645_I2S_BCLK_MS1 (reg 0x73 [5]) is reserverd in rt5645 and rt5650. This function is move to TDM control. We can configure it by snd_soc_dai_set_tdm_slot's slot_width parameter. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/codecs/rt5645.c5
-rw-r--r--sound/soc/codecs/rt5645.h4
2 files changed, 2 insertions, 7 deletions
diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c
index b7b095994a75..5d71bfbdacf1 100644
--- a/sound/soc/codecs/rt5645.c
+++ b/sound/soc/codecs/rt5645.c
@@ -2104,9 +2104,8 @@ static int rt5645_hw_params(struct snd_pcm_substream *substream,
2104 2104
2105 switch (dai->id) { 2105 switch (dai->id) {
2106 case RT5645_AIF1: 2106 case RT5645_AIF1:
2107 mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK; 2107 mask_clk = RT5645_I2S_PD1_MASK;
2108 val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT | 2108 val_clk = pre_div << RT5645_I2S_PD1_SFT;
2109 pre_div << RT5645_I2S_PD1_SFT;
2110 snd_soc_update_bits(codec, RT5645_I2S1_SDP, 2109 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2111 (0x3 << dl_sft), (val_len << dl_sft)); 2110 (0x3 << dl_sft), (val_len << dl_sft));
2112 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); 2111 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
diff --git a/sound/soc/codecs/rt5645.h b/sound/soc/codecs/rt5645.h
index 4473636521e5..fa5c56037d58 100644
--- a/sound/soc/codecs/rt5645.h
+++ b/sound/soc/codecs/rt5645.h
@@ -942,10 +942,6 @@
942#define RT5645_I2S2_SDI_I2S2 (0x1 << 6) 942#define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
943 943
944/* ADC/DAC Clock Control 1 (0x73) */ 944/* ADC/DAC Clock Control 1 (0x73) */
945#define RT5645_I2S_BCLK_MS1_MASK (0x1 << 15)
946#define RT5645_I2S_BCLK_MS1_SFT 15
947#define RT5645_I2S_BCLK_MS1_32 (0x0 << 15)
948#define RT5645_I2S_BCLK_MS1_64 (0x1 << 15)
949#define RT5645_I2S_PD1_MASK (0x7 << 12) 945#define RT5645_I2S_PD1_MASK (0x7 << 12)
950#define RT5645_I2S_PD1_SFT 12 946#define RT5645_I2S_PD1_SFT 12
951#define RT5645_I2S_PD1_1 (0x0 << 12) 947#define RT5645_I2S_PD1_1 (0x0 << 12)