aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTal Gilboa <talgi@mellanox.com>2018-03-30 10:01:51 -0400
committerBjorn Helgaas <helgaas@kernel.org>2018-04-03 09:58:33 -0400
commit33523a361307c097a8a23f3549cb485db5fba6c5 (patch)
tree28dd8eb0a75acbfc0958bf8e8ef5e771ba308dfb
parent00c6bcb0d60e3f05a533d324ca17b21b6af87fea (diff)
net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth
Use the new pci_bandwidth_available() function to calculate maximum available bandwidth through the PCI chain instead of computing it ourselves with mlx5e_get_pci_bw(). This is used to detect when the device is capable of more bandwidth than is available in the current slot. The driver may adjust compression settings accordingly. Note that pci_bandwidth_available() accounts for PCIe encoding overhead, so it is more accurate than mlx5e_get_pci_bw() was. Signed-off-by: Tal Gilboa <talgi@mellanox.com> [bhelgaas: remove mlx5e_get_pci_bw() wrapper altogether] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
-rw-r--r--drivers/net/ethernet/mellanox/mlx5/core/en_main.c32
1 files changed, 1 insertions, 31 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 47bab842c5ee..93291ec4a3d1 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -3864,36 +3864,6 @@ void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
3864 indirection_rqt[i] = i % num_channels; 3864 indirection_rqt[i] = i % num_channels;
3865} 3865}
3866 3866
3867static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3868{
3869 enum pcie_link_width width;
3870 enum pci_bus_speed speed;
3871 int err = 0;
3872
3873 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3874 if (err)
3875 return err;
3876
3877 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3878 return -EINVAL;
3879
3880 switch (speed) {
3881 case PCIE_SPEED_2_5GT:
3882 *pci_bw = 2500 * width;
3883 break;
3884 case PCIE_SPEED_5_0GT:
3885 *pci_bw = 5000 * width;
3886 break;
3887 case PCIE_SPEED_8_0GT:
3888 *pci_bw = 8000 * width;
3889 break;
3890 default:
3891 return -EINVAL;
3892 }
3893
3894 return 0;
3895}
3896
3897static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw) 3867static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3898{ 3868{
3899 return (link_speed && pci_bw && 3869 return (link_speed && pci_bw &&
@@ -3979,7 +3949,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3979 params->num_tc = 1; 3949 params->num_tc = 1;
3980 3950
3981 mlx5e_get_max_linkspeed(mdev, &link_speed); 3951 mlx5e_get_max_linkspeed(mdev, &link_speed);
3982 mlx5e_get_pci_bw(mdev, &pci_bw); 3952 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
3983 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n", 3953 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3984 link_speed, pci_bw); 3954 link_speed, pci_bw);
3985 3955