Merge branch 'clk-qcom-sdm845-lpass' into clk-next

 - Qualcomm SDM845 audio subsystem clks

* clk-qcom-sdm845-lpass:
  clk: qcom: Add lpass clock controller driver for SDM845
  dt-bindings: clock: Introduce QCOM LPASS clock bindings
  dt-bindings: clock: Update GCC bindings for protected-clocks

8 files changed, 282 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 52d9345c9927..8661c3cd3ccf 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -35,6 +35,8 @@ be part of GCC and hence the TSENS properties can also be
 part of the GCC/clock-controller node.
 For more details on the TSENS properties please refer
 Documentation/devicetree/bindings/thermal/qcom-tsens.txt
+- protected-clocks : Protected clock specifier list as per common clock
+ binding.
 
 Example:
         clock-controller@900000 {
@@ -55,3 +57,17 @@ Example of GCC with TSENS properties:
                 #reset-cells = <1>;
                 #thermal-sensor-cells = <1>;
         };
+
+Example of GCC with protected-clocks properties:
+        clock-controller@100000 {
+                compatible = "qcom,gcc-sdm845";
+                reg = <0x100000 0x1f0000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+                #power-domain-cells = <1>;
+                protected-clocks = <GCC_QSPI_CORE_CLK>,
+                                   <GCC_QSPI_CORE_CLK_SRC>,
+                                   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+                                   <GCC_LPASS_Q6_AXI_CLK>,
+                                   <GCC_LPASS_SWAY_CLK>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
new file mode 100644
index 000000000000..b9e9787045b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
@@ -0,0 +1,26 @@
+Qualcomm LPASS Clock Controller Binding
+-----------------------------------------------
+
+Required properties :
+- compatible            : shall contain "qcom,sdm845-lpasscc"
+- #clock-cells          : from common clock binding, shall contain 1.
+- reg                   : shall contain base register address and size,
+                          in the order
+                        Index-0 maps to LPASS_CC register region
+                        Index-1 maps to LPASS_QDSP6SS register region
+
+Optional properties :
+- reg-names     : register names of LPASS domain
+                 "cc", "qdsp6ss".
+
+Example:
+
+The below node has to be defined in the cases where the LPASS peripheral loader
+would bring the subsystem out of reset.
+
+        lpasscc: clock-controller@17014000 {
+                compatible = "qcom,sdm845-lpasscc";
+                reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
+                reg-names = "cc", "qdsp6ss";
+                #clock-cells = <1>;
+        };
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index aca754f09817..1b1ba54e33dd 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -276,6 +276,14 @@ config SDM_DISPCC_845
           Say Y if you want to support display devices and functionality such as
           splash screen.
 
+config SDM_LPASSCC_845
+        tristate "SDM845 Low Power Audio Subsystem (LPAAS) Clock Controller"
+        select SDM_GCC_845
+        help
+          Support for the LPASS clock controller on SDM845 devices.
+          Say Y if you want to use the LPASS branch clocks of the LPASS clock
+          controller to reset the LPASS subsystem.
+
 config SPMI_PMIC_CLKDIV
         tristate "SPMI PMIC clkdiv Support"
         depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 6ed28272e176..ee8d0698e370 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
 obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
 obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
 obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
+obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index f133b7f5652f..c782e62dd98b 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3153,6 +3153,37 @@ static struct clk_branch gcc_cpuss_gnoc_clk = {
         },
 };
 
+/* TODO: Remove after DTS updated to protect these */
+#ifdef CONFIG_SDM_LPASSCC_845
+static struct clk_branch gcc_lpass_q6_axi_clk = {
+        .halt_reg = 0x47000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x47000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_lpass_q6_axi_clk",
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_lpass_sway_clk = {
+        .halt_reg = 0x47008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x47008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_lpass_sway_clk",
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+#endif
+
 static struct gdsc pcie_0_gdsc = {
         .gdscr = 0x6b004,
         .pd = {
@@ -3453,6 +3484,10 @@ static struct clk_regmap *gcc_sdm845_clocks[] = {
         [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
         [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
         [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
+#ifdef CONFIG_SDM_LPASSCC_845
+        [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
+        [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
+#endif
 };
 
 static const struct qcom_reset_map gcc_sdm845_resets[] = {
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c
new file mode 100644
index 000000000000..e246b99dfbc6
--- /dev/null
+++ b/drivers/clk/qcom/lpasscc-sdm845.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,lpass-sdm845.h>
+
+#include "clk-regmap.h"
+#include "clk-branch.h"
+#include "common.h"
+
+static struct clk_branch lpass_q6ss_ahbm_aon_clk = {
+        .halt_reg = 0x12000,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x12000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "lpass_q6ss_ahbm_aon_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch lpass_q6ss_ahbs_aon_clk = {
+        .halt_reg = 0x1f000,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x1f000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "lpass_q6ss_ahbs_aon_clk",