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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2019-03-24 11:11:02 -0400
committerNeil Armstrong <narmstrong@baylibre.com>2019-04-01 07:33:52 -0400
commit32cd198a1a505566f8e9d2c925bcfc8b889bbc23 (patch)
tree8ef07013bd23767fd4bdd7b03cfb74c527f4826e
parent4b0f73055acaced436d5de909b26d001ea7f667c (diff)
clk: meson: meson8b: use a separate clock table for Meson8m2
Meson8, Meson8b and Meson8m2 implement a similar clock controller. However, there are a few differences between the three actual IP blocks. One example where Meson8m2 differs from Meson8b is the VPU clock setup: - the VPU input mux can choose between "fclk_div4", "fclk_div3", "fclk_div5" and "fclk_div7" on Meson8b - however, on Meson8m2 it can choose between "fclk_div4", "fclk_div3", "fclk_div5" and "gp_pll" (GP_PLL only exists on Meson8m2, it's the predecessor of the GP0_PLL clock on GXBB/GXL/GXM)) Add a separate clk_hw_onecell_data table for Meson8m2 so these differences can be implemented in our clock controller driver. For now meson8m2_hw_onecell_data is a clone of our existing meson8b_hw_onecell_data. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190324151104.18397-3-martin.blumenstingl@googlemail.com
Diffstat
-rw-r--r--drivers/clk/meson/meson8b.c193
1 files changed, 192 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 576ad42252d0..c9e6ec67d649 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -2157,6 +2157,192 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
2157 .num = CLK_NR_CLKS, 2157 .num = CLK_NR_CLKS,
2158}; 2158};
2159 2159
2160static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
2161 .hws = {
2162 [CLKID_XTAL] = &meson8b_xtal.hw,
2163 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2164 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2165 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2166 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2167 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2168 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2169 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2170 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2171 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2172 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2173 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2174 [CLKID_CLK81] = &meson8b_clk81.hw,
2175 [CLKID_DDR] = &meson8b_ddr.hw,
2176 [CLKID_DOS] = &meson8b_dos.hw,
2177 [CLKID_ISA] = &meson8b_isa.hw,
2178 [CLKID_PL301] = &meson8b_pl301.hw,
2179 [CLKID_PERIPHS] = &meson8b_periphs.hw,
2180 [CLKID_SPICC] = &meson8b_spicc.hw,
2181 [CLKID_I2C] = &meson8b_i2c.hw,
2182 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
2183 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
2184 [CLKID_RNG0] = &meson8b_rng0.hw,
2185 [CLKID_UART0] = &meson8b_uart0.hw,
2186 [CLKID_SDHC] = &meson8b_sdhc.hw,
2187 [CLKID_STREAM] = &meson8b_stream.hw,
2188 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
2189 [CLKID_SDIO] = &meson8b_sdio.hw,
2190 [CLKID_ABUF] = &meson8b_abuf.hw,
2191 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
2192 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
2193 [CLKID_SPI] = &meson8b_spi.hw,
2194 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
2195 [CLKID_ETH] = &meson8b_eth.hw,
2196 [CLKID_DEMUX] = &meson8b_demux.hw,
2197 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
2198 [CLKID_IEC958] = &meson8b_iec958.hw,
2199 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
2200 [CLKID_AMCLK] = &meson8b_amclk.hw,
2201 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
2202 [CLKID_MIXER] = &meson8b_mixer.hw,
2203 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
2204 [CLKID_ADC] = &meson8b_adc.hw,
2205 [CLKID_BLKMV] = &meson8b_blkmv.hw,
2206 [CLKID_AIU] = &meson8b_aiu.hw,
2207 [CLKID_UART1] = &meson8b_uart1.hw,
2208 [CLKID_G2D] = &meson8b_g2d.hw,
2209 [CLKID_USB0] = &meson8b_usb0.hw,
2210 [CLKID_USB1] = &meson8b_usb1.hw,
2211 [CLKID_RESET] = &meson8b_reset.hw,
2212 [CLKID_NAND] = &meson8b_nand.hw,
2213 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
2214 [CLKID_USB] = &meson8b_usb.hw,
2215 [CLKID_VDIN1] = &meson8b_vdin1.hw,
2216 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
2217 [CLKID_EFUSE] = &meson8b_efuse.hw,
2218 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
2219 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
2220 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
2221 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
2222 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
2223 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
2224 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
2225 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
2226 [CLKID_DVIN] = &meson8b_dvin.hw,
2227 [CLKID_UART2] = &meson8b_uart2.hw,
2228 [CLKID_SANA] = &meson8b_sana.hw,
2229 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
2230 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2231 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
2232 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
2233 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
2234 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
2235 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
2236 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
2237 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
2238 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
2239 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
2240 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
2241 [CLKID_ENC480P] = &meson8b_enc480p.hw,
2242 [CLKID_RNG1] = &meson8b_rng1.hw,
2243 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
2244 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
2245 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
2246 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
2247 [CLKID_EDP] = &meson8b_edp.hw,
2248 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
2249 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
2250 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
2251 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
2252 [CLKID_MPLL0] = &meson8b_mpll0.hw,
2253 [CLKID_MPLL1] = &meson8b_mpll1.hw,
2254 [CLKID_MPLL2] = &meson8b_mpll2.hw,
2255 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
2256 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
2257 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
2258 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
2259 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
2260 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
2261 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
2262 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
2263 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
2264 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
2265 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
2266 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
2267 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
2268 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
2269 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
2270 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
2271 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
2272 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
2273 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
2274 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
2275 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
2276 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
2277 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
2278 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
2279 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
2280 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
2281 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
2282 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
2283 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
2284 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
2285 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
2286 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
2287 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
2288 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
2289 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
2290 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
2291 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
2292 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
2293 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
2294 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
2295 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
2296 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
2297 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
2298 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
2299 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
2300 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
2301 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
2302 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
2303 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
2304 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
2305 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
2306 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
2307 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
2308 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
2309 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
2310 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
2311 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
2312 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
2313 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
2314 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
2315 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
2316 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
2317 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
2318 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
2319 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
2320 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
2321 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
2322 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
2323 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
2324 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
2325 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
2326 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
2327 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
2328 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
2329 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
2330 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
2331 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
2332 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
2333 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
2334 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
2335 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
2336 [CLKID_MALI_0] = &meson8b_mali_0.hw,
2337 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
2338 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
2339 [CLKID_MALI_1] = &meson8b_mali_1.hw,
2340 [CLKID_MALI] = &meson8b_mali.hw,
2341 [CLK_NR_CLKS] = NULL,
2342 },
2343 .num = CLK_NR_CLKS,
2344};
2345
2160static struct clk_regmap *const meson8b_clk_regmaps[] = { 2346static struct clk_regmap *const meson8b_clk_regmaps[] = {
2161 &meson8b_clk81, 2347 &meson8b_clk81,
2162 &meson8b_ddr, 2348 &meson8b_ddr,
@@ -2558,9 +2744,14 @@ static void __init meson8b_clkc_init(struct device_node *np)
2558 return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data); 2744 return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
2559} 2745}
2560 2746
2747static void __init meson8m2_clkc_init(struct device_node *np)
2748{
2749 return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
2750}
2751
2561CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc", 2752CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
2562 meson8_clkc_init); 2753 meson8_clkc_init);
2563CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc", 2754CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
2564 meson8b_clkc_init); 2755 meson8b_clkc_init);
2565CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc", 2756CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
2566 meson8b_clkc_init); 2757 meson8m2_clkc_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 03:04:18 -0400